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| author | Hans de Goede <hdegoede@redhat.com> | 2015-08-15 11:58:03 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-31 08:43:41 +0200 |
| commit | 31c21471debbc9cec7466088da4fe2ee970d33b6 (patch) | |
| tree | b309bf8b5abfa016b81c4c695d80ade4337c42a3 | |
| parent | f62bfa56daf17e3e8fac85795196c0ffad42e444 (diff) | |
| download | u-boot-imx-31c21471debbc9cec7466088da4fe2ee970d33b6.zip u-boot-imx-31c21471debbc9cec7466088da4fe2ee970d33b6.tar.gz u-boot-imx-31c21471debbc9cec7466088da4fe2ee970d33b6.tar.bz2 | |
sunxi_nand_spl: Make sure the DMA controller is enabled
We use DMA for nand data transfers in the SPL, so make sure the DMA
controller is enabled.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
| -rw-r--r-- | board/sunxi/board.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index b76bb83..1ebd0a4 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -125,7 +125,13 @@ static void nand_clock_setup(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); +#ifdef CONFIG_MACH_SUN9I + setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); +#else + setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); +#endif setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); } |