ppc4xx: Remove sc3 board

As this board seems to be unmaintained for quite some time, and its
not moved to the generic board ingrastructure, lets remove it.

This will also enable us to remove the CONFIG_AUTOBOOT_DELAY_STR2
and CONFIG_AUTOBOOT_STOP_STR2 macros, as this sc3 board is the
only one using one of this macros. A removal patch will follow
soon.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Juergen Beisert <jbeisert@eurodsn.de>
Acked-by: Heiko Schocher <hs@denx.de>

13 files changed, 1 insertions, 1907 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
index b26ec2a..30e6c65 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
@@ -408,7 +408,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 }
 
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
+#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
 
 /*
  *As is these functs get called out of flash Not a horrible
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 89cb3e9..4d5954a 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -23,9 +23,6 @@ config TARGET_PCS440EP
 config TARGET_SBC405
 	bool "Support sbc405"
 
-config TARGET_SC3
-	bool "Support sc3"
-
 config TARGET_T3CORP
 	bool "Support t3corp"
 
@@ -202,7 +199,6 @@ source "board/pcs440ep/Kconfig"
 source "board/prodrive/alpr/Kconfig"
 source "board/prodrive/p3p440/Kconfig"
 source "board/sbc405/Kconfig"
-source "board/sc3/Kconfig"
 source "board/t3corp/Kconfig"
 source "board/xes/xpedite1000/Kconfig"
 source "board/xilinx/ml507/Kconfig"
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 5ea29cc..4c9c3ac 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -75,10 +75,6 @@
 extern int update_flash_size(int flash_size);
 #endif
 
-#if defined(CONFIG_SC3)
-extern void sc3_read_eeprom(void);
-#endif
-
 #if defined(CONFIG_CMD_DOC)
 void doc_init(void);
 #endif
@@ -791,10 +787,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif /* CONFIG_405GP, CONFIG_405EP */
 #endif /* CONFIG_SYS_EXTBDINFO */
 
-#if defined(CONFIG_SC3)
-	sc3_read_eeprom();
-#endif
-
 #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
 	mac_read_from_eeprom();
 #endif
diff --git a/board/sc3/Kconfig b/board/sc3/Kconfig
deleted file mode 100644
index 88a6d86..0000000
--- a/board/sc3/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SC3
-
-config SYS_BOARD
-	default "sc3"
-
-config SYS_CONFIG_NAME
-	default "sc3"
-
-endif
diff --git a/board/sc3/MAINTAINERS b/board/sc3/MAINTAINERS
deleted file mode 100644
index b86c6e6..0000000
--- a/board/sc3/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SC3 BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/sc3/
-F:	include/configs/sc3.h
-F:	configs/sc3_defconfig
diff --git a/board/sc3/Makefile b/board/sc3/Makefile
deleted file mode 100644
index c1d163e..0000000
--- a/board/sc3/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= sc3.o sc3nand.o
-obj-y	+= init.o
diff --git a/board/sc3/init.S b/board/sc3/init.S
deleted file mode 100644
index 097aa4a..0000000
--- a/board/sc3/init.S
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-/**
- * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
- *
- * IMPORTANT: For pass1 this code must run from cache since you can not
- * reliably change a peripheral banks timing register (pbxap) while running
- * code from that bank. For ex., since we are running from ROM on bank 0, we
- * can NOT execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- *
- * Bank 0 - Boot-Flash
- * Bank 1 - NAND-Flash
- * Bank 2 - ISA bus
- * Bank 3 - Second Flash
- * Bank 4 - USB controller
- */
-	.globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
-/*
- * We need the current boot up configuration to set correct
- * timings into internal flash and external flash
- */
-		mfdcr r24,CPC0_PSR		/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
-						   0 0 -> 8 bit external ROM
-						   0 1 -> 16 bit internal ROM */
-		addi r4,0,2
-		srw r24,r24,r4				/* shift right r24 two positions */
-		andi. r24,r24,0x06000
-/*
- * All calculations are based on 33MHz EBC clock.
- *
- * First, create a "very slow" timing (~250ns) with burst mode enabled
- * This is need for the external flash access
- */
-		lis r25,0x0800
-		/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
-		ori r25,r25,0x0280
-/*
- * Second, create a fast timing:
- * 90ns first cycle - 3 clock access
- * and 90ns burst cycle, plus 1 clock after the last access
- * This is used for the internal access
- */
-		lis r26,0x8900
-		/* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
-		ori r26,r26,0x0280
-/*
- * We can't change settings on CS# if we currently use them.
- * -> load a few instructions into cache and run this code from cache
- */
-		mflr r4					/* save link register */
-		bl ..getAddr
-..getAddr:
-		mflr r3					/* get address of ..getAddr */
-		mtlr r4					/* restore link register */
-		addi r4,0,14				/* set ctr to 10; used to prefetch */
-		mtctr r4				/* 10 cache lines to fit this function
-							in cache (gives us 8x10=80 instructions) */
-..ebcloop:
-		icbt r0,r3				/* prefetch cache line for addr in r3 */
-		addi r3,r3,32				/* move to next cache line */
-		bdnz ..ebcloop				/* continue for 10 cache lines */
-/*
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings. 200usec should be enough.
- * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- */
-		lis r3,0x0
-		ori r3,r3,0xA000			/* ensure 200usec have passed since reset */
-		mtctr r3
-..spinlp:
-		bdnz ..spinlp				/* spin loop */
-
-/*-----------------------------------------------------------------------
- * Memory Bank 0 (BOOT-ROM) initialization
- * 0xFFEF00000....0xFFFFFFF
- * We only have to change the timing. Mapping is ok by boot-strapping
- *----------------------------------------------------------------------- */
-
-		li r4,PB1AP				/* PB0AP=Peripheral Bank 0 Access Parameters */
-		mtdcr EBC0_CFGADDR,r4
-
-		mr r4,r26				/* assume internal fast flash is boot flash */
-		cmpwi r24,0x2000			/* assumption true? ... */
-		beq 1f					/* ...yes! */
-		mr r4,r25				/* ...no, use the slow variant */
-		mr r25,r26				/* use this for the other flash */
-1:
-		mtdcr EBC0_CFGDATA,r4			/* change timing now */
-
-		li r4,PB0CR				/* PB0CR=Peripheral Bank 0 Control Register */
-		mtdcr EBC0_CFGADDR,r4
-		mfdcr r4,EBC0_CFGDATA
-		lis r3,0x0001
-		ori r3,r3,0x8000			/* allow reads and writes */
-		or r4,r4,r3
-		mtdcr EBC0_CFGDATA,r4
-
-/*-----------------------------------------------------------------------
- * Memory Bank 3 (Second-Flash) initialization
- * 0xF0000000...0xF01FFFFF -> 2MB
- *----------------------------------------------------------------------- */
-
-		li r4,PB3AP				/* Peripheral Bank 1 Access Parameter */
-		mtdcr EBC0_CFGADDR,r4
-		mtdcr EBC0_CFGDATA,r2			/* change timing */
-
-		li r4,PB3CR				/* Peripheral Bank 1 Configuration Registers */
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0xF003
-		ori r4,r4,0x8000
-/*
- * Consider boot configuration
- */
-		xori r24,r24,0x2000			/* invert current bus width */
-		or r4,r4,r24
-		mtdcr EBC0_CFGDATA,r4
-
-/*-----------------------------------------------------------------------
- * Memory Bank 1 (NAND-Flash) initialization
- * 0x77D00000...0x77DFFFFF -> 1MB
- * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
- * - the setup time is 0ns
- * - the hold time is 15ns
- * ->
- *   - TWT = 0
- *   - CSN = 0
- *   - OEN = 0
- *   - WBN = 0
- *   - WBF = 0
- *   - TH  = 1
- * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
- *----------------------------------------------------------------------- */
-
-		li r4,PB1AP				/* Peripheral Bank 1 Access Parameter */
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0x0000
-		ori r4,r4,0x0200
-		mtdcr EBC0_CFGDATA,r4
-
-		li r4,PB1CR				/* Peripheral Bank 1 Configuration Registers */
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0x77D1
-		ori r4,r4,0x8000
-		mtdcr EBC0_CFGDATA,r4
-
-
-/* USB init (without acceleration) */
-#ifndef CONFIG_ISP1161_PRESENT
-		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
-		mtdcr EBC0_CFGADDR,r4
-		lis r4,0x0180
-		ori r4,r4,0x5940
-		mtdcr EBC0_CFGDATA,r4
-#endif
-
-/*-----------------------------------------------------------------------
- * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
- * 0x78000000...0x7BFFFFFF -> 64 MB
- * Wir arbeiten bei 33 MHz -> 30ns
- *-----------------------------------------------------------------------
-
- A7 (ppc notation) or A24 (standard notation) decides about
- the type of access:
- A7/A24=0 -> memory cycle
- A7/ /A24=1 -> I/O cycle
-*/
-		li r4,PB2AP				/* PB2AP=Peripheral Bank 2 Access Parameters */
-		mtdcr EBC0_CFGADDR,r4
-/*
- We emulate an ISA access
-
- 1. Address active
- 2. wait 0 EBC clocks -> CSN=0
- 3. set CS#
- 4. wait 0 EBC clock -> OEN/WBN=0
- 5. set OE#/WE#
- 6. wait 4 clocks (ca. 90ns) and for Ready signal
- 7. hold for 4 clocks -> TH=4
-*/
-
-#if 1
-/* faster access to isa-bus */
-		lis r4,0x0180
-		ori r4,r4,0x5940
-#else
-		lis r4,0x0100
-		ori r4,r4,0x0340
-#endif
-		mtdcr EBC0_CFGDATA,r4
-
-#ifdef IDE_USES_ISA_EMULATION
-		li r25,PB5AP				/* PB5AP=Peripheral Bank 5 Access Parameters */
-		mtdcr EBC0_CFGADDR,r25
-		mtdcr EBC0_CFGDATA,r4
-#endif
-
-		li r25,PB6AP				/* PB6AP=Peripheral Bank 6 Access Parameters */
-		mtdcr EBC0_CFGADDR,r25
-		mtdcr EBC0_CFGDATA,r4
-		li r25,PB7AP				/* PB7AP=Peripheral Bank 7 Access Parameters */
-		mtdcr EBC0_CFGADDR,r25
-		mtdcr EBC0_CFGDATA,r4
-
-		li r25,PB2CR				/* PB2CR=Peripheral Bank 2 Configuration Register */
-		mtdcr EBC0_CFGADDR,r25
-
-		lis r4,0x780B
-		ori r4,r4,0xA000
-		mtdcr EBC0_CFGDATA,r4
-/*
- * the other areas are only 1MiB in size
- */
-		lis r4,0x7401
-		ori r4,r4,0xA000
-
-		li r25,PB6CR				/* PB6CR=Peripheral Bank 6 Configuration Register */
-		mtdcr EBC0_CFGADDR,r25
-		lis r4,0x7401
-		ori r4,r4,0xA000
-		mtdcr EBC0_CFGDATA,r4
-
-		li r25,PB7CR				/* PB7CR=Peripheral Bank 7 Configuration Register */
-		mtdcr EBC0_CFGADDR,r25
-		lis r4,0x7411
-		ori r4,r4,0xA000
-		mtdcr EBC0_CFGDATA,r4
-
-#ifndef CONFIG_ISP1161_PRESENT
-		li r25,PB4CR				/* PB4CR=Peripheral Bank 4 Configuration Register */
-		mtdcr EBC0_CFGADDR,r25
-		lis r4,0x7421
-		ori r4,r4,0xA000
-		mtdcr EBC0_CFGDATA,r4
-#endif
-#ifdef IDE_USES_ISA_EMULATION
-		li r25,PB5CR				/* PB5CR=Peripheral Bank 5 Configuration Register */
-		mtdcr EBC0_CFGADDR,r25
-		lis r4,0x0000
-		ori r4,r4,0x0000
-		mtdcr EBC0_CFGDATA,r4
-#endif
-
-/*-----------------------------------------------------------------------
- * Memory bank 4: USB controller Philips ISP6111
- * 0x77C00000 ... 0x77CFFFFF
- *
- * The chip is connected to:
- * - CPU CS#4
- * - CPU IRQ#2
- * - CPU DMA 3
- *
- * Timing:
- * - command to first data: 300ns. Software must ensure this timing!
- * - Write pulse: 26ns
- * - Read pulse: 33ns
- * - read cycle time: 150ns
- * - write cycle time: 140ns
- *
- * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
- *
- *			  |- 300ns --|
- *		  |---- 420ns ---|---- 420ns ---| cycle
- * CS ############:###____#######:###____#######
- * OE ############:####___#######:####___#######
- * WE ############:####__########:####__########
- *
- * ----> 2 clocks RD/WR pulses: 60ns
- * ----> CSN: 3 clock, 90ns
- * ----> OEN: 1 clocks (read cycle)
- * ----> WBN: 1 clocks (write cycle)
- * ----> WBE: 2 clocks
- * ----> TH: 7 clock, 210ns
- * ----> TWT: 7 clocks
- *----------------------------------------------------------------------- */
-
-#ifdef CONFIG_ISP1161_PRESENT
-
-		li r4,PB4AP				/* PB4AP=Peripheral Bank 4 Access Parameters */
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0x030D
-		ori r4,r4,0x5E80
-		mtdcr EBC0_CFGDATA,r4
-
-		li r4,PB4CR				/* PB2CR=Peripheral Bank 4 Configuration Register */
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0x77C1
-		ori r4,r4,0xA000
-		mtdcr EBC0_CFGDATA,r4
-
-#endif
-
-#ifndef IDE_USES_ISA_EMULATION
-
-/*-----------------------------------------------------------------------
- * Memory Bank 5 used for IDE access
- *
- * Timings for IDE Interface
- *
- * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
- *  70		165		30		PIO-Mode 0, [ns]
- *   3		  6		 1		[Cycles] ----> AP=0x040C0200
- *  50		125		20	   PIO-Mode 1, [ns]
- *   2		  5		 1		[Cycles] ----> AP=0x03080200
- *  30		100		15	   PIO-Mode 2, [ns]
- *   1		  4		 1		[Cycles] ----> AP=0x02040200
- *  30		 80		10	   PIO-Mode 3, [ns]
- *   1		  3		 1		[Cycles] ----> AP=0x01840200
- *  25		 70		10	   PIO-Mode 4, [ns]
- *   1		  3		 1		[Cycles] ----> AP=0x01840200
- *
- *----------------------------------------------------------------------- */
-
-		li r4,PB5AP
-		mtdcr EBC0_CFGADDR,r4
-		lis r4,0x040C
-		ori r4,r4,0x0200
-		mtdcr EBC0_CFGDATA,r4
-
-		li r4,PB5CR			/* PB2CR=Peripheral Bank 2 Configuration Register */
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0x7A01
-		ori r4,r4,0xA000
-		mtdcr EBC0_CFGDATA,r4
-#endif
-/*
- * External Peripheral Control Register
- */
-		li r4,EBC0_CFG
-		mtdcr EBC0_CFGADDR,r4
-
-		lis r4,0xB84E
-		ori r4,r4,0xF000
-		mtdcr EBC0_CFGDATA,r4
-/*
- * drive POST code
- */
-		lis r4,0x7900
-		ori r4,r4,0x0080
-		li r3,0x0001
-		stb r3,0(r4)			/* 01 -> external bus controller is initialized */
-		nop				/* pass2 DCR errata #8 */
-		blr
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
deleted file mode 100644
index 0216a37..0000000
--- a/board/sc3/sc3.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
- *
- * (C) Copyright 2003
- * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
- * Derived from walnut.c
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "sc3.h"
-#include <pci.h>
-#include <i2c.h>
-#include <malloc.h>
-#include <netdev.h>
-
-#undef writel
-#undef writeb
-#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
-#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
-
-/* write only register to configure things in our CPLD */
-#define CPLD_CONTROL_1	0x79000102
-#define CPLD_VERSION	0x79000103
-
-#define	IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
-
-static struct pci_controller hose={0,};
-
-/************************************************************
- * Standard definition
- ************************************************************/
-
-/* CPC0_CR0        Function                                 ISA bus
-	-  GPIO0
-	-  GPIO1      -> Output: NAND-Command Latch Enable
-	-  GPIO2      -> Output: NAND Address Latch Enable
-	-  GPIO3      -> IRQ input                               ISA-IRQ #5 (through CPLD)
-	-  GPIO4      -> Output: NAND-Chip Enable
-	-  GPIO5      -> IRQ input                               ISA-IRQ#7 (through CPLD)
-	-  GPIO6      -> IRQ input                               ISA-IRQ#9 (through CPLD)
-	-  GPIO7      -> IRQ input                               ISA-IRQ#10 (through CPLD)
-	-  GPIO8      -> IRQ input                               ISA-IRQ#11 (through CPLD)
-	-  GPIO9      -> IRQ input                               ISA-IRQ#12 (through CPLD)
-	- GPIO10/CS1# -> CS1# NAND                               ISA-CS#0
-	- GPIO11/CS2# -> CS2# ISA emulation                      ISA-CS#1
-	- GPIO12/CS3# -> CS3# 2nd Flash-Bank                     ISA-CS#2 or ISA-CS#7
-	- GPIO13/CS4# -> CS4# USB HC or ISA emulation            ISA-CS#3
-	- GPIO14/CS5# -> CS5# Boosted IDE access                 ISA-CS#4
-	- GPIO15/CS6# -> CS6# ISA emulation                      ISA-CS#5
-	- GPIO16/CS7# -> CS7# ISA emulation                      ISA-CS#6
-	- GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line         ISA-IRQ#3
-	- GPIO18/IRQ1 -> IRQ input                               ISA-IRQ#14
-	- GPIO19/IRQ2 -> IRQ input or USB                        ISA-IRQ#4
-	- GPIO20/IRQ3 -> IRQ input                               PCI-IRQ#D
-	- GPIO21/IRQ4 -> IRQ input                               PCI-IRQ#C
-	- GPIO22/IRQ5 -> IRQ input                               PCI-IRQ#B
-	- GPIO23/IRQ6 -> IRQ input                               PCI-IRQ#A
-	- GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
-*/
-/*
-| CPLD register: io-space at offset 0x102 (write only)
-| 0
-| 1
-| 2 0=CS#4 USB CS#, 1=ISA or GP bus
-| 3
-| 4
-| 5
-| 6 1=enable faster IDE access
-| 7
-*/
-#define USB_CHIP_ENABLE 0x04
-#define IDE_BOOSTING 0x40
-
-/* --------------- USB stuff ------------------------------------- */
-#ifdef CONFIG_ISP1161_PRESENT
-/**
- * initUsbHost- Initialize the Philips isp1161 HC part if present
- * @cpldConfig: Pointer to value in write only CPLD register
- *
- * Initialize the USB host controller if present and fills the
- * scratch register to inform the driver about used resources
- */
-
-static void initUsbHost (unsigned char *cpldConfig)
-{
-	int i;
-	unsigned long usbBase;
-	/*
-	 * Read back where init.S has located the USB chip
-	 */
-	mtdcr (0x012, 0x04);
-	usbBase = mfdcr (0x013);
-	if (!(usbBase & 0x18000))	/* enabled? */
-		return;
-	usbBase &= 0xFFF00000;
-
-	/*
-	 * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
-	 */
-	writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
-
-	/*
-	 * first check: is the controller assembled?
-	 */
-	hcWriteWord (usbBase, 0x5555, HcScratch);
-	if (hcReadWord (usbBase, HcScratch) == 0x5555) {
-		hcWriteWord (usbBase, 0xAAAA, HcScratch);
-		if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
-			if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
-				return;	/* this is not our controller */
-		/*
-		 * try a software reset. This needs up to 10 seconds (see datasheet)
-		 */
-			hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
-			for (i = 1000; i > 0; i--) {	/* loop up to 10 seconds */
-				udelay (10);
-				if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
-					break;
-			}
-
-			if (!i)
-				return;  /* the controller doesn't responding. Broken? */
-		/*
-		 * OK. USB controller is ready. Initialize it in such way the later driver
-		 * can us it (without any knowing about specific implementation)
-		 */
-			hcWriteDWord (usbBase, 0x00000000, HcControl);
-		/*
-		 * disable all interrupt sources. Because we
-		 * don't know where we come from (hard reset, cold start, soft reset...)
-		 */
-			hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
-		/*
-		 * our current setup hardware configuration
-		 * - every port power supply can switched indepently
-		 * - every port can signal overcurrent
-		 * - every port is "outside" and the devices are removeable
-		 */
-			hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
-			hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
-		/*
-		 * don't forget to switch off power supply of each port
-		 * The later running driver can reenable them to find and use
-		 * the (maybe) connected devices.
-		 *
-		 */
-			hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
-			hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
-			hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
-			hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
-			hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
-			hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
-		/*
-		 * controller is present and usable
-		 */
-			*cpldConfig |= USB_CHIP_ENABLE;
-		}
-	}
-}
-#endif
-
-#if defined(CONFIG_START_IDE)
-int board_start_ide(void)
-{
-	if (IS_CAMERON) {
-		puts ("no IDE on cameron board.\n");
-		return 0;
-	}
-	return 1;
-}
-#endif
-
-static int sc3_cameron_init (void)
-{
-	/* Set up the Memory Controller for the CAMERON version */
-	mtebc (PB4AP, 0x01805940);
-	mtebc (PB4CR, 0x7401a000);
-	mtebc (PB5AP, 0x01805940);
-	mtebc (PB5CR, 0x7401a000);
-	mtebc (PB6AP, 0x0);
-	mtebc (PB6CR, 0x0);
-	mtebc (PB7AP, 0x0);
-	mtebc (PB7CR, 0x0);
-	return 0;
-}
-
-void sc3_read_eeprom (void)
-{
-	uchar i2c_buffer[18];
-
-	i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
-	i2c_buffer[9] = 0;
-	setenv ("serial#", (char *)i2c_buffer);
-
-	/* read mac-address from eeprom */
-	i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
-	i2c_buffer[17] = 0;
-	i2c_buffer[16] = i2c_buffer[14];
-	i2c_buffer[15] = i2c_buffer[13];
-	i2c_buffer[14] = ':';
-	i2c_buffer[13] = i2c_buffer[12];
-	i2c_buffer[12] = i2c_buffer[11];
-	i2c_buffer[11] = ':';
-	i2c_buffer[8] = ':';
-	i2c_buffer[5] = ':';
-	i2c_buffer[2] = ':';
-	setenv ("ethaddr", (char *)i2c_buffer);
-}
-
-int board_early_init_f (void)
-{
-	/* write only register to configure things in our CPLD */
-	unsigned char cpldConfig_1=0x00;
-
-/*-------------------------------------------------------------------------+
-| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
-|
-| Note: IRQ 0  UART 0, active high; level sensitive
-|       IRQ 1  UART 1, active high; level sensitive
-|       IRQ 2  IIC, active high; level sensitive
-|       IRQ 3  Ext. master, rising edge, edge sensitive
-|       IRQ 4  PCI, active high; level sensitive
-|       IRQ 5  DMA Channel 0, active high; level sensitive
-|       IRQ 6  DMA Channel 1, active high; level sensitive
-|       IRQ 7  DMA Channel 2, active high; level sensitive
-|       IRQ 8  DMA Channel 3, active high; level sensitive
-|       IRQ 9  Ethernet Wakeup, active high; level sensitive
-|       IRQ 10 MAL System Error (SERR), active high; level sensitive
-|       IRQ 11 MAL Tx End of Buffer, active high; level sensitive
-|       IRQ 12 MAL Rx End of Buffer, active high; level sensitive
-|       IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
-|       IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
-|       IRQ 15 Ethernet, active high; level sensitive
-|       IRQ 16 External PCI SERR, active high; level sensitive
-|       IRQ 17 ECC Correctable Error, active high; level sensitive
-|       IRQ 18 PCI Power Management, active high; level sensitive
-|
-|       IRQ 19 (EXT IRQ7 405GPr only)
-|       IRQ 20 (EXT IRQ8 405GPr only)
-|       IRQ 21 (EXT IRQ9 405GPr only)
-|       IRQ 22 (EXT IRQ10 405GPr only)
-|       IRQ 23 (EXT IRQ11 405GPr only)
-|       IRQ 24 (EXT IRQ12 405GPr only)
-|
-|       IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
-|       IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
-|       IRQ 27 (EXT IRQ 2) USB controller
-|       IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
-|       IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
-|       IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
-|       IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
-|
-| Direct Memory Access Controller Signal Polarities
-|       DRQ0 active high (like ISA)
-|       ACK0 active low (like ISA)
-|       EOT0 active high (like ISA)
-|       DRQ1 active high (like ISA)
-|       ACK1 active low (like ISA)
-|       EOT1 active high (like ISA)
-|       DRQ2 active high (like ISA)
-|       ACK2 active low (like ISA)
-|       EOT2 active high (like ISA)
-|       DRQ3 active high (like ISA)
-|       ACK3 active low (like ISA)
-|       EOT3 active high (like ISA)
-|
-+-------------------------------------------------------------------------*/
-
-	writeb (cpldConfig_1, CPLD_CONTROL_1);	/* disable everything in CPLD */
-
-	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
-
-	if (IS_CAMERON) {
-		sc3_cameron_init();
-		mtdcr (0x0B6, 0x18000000);
-		mtdcr (UIC0PR, 0xFFFFFFF0);
-		mtdcr (UIC0TR, 0x10001030);
-	} else {
-		mtdcr (0x0B6, 0x0000000);
-		mtdcr (UIC0PR, 0xFFFFFFE0);
-		mtdcr (UIC0TR, 0x10000020);
-	}
-	mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
-
-	/* setup other implementation specific details */
-	mtdcr (CPC0_ECR, 0x60606000);
-
-	mtdcr (CPC0_CR1, 0x000042C0);
-
-	if (IS_CAMERON) {
-		mtdcr (CPC0_CR0, 0x01380000);
-		/* Setup the GPIOs */
-		writel (0x08008000, 0xEF600700);	/* Output states */
-		writel (0x00000000, 0xEF600718);	/* Open Drain control */
-		writel (0x68098000, 0xEF600704);	/* Output control */
-	} else {
-		mtdcr (CPC0_CR0,0x00080000);
-		/* Setup the GPIOs */
-		writel (0x08000000, 0xEF600700);	/* Output states */
-		writel (0x14000000, 0xEF600718);	/* Open Drain control */
-		writel (0x7C000000, 0xEF600704);	/* Output control */
-	}
-
-	/* Code decompression disabled */
-	mtdcr (DCP0_CFGADDR, KCONF);
-	mtdcr (DCP0_CFGDATA, 0x2B);
-
-	/* CPC0_ER: enable sleep mode of (currently) unused components */
-	/* CPC0_FR: force unused components into sleep mode */
-	mtdcr (CPC0_ER, 0x3F800000);
-	mtdcr (CPC0_FR, 0x14000000);
-
-	/* set PLB priority */
-	mtdcr (PLB0_ACR, 0x08000000);
-
-	/* --------------- DMA stuff ------------------------------------- */
-	mtdcr (0x126, 0x49200000);
-
-#ifndef IDE_USES_ISA_EMULATION
-	cpldConfig_1 |= IDE_BOOSTING;	/* enable faster IDE */
-	/* cpldConfig |= 0x01; */	/* enable 8.33MHz output, if *not* present on your baseboard */
-	writeb (cpldConfig_1, CPLD_CONTROL_1);
-#endif
-
-#ifdef CONFIG_ISP1161_PRESENT
-	initUsbHost (&cpldConfig_1);
-	writeb (cpldConfig_1, CPLD_CONTROL_1);
-#endif
-	/* FIXME: for what must we do this */
-	*(unsigned long *)0x79000080 = 0x0001;
-	return(0);
-}
-
-int misc_init_r (void)
-{
-	char *s1;
-	int i, xilinx_val;
-	volatile char *xilinx_adr;
-	xilinx_adr = (char *)0x79000102;
-
-	*xilinx_adr = 0x00;
-
-/* customer settings ***************************************** */
-/*
-	s1 = getenv ("function");
-	if (s1) {
-		if (!strcmp (s1, "Rosho")) {
-			printf ("function 'Rosho' activated\n");
-			*xilinx_adr = 0x40;
-		}
-		else {
-			printf (">>>>>>>>>> function %s not recognized\n",s1);
-		}
-	}
-*/
-
-/* individual settings ***************************************** */
-	if ((s1 = getenv ("xilinx"))) {
-		i=0;
-		xilinx_val = 0;
-		while (i < 3 && s1[i]) {
-			if (s1[i] >= '0' && s1[i] <= '9')
-				xilinx_val = (xilinx_val << 4) + s1[i] - '0';
-			else
-				if (s1[i] >= 'A' && s1[i] <= 'F')
-					xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
-				else
-					if (s1[i] >= 'a' && s1[i] <= 'f')
-						xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
-					else {
-						xilinx_val = -1;
-						break;
-					}
-			i++;
-		}
-		if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
-			printf ("Xilinx: set to %s\n", s1);
-			*xilinx_adr = (unsigned char) xilinx_val;
-		} else
-			printf ("Xilinx: rejected value %s\n", s1);
-	}
-	return 0;
-}
-
-/* -------------------------------------------------------------------------
- * printCSConfig
- *
- * Print some informations about chips select configurations
- * Only used while debugging.
- *
- * Params:
- * - No. of CS pin
- * - AP of this CS
- * - CR of this CS
- *
- * Returns
- * nothing
-   ------------------------------------------------------------------------- */
-
-#ifdef SC3_DEBUGOUT
-static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
-{
-	const char *bsize[4] = {"8","16","32","?"};
-	const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
-	const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
-
-#define CYCLE 30  /* time of one clock (based on 33MHz) */
-
-	printf("\nCS#%d",reg);
-	if (!(cr & 0x00018000))
-		puts(" unused");
-	else {
-		if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
-			puts(" Address is not multiple of bank size!");
-
-		printf("\n -%s bit device",
-			bsize[(cr & 0x00006000) >> 13]);
-		printf(" at 0x%08lX", cr & 0xFFF00000U);
-		printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
-		printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
-		if (ap & 0x80000000) {
-			printf("\n -Burst device (%luns/%luns)",
-				(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
-				(((ap & 0x03800000) >> 23) + 1) * CYCLE);
-		} else {
-			printf("\n -Non burst device, active cycle %luns",
-				(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
-			printf("\n -Address setup %luns",
-				((ap & 0xC0000) >> 18) * CYCLE);
-			printf("\n -CS active to RD %luns/WR %luns",
-				((ap & 0x30000) >> 16) * CYCLE,
-				((ap & 0xC000) >> 14) * CYCLE);
-			printf("\n -WR to CS inactive %luns",
-				((ap & 0x3000) >> 12) * CYCLE);
-			printf("\n -Hold after access %luns",
-				((ap & 0xE00) >> 9) * CYCLE);
-			printf("\n -Ready is %sabled",
-				ap & 0x100 ? "en" : "dis");
-		}
-	}
-}
-#endif
-
-#ifdef SC3_DEBUGOUT
-
-static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
-				PB5AP, PB6AP, PB7AP};
-static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
-				PB5CR, PB6CR, PB7CR};
-
-static int show_reg (int nr)
-{
-	unsigned long ul1, ul2;
-
-	mtdcr (EBC0_CFGADDR, ap[nr]);
-	ul1 = mfdcr (EBC0_CFGDATA);
-	mtdcr (EBC0_CFGADDR, cr[nr]);
-	ul2 = mfdcr(EBC0_CFGDATA);
-	printCSConfig(nr, ul1, ul2);
-	return 0;
-}
-#endif
-
-int checkboard (void)
-{
-#ifdef SC3_DEBUGOUT
-	unsigned long ul1;
-	int	i;
-
-	for (i = 0; i < 8; i++) {
-		show_reg (i);
-	}
-
-	mtdcr (EBC0_CFGADDR, EBC0_CFG);
-	ul1 = mfdcr (EBC0_CFGDATA);
-
-	puts ("\nGeneral configuration:\n");
-
-	if (ul1 & 0x80000000)
-		printf(" -External Bus is always driven\n");
-
-	if (ul1 & 0x400000)
-		printf(" -CS signals are always driven\n");
-
-	if (ul1 & 0x20000)
-		printf(" -PowerDown after %lu clocks\n",
-			(ul1 & 0x1F000) >> 7);
-
-	switch (ul1 & 0xC0000)
-	{
-	case 0xC0000:
-		printf(" -No external master present\n");
-		break;
-	case 0x00000:
-		printf(" -8 bit external master present\n");
-		break;
-	case 0x40000:
-		printf(" -16 bit external master present\n");
-		break;
-	case 0x80000:
-		printf(" -32 bit external master present\n");
-		break;
-	}
-
-	switch (ul1 & 0x300000)
-	{
-	case 0x300000:
-		printf(" -Prefetch: Illegal setting!\n");
-		break;
-	case 0x000000:
-		printf(" -1 doubleword prefetch\n");
-		break;
-	case 0x100000:
-		printf(" -2 doublewords prefetch\n");
-		break;
-	case 0x200000:
-		printf(" -4 doublewords prefetch\n");
-		break;
-	}
-	putc ('\n');
-#endif
-	printf("Board: SolidCard III %s %s version.\n",
-		(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
-	return 0;
-}
-
-static int printSDRAMConfig(char reg, unsigned long cr)
-{
-	const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
-#ifdef SC3_DEBUGOUT
-	const char *basize[8]=
-		{"4", "8", "16", "32", "64", "128", "256", "Reserved"};
-
-	printf("SDRAM bank %d",reg);
-
-	if (!(cr & 0x01))
-		puts(" disabled\n");
-	else {
-		printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
-		printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
-	}
-#endif
-
-	if (cr & 0x01)
-		return(bisize[(cr & 0xE0000) >> 17]);
-
-	return 0;
-}
-
-#ifdef SC3_DEBUGOUT
-static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
-#endif
-
-phys_size_t initdram (int board_type)
-{
-	unsigned int mems=0;
-	unsigned long ul1;
-
-#ifdef SC3_DEBUGOUT
-	unsigned long ul2;
-	int	i;
-
-	puts("\nSDRAM configuration:\n");
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-	ul1 = mfdcr(SDRAM0_CFGDATA);
-
-	if (!(ul1 & 0x80000000)) {
-		puts(" Controller disabled\n");
-		return 0;
-	}
-	for (i = 0; i < 4; i++) {
-		mtdcr (SDRAM0_CFGADDR, mbcf[i]);
-		ul1 = mfdcr (SDRAM0_CFGDATA);
-		mems += printSDRAMConfig (i, ul1);
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
-	ul1 = mfdcr(SDRAM0_CFGDATA);
-
-	printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
-	printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
-	printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
-	printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
-	printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
-	printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
-	puts ("Misc:\n");
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
-	ul1 = mfdcr(SDRAM0_CFGDATA);
-	printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
-
-	mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
-	ul2=mfdcr(SDRAM0_CFGDATA);
-
-	mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
-	ul1=mfdcr(SDRAM0_CFGDATA);
-
-	if (ul1 & 0x20000000)
-		printf(" -Power Down after: %luns\n",
-			((ul2 & 0xFFC00000) >> 22) * 7);
-	else
-		puts(" -Power Down disabled\n");
-
-	if (ul1 & 0x40000000)
-		printf(" -Self refresh feature active\n");
-	else
-		puts(" -Self refresh disabled\n");
-
-	if (ul1 & 0x10000000)
-		puts(" -ECC enabled\n");
-	else
-		puts(" -ECC disabled\n");
-
-	if (ul1 & 0x8000000)
-		puts(" -Using registered SDRAM\n");
-
-	if (!(ul1 & 0x6000000))
-		puts(" -Using 32 bit data width\n");
-	else
-		puts(" -Illegal data width!\n");
-
-	if (ul1 & 0x400000)
-		puts(" -ECC drivers inactive\n");
-	else
-		puts(" -ECC drivers active\n");
-
-	if (ul1 & 0x200000)
-		puts(" -Memory lines always active outputs\n");
-	else
-		puts(" -Memory lines only at write cycles active outputs\n");
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
-	ul1 = mfdcr (SDRAM0_CFGDATA);
-	if (ul1 & 0x80000000)
-		puts(" -SDRAM Controller ready\n");
-	else
-		puts(" -SDRAM Controller not ready\n");
-
-	if (ul1 & 0x4000000)
-		puts(" -SDRAM in self refresh mode!\n");
-
-	return (mems * 1024 * 1024);
-#else
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	ul1 = mfdcr (SDRAM0_CFGDATA);
-	mems = printSDRAMConfig (0, ul1);
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	ul1 = mfdcr (SDRAM0_CFGDATA);
-	mems += printSDRAMConfig (1, ul1);
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	ul1 = mfdcr(SDRAM0_CFGDATA);
-	mems += printSDRAMConfig (2, ul1);
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	ul1 = mfdcr(SDRAM0_CFGDATA);
-	mems += printSDRAMConfig (3, ul1);
-
-	return (mems * 1024 * 1024);
-#endif
-}
-
-static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
-/*-------------------------------------------------------------------------+
- |             ,-.     ,-.        ,-.        ,-.        ,-.
- |   INTD# ----|B|-----|P|-.    ,-|P|-.    ,-| |-.    ,-|G|
- |             |R|     |C|  \  /  |C|  \  /  |E|  \  /  |r|
- |   INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
- |             |D|     |0|  \/    |0|  \/    |h|  \/    |f|
- |   INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
- |             |E|     |+| /\     |+| /\     |r| /\     |k|
- |   INTA# ----| |-----| |-  `----| |-  `----| |-  `----| |
- |             `-'     `-'        `-'        `-'        `-'
- |   Slot      0       10         11         12         13
- |   REQ#              0          1          2          *
- |   GNT#              0          1          2          *
- +-------------------------------------------------------------------------*/
-	unsigned char int_line = 0xff;
-
-	switch (PCI_DEV(dev)) {
-	case 10:
-		int_line = 31; /* INT A */
-		POST_OUT(0x42);
-		break;
-
-	case 11:
-		int_line = 30; /* INT B */
-		POST_OUT(0x43);
-		break;
-
-	case 12:
-		int_line = 29; /* INT C */
-		POST_OUT(0x44);
-		break;
-
-	case 13:
-		int_line = 28; /* INT D */
-		POST_OUT(0x45);
-		break;
-	}
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-}
-
-extern void pci_405gp_init(struct pci_controller *hose);
-extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
-extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
-/*
- * The following table is used when there is a special need to setup a PCI device.
- * For every PCI device found in this table is called the given init function with given
- * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
- * parameters!
- *
-*/
-static struct pci_config_table pci_solidcard3_config_table[] =
-{
-/* Host to PCI Bridge device (405GP) */
-	{
-		vendor: 0x1014,
-		device: 0x0156,
-		class: PCI_CLASS_BRIDGE_HOST,
-		bus: 0,
-		dev: 0,
-		func: 0,
-		config_device: pci_405gp_setup_bridge
-	},
-	{ }
-};
-
-/*-------------------------------------------------------------------------+
- | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
- |
- | Init the PCI part of the SolidCard III
- |
- | Params:
- * - Pointer to current PCI hose
- * - Current Device
- *
- * Returns
- * nothing
- +-------------------------------------------------------------------------*/
-
-void pci_init_board(void)
-{
-	POST_OUT(0x41);
-/*
- * we want the ptrs to RAM not flash (ie don't use init list)
- */
-	hose.fixup_irq    = pci_solidcard3_fixup_irq;
-	hose.config_table = pci_solidcard3_config_table;
-	pci_405gp_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/sc3/sc3.h b/board/sc3/sc3.h
deleted file mode 100644
index 7178cd0..0000000
--- a/board/sc3/sc3.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/**
- * hcWriteWord - write a 16 bit value into the USB controller
- * @base: base address to access the chip registers
- * @value: 16 bit value to write into register @offset
- * @offset: register to write the @value into
- *
- */
-static void inline hcWriteWord (unsigned long base, unsigned int value,
-				unsigned int offset)
-{
-	out_le16 ((volatile u16*)(base + 2), offset | 0x80);
-	out_le16 ((volatile u16*)base, value);
-}
-
-/**
- * hcWriteDWord - write a 32 bit value into the USB controller
- * @base: base address to access the chip registers
- * @value: 32 bit value to write into register @offset
- * @offset: register to write the @value into
- *
- */
-
-static void inline hcWriteDWord (unsigned long base, unsigned long value,
-				unsigned int offset)
-{
-	out_le16 ((volatile u16*)(base + 2), offset | 0x80);
-	out_le16 ((volatile u16*)base, value);
-	out_le16 ((volatile u16*)base, value >> 16);
-}
-
-/**
- * hcReadWord - read a 16 bit value from the USB controller
- * @base: base address to access the chip registers
- * @offset: register to read from
- *
- * Returns the readed register value
- */
-
-static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
-{
-	out_le16 ((volatile u16*)(base + 2), offset);
-	return (in_le16 ((volatile u16*)base));
-}
-
-/**
- * hcReadDWord - read a 32 bit value from the USB controller
- * @base: base address to access the chip registers
- * @offset: register to read from
- *
- * Returns the readed register value
- */
-
-static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
-{
-	unsigned long val, val16;
-
-	out_le16 ((volatile u16*)(base + 2), offset);
-	val = in_le16((volatile u16*)base);
-	val16 = in_le16((volatile u16*)base);
-	return (val | (val16 << 16));
-}
-
-/* control and status registers isp1161 */
-#define HcRevision		0x00
-#define HcControl		0x01
-#define HcCommandStatus		0x02
-#define HcInterruptStatus	0x03
-#define HcInterruptEnable	0x04
-#define HcInterruptDisable	0x05
-#define HcFmInterval		0x0D
-#define HcFmRemaining		0x0E
-#define HcFmNumber		0x0F
-#define HcLSThreshold		0x11
-#define HcRhDescriptorA		0x12
-#define HcRhDescriptorB		0x13
-#define HcRhStatus		0x14
-#define HcRhPortStatus1		0x15
-#define HcRhPortStatus2		0x16
-
-#define HcHardwareConfiguration 0x20
-#define HcDMAConfiguration	0x21
-#define HcTransferCounter	0x22
-#define HcuPInterrupt		0x24
-#define HcuPInterruptEnable	0x25
-#define HcChipID		0x27
-#define HcScratch		0x28
-#define HcSoftwareReset		0x29
-#define HcITLBufferLength	0x2A
-#define HcATLBufferLength	0x2B
-#define HcBufferStatus		0x2C
-#define HcReadBackITL0Length	0x2D
-#define HcReadBackITL1Length	0x2E
-#define HcITLBufferPort		0x40
-#define HcATLBufferPort		0x41
diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c
deleted file mode 100644
index a26cd79..0000000
--- a/board/sc3/sc3nand.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <asm/processor.h>
-
-#define readb(addr)	*(volatile u_char *)(addr)
-#define readl(addr)	*(volatile u_long *)(addr)
-#define writeb(d,addr)	*(volatile u_char *)(addr) = (d)
-
-#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
-#define SC3_NAND_CLE 30	/* GPIO PIN 2 */
-#define SC3_NAND_CE  27 /* GPIO PIN 5 */
-
-static void *sc3_io_base;
-static void *sc3_control_base = (void *)0xEF600700;
-
-static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			set_bit (SC3_NAND_CLE, sc3_control_base);
-		else
-			clear_bit (SC3_NAND_CLE, sc3_control_base);
-		if ( ctrl & NAND_ALE )
-			set_bit (SC3_NAND_ALE, sc3_control_base);
-		else
-			clear_bit (SC3_NAND_ALE, sc3_control_base);
-		if ( ctrl & NAND_NCE )
-			set_bit (SC3_NAND_CE, sc3_control_base);
-		else
-			clear_bit (SC3_NAND_CE, sc3_control_base);
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static int sc3_nand_dev_ready(struct mtd_info *mtd)
-{
-	if (!(readl(sc3_control_base + 0x1C) & 0x4000))
-		return 0;
-	return 1;
-}
-
-static void sc3_select_chip(struct mtd_info *mtd, int chip)
-{
-	clear_bit (SC3_NAND_CE, sc3_control_base);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	nand->ecc.mode = NAND_ECC_SOFT;
-
-	sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
-	/* Set address of NAND IO lines (Using Linear Data Access Region) */
-	nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
-	nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
-	/* Reference hardware control function */
-	nand->cmd_ctrl  = sc3_nand_hwcontrol;
-	nand->dev_ready  = sc3_nand_dev_ready;
-	nand->select_chip = sc3_select_chip;
-	return 0;
-}
-#endif
diff --git a/common/board_r.c b/common/board_r.c
index 1a46f62..bf6c725 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -480,17 +480,6 @@ static int initr_malloc_bootparams(void)
 }
 #endif
 
-#ifdef CONFIG_SC3
-/* TODO: with new initcalls, move this into the driver */
-extern void sc3_read_eeprom(void);
-
-static int initr_sc3_read_eeprom(void)
-{
-	sc3_read_eeprom();
-	return 0;
-}
-#endif
-
 static int initr_jumptable(void)
 {
 	jumptable_init();
@@ -804,9 +793,6 @@ init_fnc_t init_sequence_r[] = {
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 	initr_secondary_cpu,
-#ifdef CONFIG_SC3
-	initr_sc3_read_eeprom,
-#endif
 #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
 	mac_read_from_eeprom,
 #endif
diff --git a/configs/sc3_defconfig b/configs/sc3_defconfig
deleted file mode 100644
index e77b04c..0000000
--- a/configs/sc3_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_SC3=y
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
deleted file mode 100644
index 14e033d..0000000
--- a/include/configs/sc3.h
+++ /dev/null
@@ -1,549 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
- *
- * From:
- * (C) Copyright 2003
- * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef USE_VGA_GRAPHICS
-
-/* Memory Map
- * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
- * 0x74000000 .... 0x740FFFFF -> CS#6
- * 0x74100000 .... 0x741FFFFF -> CS#7
- * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
- * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
- * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
- * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
- * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
- * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
- * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
- * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
- *
- * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
- * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
- * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
- * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
- * 0xEED00000 .... 0xEED00003 -> PCI-Bus
- * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
- * 0xEF40003F .... 0xEF5FFFFF -> reserved
- * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
- * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
- * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
- * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
- * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
- * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
- */
-
-#define CONFIG_SC3	1
-#define CONFIG_405GP	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
-
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r() */
-
-/*
- * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
- * If undefined, IDE access uses a seperat emulation with higher access speed.
- * Consider to inform your Linux IDE driver about the different addresses!
- * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
- */
-#define IDE_USES_ISA_EMULATION
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-/*
- * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
- */
-#define CONFIG_SYS_CLK_FREQ	33333333
-
-/*
- * define CONFIG_BAUDRATE to the baudrate value you want to use as default
- */
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3 /* autoboot after 3 seconds	      */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nand_args=setenv bootargs root=/dev/mtdblock5 rw"		\
-		"rootfstype=jffs2\0"					\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addcons=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate}\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0"	\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/sc3/uImage\0"				\
-	"u-boot=/tftpboot/sc3/u-boot.bin\0"				\
-	"setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0"	\
-	"kernel_addr=FFE08000\0"					\
-	""
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_SILENT_CONSOLE	1	/* enable silent startup */
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#if 1	/* feel free to disable for development */
-#define CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
-#define CONFIG_AUTOBOOT_PROMPT		\
-	"\nSC3 - booting... stop with ENTER\n"
-#define CONFIG_AUTOBOOT_DELAY_STR	"\r"	/* 1st "password"	*/
-#define CONFIG_AUTOBOOT_DELAY_STR2	"\n"	/* 1st "password"	*/
-#endif
-
-/*
- * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
- * the CONFIG_BOOTDELAY delay to boot your machine
- */
-#define CONFIG_BOOTCOMMAND	"bootp;dcache on;bootm"
-
-/*
- * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
- * set different values at the u-boot prompt
- */
-#ifdef USE_VGA_GRAPHICS
- #define CONFIG_BOOTARGS	"root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
-#else
- #define CONFIG_BOOTARGS	"console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
-#endif
-/*
- * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
- * This reserves memory bank #4 for this purpose
- */
-#undef CONFIG_ISP1161_PRESENT
-
-#undef CONFIG_LOADS_ECHO   /* no echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-/* #define CONFIG_EEPRO100_SROM_WRITE */
-/* #define CONFIG_SHOW_MAC */
-#define CONFIG_EEPRO100
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1			/* add 405GP MII PHY management		*/
-#define CONFIG_PHY_ADDR 1	/* the connected Phy defaults to address 1 */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SOURCE
-
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP	1		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- *    baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- *
- * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
- * (see 405GP datasheet for descritpion)
- */
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
-#undef	CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
-#define CONFIG_SYS_BASE_BAUD		921600	/* internal clock */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR		0x1000000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-/*-----------------------------------------------------------------------
- * IIC stuff
- *-----------------------------------------------------------------------
- */
-#define  CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-
-#define I2C_INIT
-#define I2C_ACTIVE 0
-#define I2C_TRISTATE 0
-
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* mask valid bits */
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-/* If you want to see, whats connected to your PCI bus */
-/* #define CONFIG_PCI_SCAN_SHOW */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#if !defined(CONFIG_CMD_IDE)
-
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#else
-#define CONFIG_START_IDE	1	/* check, if use IDE */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
-
-#define	CONFIG_ATAPI
-#define	CONFIG_DOS_PARTITION
-#define	CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#ifndef IDE_USES_ISA_EMULATION
-
-/* New and faster access */
-#define	CONFIG_SYS_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
-
-/* How many IDE busses are available */
-#define	CONFIG_SYS_IDE_MAXBUS		1
-
-/* What IDE ports are available */
-#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x000		/* first is available */
-#undef	CONFIG_SYS_ATA_IDE1_OFFSET			/* second not available */
-
-/* access to the data port is calculated:
-   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
-
-/* access to the registers is calculated:
-   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
-#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-
-/* access to the alternate register is calculated:
-   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
-
-#else /* IDE_USES_ISA_EMULATION */
-
-#define	CONFIG_SYS_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
-
-/* How many IDE busses are available */
-#define	CONFIG_SYS_IDE_MAXBUS		1
-
-/* What IDE ports are available */
-#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* first is available */
-#undef	CONFIG_SYS_ATA_IDE1_OFFSET				/* second not available */
-
-/* access to the data port is calculated:
-   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
-
-/* access to the registers is calculated:
-   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
-#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
-
-/* access to the alternate register is calculated:
-   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
-
-#endif /* IDE_USES_ISA_EMULATION */
-
-#endif
-
-/*
-#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
-#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
-#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
-*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * CONFIG_SYS_FLASH_BASE   -> start address of internal flash
- * CONFIG_SYS_MONITOR_BASE -> start of u-boot
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFE00000
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
-#define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MiB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization ## FIXME: lookup in datasheet
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_CFI			/* flash is CFI compat.	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CONFIG_SYS_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET		0x00000000  /* Offset of Environment Sector in bottom type */
-#define CONFIG_ENV_SIZE		0x4000	    /* Total Size of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	0x4000	    /* see README - env sector total size	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#endif
-/* let us changing anything in our environment */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * NAND-FLASH stuff
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0x77D00000
-
-#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
-
-/* No command line, one static partition */
-#undef	CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nand0"
-#define CONFIG_JFFS2_PART_SIZE		0x01000000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/*
- * Init Memory Controller:
- *
- */
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define FLASH_BASE1_PRELIM	0
-
-/*-----------------------------------------------------------------------
- * Some informations about the internal SRAM (OCM=On Chip Memory)
- *
- * CONFIG_SYS_OCM_DATA_ADDR -> location
- * CONFIG_SYS_OCM_DATA_SIZE -> size
-*/
-
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM):
- * - we are using the internal 4k SRAM, so we don't need data cache mapping
- * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
- * - Stackpointer will be located to
- *   (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
- *   in arch/powerpc/cpu/ppc4xx/start.S
- */
-
-#undef CONFIG_SYS_INIT_DCACHE_CS
-/* Where the internal SRAM starts */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
-/* Where the internal SRAM ends (only offset) */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x0F00
-
-/*
-
- CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address
-			   |	      |
-			   |  ^       |
-			   |  |       |
-			   |  | Stack |
- CONFIG_SYS_GBL_DATA_OFFSET ----> ------------
-			   |	      |
-			   | 64 Bytes |
-			   |	      |
- CONFIG_SYS_INIT_RAM_SIZE  ------> ------------ higher address
-  (offset only)
-
-*/
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* Initial value of the stack pointern in internal SRAM */
-#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
-
-/* ################################################################################### */
-/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects  */
-/* They are currently undefined cause they are initiaized in board/solidcard3/init.S   */
-
-/* This chip select accesses the boot device */
-/* It depends on boot select switch if this device is 16 or 8 bit */
-
-#undef CONFIG_SYS_EBC_PB0AP
-#undef CONFIG_SYS_EBC_PB0CR
-
-#undef CONFIG_SYS_EBC_PB1AP
-#undef CONFIG_SYS_EBC_PB1CR
-
-#undef CONFIG_SYS_EBC_PB2AP
-#undef CONFIG_SYS_EBC_PB2CR
-
-#undef CONFIG_SYS_EBC_PB3AP
-#undef CONFIG_SYS_EBC_PB3CR
-
-#undef CONFIG_SYS_EBC_PB4AP
-#undef CONFIG_SYS_EBC_PB4CR
-
-#undef CONFIG_SYS_EBC_PB5AP
-#undef CONFIG_SYS_EBC_PB5CR
-
-#undef CONFIG_SYS_EBC_PB6AP
-#undef CONFIG_SYS_EBC_PB6CR
-
-#undef CONFIG_SYS_EBC_PB7AP
-#undef CONFIG_SYS_EBC_PB7CR
-
-#define CONFIG_SYS_EBC_CFG    0xb84ef000
-
-#undef CONFIG_SDRAM_BANK0	/* use private SDRAM initialization */
-#undef CONFIG_SPD_EEPROM
-
-/*
- * Define this to get more information about system configuration
- */
-/* #define SC3_DEBUGOUT */
-#undef SC3_DEBUGOUT
-
-/***********************************************************************
- * External peripheral base address
- ***********************************************************************/
-
-#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000
-/*
- Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
- Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
- das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
- auf ISA- und PCI-Zyklen)
- */
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0xE8000000
-/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0x79000000 */
-
-/************************************************************
- * Video support
- ************************************************************/
-
-#ifdef USE_VGA_GRAPHICS
-#define CONFIG_VIDEO		/* To enable video controller support */
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
-/* #define CONFIG_VIDEO_LOGO */
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-/* #define CONFIG_VIDEO_HW_CURSOR */
-#define CONFIG_VIDEO_ONBOARD	/* Video controller is on-board */
-
-#define VIDEO_HW_RECTFILL
-#define VIDEO_HW_BITBLT
-
-#endif
-
-/************************************************************
- * Ident
- ************************************************************/
-#define CONFIG_SC3_VERSION "r1.4"
-
-#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
-
-#endif	/* __CONFIG_H */