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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-02 21:11:34 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-14 16:36:13 +0900 |
| commit | 233812a64274e80f1a7b291653fa9d341a326ebd (patch) | |
| tree | c5d11e8f53ad6cf6e856a632a490b743becb958f | |
| parent | cc33609546e1e4c6c7bb59026eca7463765be61e (diff) | |
| download | u-boot-imx-233812a64274e80f1a7b291653fa9d341a326ebd.zip u-boot-imx-233812a64274e80f1a7b291653fa9d341a326ebd.tar.gz u-boot-imx-233812a64274e80f1a7b291653fa9d341a326ebd.tar.bz2 | |
ARM: dts: uniphier: add device nodes for System Control blocks
These are mainly used for controlling clocks and resets.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | arch/arm/dts/uniphier-common32.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm/dts/uniphier-ph1-ld4.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/dts/uniphier-ph1-pro4.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/dts/uniphier-ph1-pro5.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm/dts/uniphier-ph1-sld8.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/dts/uniphier-proxstream2.dtsi | 4 |
7 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index de04de1..d3e5a74 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -101,6 +101,14 @@ reg = <0x5f801000 0xe00>; }; + sysctrl: sysctrl@61840000 { + /* specify compatible in each SoC DTSI */ + reg = <0x61840000 0x4000>; + #clock-cells = <1>; + clock-names = "ref"; + clocks = <&refclk>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 6f15978..6bd4b91 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -160,3 +160,7 @@ &pinctrl { compatible = "socionext,ph1-ld4-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-ld4-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index a236dbc..984f99c 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -200,3 +200,7 @@ &pinctrl { compatible = "socionext,ph1-pro4-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-pro4-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 120767c..a836176 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -194,3 +194,7 @@ &pinctrl { compatible = "socionext,ph1-pro5-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-pro5-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 9ff9584..c7a8902 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -206,6 +206,14 @@ interrupts = <0 83 4>; }; + sysctrl: sysctrl@f1840000 { + compatible = "socionext,ph1-sld3-sysctrl"; + reg = <0xf1840000 0x4000>; + #clock-cells = <1>; + clock-names = "ref"; + clocks = <&refclk>; + }; + nand: nand@f8000000 { compatible = "denali,denali-nand-dt"; reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index e765a4b..9d97fb0 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -160,3 +160,7 @@ &pinctrl { compatible = "socionext,ph1-sld8-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-sld8-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index c7423ff..f6f4bbe 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -205,3 +205,7 @@ &pinctrl { compatible = "socionext,proxstream2-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,proxstream2-sysctrl"; +}; |