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authorGraeme Russ <graeme.russ@gmail.com>2009-08-23 12:59:54 +1000
committerWolfgang Denk <wd@denx.de>2009-09-04 21:55:17 +0200
commit91ee4e183cb7ac5f86e7673ead51400f19906635 (patch)
tree7c0af1aaf3965a8542133c5927055e75d1c92a8e
parent8907b8dbc5805094f1316d64737d3428b3863693 (diff)
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Fixup sc520_spunk board
Primary intent is to resolve build errors for this board which has been neglected for a very long time. I do not have one of these boards, so I cannot test functionality Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
-rw-r--r--board/sc520_spunk/sc520_spunk.c33
-rw-r--r--include/configs/sc520_spunk.h2
2 files changed, 33 insertions, 2 deletions
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index d3bd869..36a0a8e 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -24,11 +24,13 @@
#include <common.h>
#include <pci.h>
-#include <ssi.h>
#include <netdev.h>
+#include <ds1722.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+#include <asm/ic/ssi.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -112,7 +114,7 @@ static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev
};
static int next_irq_index=0;
- char tmp_pin;
+ uchar tmp_pin;
int pin;
pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
@@ -637,6 +639,33 @@ void ssi_chip_select(int dev)
}
}
+void spi_eeprom_probe(int x)
+{
+}
+
+int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
+
+int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
+
+void mw_eeprom_probe(int x)
+{
+}
+
+int mw_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
+
+int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
void spi_init_f(void)
{
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index d42ef84..f3fc960 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -37,6 +37,7 @@
#define CONFIG_X86 1 /* This is a X86 CPU */
#define CONFIG_SYS_SC520 1 /* Include support for AMD SC520 */
+#define CONFIG_SYS_SC520_SSI
#define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6 /* 6T */
#define CONFIG_SYS_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
@@ -218,6 +219,7 @@
#define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE 0x00100000
#define CONFIG_SYS_PCMCIA_IO_WIN 0xe000
#define CONFIG_SYS_PCMCIA_IO_WIN_SIZE 16
+#define CONFIG_PCMCIA_SLOT_A /* TODO: Check this */
/************************************************************
* DISK Partition support