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authorMarek Vasut <marex@denx.de>2014-10-10 01:50:23 +0200
committerMarek Vasut <marex@denx.de>2014-10-11 00:50:33 +0200
commit5a1d0ad3ee1ba98ca273c4b35c68618f107ccadd (patch)
tree6db1f31e2ab5395645c59d6bed413ac85fa2f006
parentd8540a16193703a8e5833befbf410c299b83c990 (diff)
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arm: socfpga: Use EMAC1 on SoCDK
The SoCDK uses EMAC1, not EMAC0. This patch fixes the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
-rw-r--r--include/configs/socfpga_cyclone5.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 8d54bf8..60d7e20 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -53,7 +53,7 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
#define CONFIG_EPHY0_PHY_ADDR 0