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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-10-17 16:35:38 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-11-01 15:56:00 -0400 |
| commit | 42d4f37b790307987bd2f7cc569238b6b515149d (patch) | |
| tree | 5305b0d6ff370d753de1a217d08cd33efec0c765 | |
| parent | f9f6686ff8ad3cbc860a51aa2b6b6def4188f15b (diff) | |
| download | u-boot-imx-42d4f37b790307987bd2f7cc569238b6b515149d.zip u-boot-imx-42d4f37b790307987bd2f7cc569238b6b515149d.tar.gz u-boot-imx-42d4f37b790307987bd2f7cc569238b6b515149d.tar.bz2 | |
ARM: OMAP5: DDR3: Change io settings
The change from 0x64656465 to 0x64646464 is to remove the weak pull
enabled on DQS, nDQS lines. This pulls the differential signals in the
same direction which is not intended. So disabling the weak pulls improves
signal integrity.
On the uEVM there are 4 DDR3 devices. The VREF for 2 of the devices is powered by
the OMAP's VREF_CA_OUT pins. The VREF on the other 2 devices is powered by the OMAP's
VREF_DQ_OUT pins. So the net effect here is that only half of the DDR3 devices were being
supplied a VREF! This was clearly a mistake. The second change improves the robustness of
the interface and was specifically seen to cure corruption observed at high temperatures
on some boards.
With the above two changes better memory stability was observed with extended
temperature ranges around 100C.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 414d37a..3c2306f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -145,9 +145,9 @@ struct s32ktimer { #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 #define EFUSE_1 0x45145100 |