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author | Michal Simek <monstr@monstr.eu> | 2014-04-25 12:21:04 +0200 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2014-05-14 07:43:35 +0200 |
commit | 3cc3fa8672705e609ccd25348438453bd8de07fd (patch) | |
tree | 6202a43599c712105d27f75c0131bc0165e477fd | |
parent | 3d456eec43c13778738a5b5246a4109282d207a3 (diff) | |
download | u-boot-imx-3cc3fa8672705e609ccd25348438453bd8de07fd.zip u-boot-imx-3cc3fa8672705e609ccd25348438453bd8de07fd.tar.gz u-boot-imx-3cc3fa8672705e609ccd25348438453bd8de07fd.tar.bz2 |
ARM: zynq: Add MIO detection code
Add run-time MIO pin detection to get actual
pin configuration for specific periphery.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 50 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-zynq/sys_proto.h | 1 |
2 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 5ba58fa..51894f9 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -17,6 +17,26 @@ #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) @@ -120,3 +140,33 @@ u32 zynq_slcr_get_idcode(void) return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 2445a04..53c30ec 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -15,6 +15,7 @@ extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); |