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| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2013-01-30 11:19:16 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-02-12 13:52:31 +0100 |
| commit | 1791b1f97f71bb4f110ca851ab10479640b7bc05 (patch) | |
| tree | 01d05a71d77785352afd7c0e006f26b1effa0c19 | |
| parent | ada02b84636242f5142f74016dbedb50889e93d0 (diff) | |
| download | u-boot-imx-1791b1f97f71bb4f110ca851ab10479640b7bc05.zip u-boot-imx-1791b1f97f71bb4f110ca851ab10479640b7bc05.tar.gz u-boot-imx-1791b1f97f71bb4f110ca851ab10479640b7bc05.tar.bz2 | |
imx: mx6q DDR3 init: Fix RST_to_CKE
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| -rw-r--r-- | board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 73317b5..51f8c35 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005A1021 +DATA 4 0x021b0030 0x005A1023 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 |