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| author | Janne Grunau <j@jannau.net> | 2014-02-16 21:57:18 +0100 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 13:55:41 -0500 |
| commit | 6e2192a3d80b315d071dfe0cbb70a35fe0a262e9 (patch) | |
| tree | e45fd9305635aee37cfa45d288abcfa09c377257 | |
| parent | a5d64dbf20dd4b658dafb081afbbea797b27bdc3 (diff) | |
| download | u-boot-imx-6e2192a3d80b315d071dfe0cbb70a35fe0a262e9.zip u-boot-imx-6e2192a3d80b315d071dfe0cbb70a35fe0a262e9.tar.gz u-boot-imx-6e2192a3d80b315d071dfe0cbb70a35fe0a262e9.tar.bz2 | |
ARM: OMAP4: fix DDR timings for OMAP4430 ES2.0
DDR timings were broken since 47abc3df701d8bc26f311350aa523fc1d0f8ad4e
for PandaBoard EA1.
Signed-off-by: Janne Grunau <j@jannau.net>
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/hw_data.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 4dec73e..029533c 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = { .ddr = NULL }; +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct dplls omap4430_dplls = { .mpu = mpu_dpll_params_1200mhz, .core = core_dpll_params_1600mhz, @@ -413,6 +427,10 @@ void hw_data_init(void) break; case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + case OMAP4430_ES2_1: case OMAP4430_ES2_2: case OMAP4430_ES2_3: |