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author | Timur Tabi <timur@freescale.com> | 2008-10-20 15:16:47 -0500 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:15:20 +0200 |
commit | 681c02d05b29c6d46093525052c74b9c4ddc8b08 (patch) | |
tree | 56d1b0d00ff39a2abccd5218bc16c50e1cf4c493 | |
parent | 50bd0057ba8fceeb48533f8b1a652ccd0e170838 (diff) | |
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85xx: properly document MPC85xx_PORDEVSR2_SEC_CFG
Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot
to add a comment that the correct value disagrees with the 8544 reference
manual. The changelog for that commit is also wrong, as it says "bit 28"
when it should be "bit 24".
Signed-off-by: Timur Tabi <timur@freescale.com>
-rw-r--r-- | include/asm-ppc/immap_85xx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2399243..ad30099 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1579,6 +1579,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ +/* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ |