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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:47 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:06 -0800 |
| commit | 9955b4ab0187e0e9faac57acc01ebe7714d0ec23 (patch) | |
| tree | 0cf5592aeb45af97ff734a8653589dde5a16e1b7 | |
| parent | 1f3402e7291afa3ba0a5f4da72640edaf2f65405 (diff) | |
| download | u-boot-imx-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.zip u-boot-imx-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.tar.gz u-boot-imx-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.tar.bz2 | |
driver/ddr/fsl: Add workaround for A008336
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 5 | ||||
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 22 |
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index d4f688b..256adb0 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,11 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 4eef047..5c2579e 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -32,24 +32,39 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 temp_sdram_cfg; u32 total_gb_size_per_controller; int timeout; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 + u32 *eddrtqcr1; +#endif switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; +#endif break; #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; +#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; +#endif break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; +#endif break; #endif default: @@ -60,6 +75,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (step == 2) goto step2; +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_LS2085A + /* A008336 only applies to general DDR controllers */ + if ((ctrl_num == 0) || (ctrl_num == 1)) +#endif + ddr_out32(eddrtqcr1, 0x63b30002); +#endif if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor); |