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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2014-03-28 09:43:36 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2014-04-28 04:35:11 +0900
commit42c53ab0a7bb45c20f4891b67826e614304da16f (patch)
treeade0e87f78c089ba30336dbd70b87325f7f632a0
parent5723e24df5c8df55b248c6779a2563ce5ad367e4 (diff)
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arm: rmobile: r8a779x: Fix L2 cache init and latency setting
L2CTLR only need to update for cluster 0. This changes L2CTLR to initialize only when cluster is 0. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-rw-r--r--arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S20
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index e07cc80..287f8d7 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -2,7 +2,7 @@
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -36,16 +36,32 @@ do_cpu_waiting:
.align 4
do_lowlevel_init:
/* surpress wfe if ca15 */
- tst r4, #4
+ tst r4, #4
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
+
/* and set l2 latency */
mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
orreq r0, r0, #0x00000800
orreq r0, r0, #0x00000003
mcreq p15, 1, r0, c9, c0, 2
+ mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
+ and r0, r0, #0xf00
+ lsr r0, r0, #8
+ tst r0, #1 /* only need for cluster 0 */
+ bne _exit_init_l2_a15
+
+ mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
+ and r1, r0, #7
+ cmp r1, #3 /* has already been set up */
+ bicne r0, r0, #0xe7
+ orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
+ orrne r0, r0, #0x20 /* L2CTLR[5] */
+ mcrne p15, 1, r0, c9, c0, 2
+
+_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]