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| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2007-03-07 15:32:01 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-08 22:14:47 +0100 |
| commit | f9fc6a5852a6335840882fa2111925010eea1abe (patch) | |
| tree | 446e0317e52bbdd358a755376051d06ea3538388 | |
| parent | 35ded29fd941f3bd40660dd1440763f34708cf65 (diff) | |
| download | u-boot-imx-f9fc6a5852a6335840882fa2111925010eea1abe.zip u-boot-imx-f9fc6a5852a6335840882fa2111925010eea1abe.tar.gz u-boot-imx-f9fc6a5852a6335840882fa2111925010eea1abe.tar.bz2 | |
fixed ethernet phy configuration for plu405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| -rw-r--r-- | board/esd/plu405/plu405.c | 17 | ||||
| -rw-r--r-- | include/configs/PLU405.h | 8 |
2 files changed, 13 insertions, 12 deletions
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 37b92fb..59171f8 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -215,12 +215,6 @@ int checkboard (void) } putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - return 0; } @@ -292,3 +286,14 @@ void board_auto_update_show(int au_active) } } #endif + +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index dd5d831..d02c39b 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -51,17 +51,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if 0 /* test-only */ #define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ -#else -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#endif #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ |