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| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2014-08-03 05:32:44 +0300 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2014-08-12 08:42:32 +0200 |
| commit | cfc89b003bb2600eb330939da0f53b9caf3e17fa (patch) | |
| tree | c73599e993a3723ffd607d84eb1f344feaad944b | |
| parent | 7e40e1926a237ad215901cd780f309e995105515 (diff) | |
| download | u-boot-imx-cfc89b003bb2600eb330939da0f53b9caf3e17fa.zip u-boot-imx-cfc89b003bb2600eb330939da0f53b9caf3e17fa.tar.gz u-boot-imx-cfc89b003bb2600eb330939da0f53b9caf3e17fa.tar.bz2 | |
sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 33e8bd6..9042e9a 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -446,10 +446,6 @@ unsigned long dramc_init(struct dram_para *para) /* Disable any pad power save control */ mctl_disable_power_save(); - /* reset external DRAM */ -#ifndef CONFIG_SUN7I - mctl_ddr3_reset(); -#endif mctl_set_drive(); /* dram clock off */ @@ -491,18 +487,11 @@ unsigned long dramc_init(struct dram_para *para) reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); writel(reg_val, &dram->dcr); -#ifdef CONFIG_SUN7I dramc_clock_output_en(1); -#endif mctl_set_cke_delay(); -#ifdef CONFIG_SUN7I mctl_ddr3_reset(); -#else - /* dram clock on */ - dramc_clock_output_en(1); -#endif udelay(1); |