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| author | Michal Simek <michal.simek@xilinx.com> | 2014-11-04 13:27:52 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-01-21 10:20:36 +0100 |
| commit | 822d43a6d90223db043d1610895c8e8b82e5ba5b (patch) | |
| tree | 5842d50ca500c951b97fb8d8658ce69230a9b035 | |
| parent | 768f6096f9c389b5ed36bee2957bee16b085fc4a (diff) | |
| download | u-boot-imx-822d43a6d90223db043d1610895c8e8b82e5ba5b.zip u-boot-imx-822d43a6d90223db043d1610895c8e8b82e5ba5b.tar.gz u-boot-imx-822d43a6d90223db043d1610895c8e8b82e5ba5b.tar.bz2 | |
microblaze: Enable hardware exception by default
Enable hardware exception by default to be able to
handle it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | arch/microblaze/cpu/start.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 1757bbf..f466031 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -130,7 +130,7 @@ flush: bralid r15, flush_cache /* enable instruction and data cache */ mfs r12, rmsr - ori r12, r12, 0xa0 + ori r12, r12, 0x1a0 mts rmsr, r12 clear_bss: |