diff options
| author | Ye Li <ye.li@nxp.com> | 2016-04-12 14:06:42 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2016-04-12 14:06:42 +0800 |
| commit | 5154e0c15965019602a7c128abe00d58b6e26ff1 (patch) | |
| tree | f8f89ea99369ff9bc2ad39fa835152b08e43816e | |
| parent | 60cb811a0e9abbdd89e498c499fa4e63a18fae58 (diff) | |
| download | u-boot-imx-5154e0c15965019602a7c128abe00d58b6e26ff1.zip u-boot-imx-5154e0c15965019602a7c128abe00d58b6e26ff1.tar.gz u-boot-imx-5154e0c15965019602a7c128abe00d58b6e26ff1.tar.bz2 | |
MLK-12616-9 mx6ull: Update memory map address
Update memory map address for mx6ull which uses AIPS3 and adjust UART8
to AIPS3 by replacing for ESAI.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 9fbe3e4..3d0a79d 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -163,7 +163,11 @@ #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #if defined(CONFIG_MX6UL) +#if defined(CONFIG_MX6ULL) +#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#else #define UART8_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#endif #define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) #define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) @@ -219,10 +223,12 @@ #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) + #if defined(CONFIG_MX6SL) #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #elif defined(CONFIG_MX6SX) #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) @@ -243,8 +249,8 @@ #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#endif #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#endif #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) @@ -378,6 +384,14 @@ #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#elif defined(CONFIG_MX6ULL) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #endif #define CHIP_REV_1_0 0x10 |