Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'

36 files changed, 896 insertions, 298 deletions

diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
index 03eb2de..0ba6f09 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
@@ -31,7 +31,7 @@ static u32 kirkwood_variant(void)
 #define MPP_CTRL(i)	(KW_MPP_BASE + (i* 4))
 #define MPP_NR_REGS	(1 + MPP_MAX/8)
 
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
 {
 	u32 mpp_ctrl[MPP_NR_REGS];
 	unsigned int variant_mask;
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
index 57bfe8e..009a6bb 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -33,7 +33,7 @@
 			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
 
 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
+		((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
 
 #define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
 #define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h
index 8ceea7b..48d1477 100644
--- a/arch/arm/include/asm/arch-kirkwood/mpp.h
+++ b/arch/arm/include/asm/arch-kirkwood/mpp.h
@@ -312,6 +312,6 @@
 
 #define MPP_MAX			49
 
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
 
 #endif
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index 0e06c29..e524f35 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
 			NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
index 101a80a..0aa5345 100644
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
 			NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
new file mode 100644
index 0000000..b43c3d3
--- /dev/null
+++ b/board/LaCie/wireless_space/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
new file mode 100644
index 0000000..0daf5b5
--- /dev/null
+++ b/board/LaCie/wireless_space/kwbimage.cfg
@@ -0,0 +1,82 @@
+#
+# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on netspace_v2 kwbimage.cfg:
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand	# Boot from NAND flash
+NAND_PAGE_SIZE 800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Values taken from image original LaCie U-Boot header dump!
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+
+DATA 0xFFD01404 0x37743000	# DDR Controller Control Low
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+
+DATA 0xFFD01410 0x0000CCCC	#  DDR Address Control
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+
+DATA 0xFFD0141C 0x00000662	#  DDR Mode
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+
+DATA 0xFFD01428 0x00096630	# DDR2 ODT Read Timing (default values)
+
+DATA 0xFFD0147C 0x00009663	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+DATA 0xFFD01508 0x00000000	# CS[1]n Base address to 0x0
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0xFFD10000 0x01112222
+DATA 0xFFD1000C 0x00000000
+DATA 0xFFD10104 0x00000000
+DATA 0xFFD10100 0x40000000
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
new file mode 100644
index 0000000..2080658
--- /dev/null
+++ b/board/LaCie/wireless_space/wireless_space.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "../common/common.h"
+#include "netdev.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO configuration: start FAN at low speed, USB and HDD */
+
+#define WIRELESS_SPACE_OE_LOW		0xFF006808
+#define WIRELESS_SPACE_OE_HIGH		0x0000F989
+#define WIRELESS_SPACE_OE_VAL_LOW	0x00010080
+#define WIRELESS_SPACE_OE_VAL_HIGH	0x00000240
+
+#define WIRELESS_SPACE_REAR_BUTTON	13
+#define WIRELESS_SPACE_FRONT_BUTTON	43
+
+const u32 kwmpp_config[] = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_GPO,		/* Fan speed (bit 1) */
+	MPP8_TW_SDA,
+	MPP9_TW_SCK,
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP13_GPIO,		/* Red led */
+	MPP14_GPIO,		/* USB fuse */
+	MPP15_SATA0_ACTn,
+	MPP16_GPIO,		/* SATA 0 power */
+	MPP17_GPIO,		/* SATA 1 power */
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GE1_0,		/* Gigabit Ethernet 1 */
+	MPP21_GE1_1,
+	MPP22_GE1_2,
+	MPP23_GE1_3,
+	MPP24_GE1_4,
+	MPP25_GE1_5,
+	MPP26_GE1_6,
+	MPP27_GE1_7,
+	MPP28_GE1_8,
+	MPP29_GE1_9,
+	MPP30_GE1_10,
+	MPP31_GE1_11,
+	MPP32_GE1_12,
+	MPP33_GE1_13,
+	MPP34_GE1_14,
+	MPP35_GE1_15,
+	MPP36_GPIO,		/* Fan speed (bit 2) */
+	MPP37_GPIO,		/* Fan speed (bit 0) */
+	MPP38_GPIO,		/* Fan power */
+	MPP39_GPIO,		/* Fan rotation fail */
+	MPP40_GPIO,		/* Ethernet switch link */
+	MPP41_GPIO,		/* USB enable host vbus */
+	MPP42_GPIO,		/* LED clock control */
+	MPP43_GPIO,		/* WPS button (0=Pushed, 1=Released) */
+	MPP44_GPIO,		/* Red LED on/off */
+	MPP45_GPIO,		/* Red LED timer blink (on=off=100ms) */
+	MPP46_GPIO,		/* Green LED on/off */
+	MPP47_GPIO,		/* LED (blue, green) SATA activity blink */
+	MPP48_GPIO,		/* Blue LED on/off */
+	0
+};
+
+struct mv88e61xx_config swcfg = {
+	.name = "egiga0",
+	.vlancfg = MV88E61XX_VLANCFG_ROUTER,
+	.rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+	.led_init = MV88E61XX_LED_INIT_EN,
+	.mdip = MV88E61XX_MDIP_NOCHANGE,
+	.portstate = MV88E61XX_PORTSTT_FORWARDING,
+	.cpuport = 0x20,
+	.ports_enabled = 0x3F,
+};
+
+int board_early_init_f(void)
+{
+	/* Gpio configuration */
+	kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
+			WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Machine number */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+	if (!getenv("ethaddr")) {
+		uchar mac[6];
+		if (lacie_read_mac_address(mac) == 0)
+			eth_setenv_enetaddr("ethaddr", mac);
+	}
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	/* configure switch on egiga0 */
+	mv88e61xx_switch_initialize(&swcfg);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
+/* Return GPIO button status */
+static int
+do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (strcmp(argv[1], "button") == 0) {
+		if (strcmp(argv[2], "rear") == 0)
+			/* invert GPIO result for intuitive while/until use */
+			return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
+		else if (strcmp(argv[2], "front") == 0)
+			return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
+		else
+			return -1;
+	} else {
+		return -1;
+	}
+}
+
+U_BOOT_CMD(ws, 3, 0, do_ws,
+	   "Return GPIO button status 0=off 1=on",
+	   "- ws button rear|front: test buttons' states\n"
+);
+#endif
diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c
index d6497aa..0caf34f 100644
--- a/board/Marvell/dreamplug/dreamplug.c
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -46,7 +46,7 @@ int board_early_init_f(void)
 			DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,		/* SPI Flash */
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index f5c1c3c..3a52ab2 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -43,7 +43,7 @@ int board_early_init_f(void)
 			GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index 43852f6..fb57faa 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -45,7 +45,7 @@ int board_early_init_f(void)
 			MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
index d48f05a..c59a326 100644
--- a/board/Marvell/openrd/openrd.c
+++ b/board/Marvell/openrd/openrd.c
@@ -48,7 +48,7 @@ int board_early_init_f(void)
 			OPENRD_OE_LOW, OPENRD_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index 1fd7677..adaa6a1 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -44,7 +44,7 @@ int board_early_init_f(void)
 			RD6281A_OE_LOW, RD6281A_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 688d308..16efe64 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -43,7 +43,7 @@ int board_early_init_f(void)
 			SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c
index fc88520..4f1f899 100644
--- a/board/Seagate/dockstar/dockstar.c
+++ b/board/Seagate/dockstar/dockstar.c
@@ -47,7 +47,7 @@ int board_early_init_f(void)
 			DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index 57776fb..83eea04 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -49,9 +49,8 @@
  * you can do this only with a working network connection. Therefore, a random
  * ethernet address is generated if none is set and a DHCP request is sent.
  * After a successful DHCP response is received, the network settings are
- * configured and the ncip parameter is set to the serverip. Eg. for a working
- * resuce mode, you should set 'next-server' to the host where the netconsole
- * client is started.
+ * configured and the ncip is unset. Therefore, all netconsole packets are
+ * broadcasted.
  * Additionally, the bootsource is set to 'rescue'.
  */
 
@@ -76,7 +75,7 @@ int board_early_init_f(void)
 	 * Multi-Purpose Pins Functionality configuration
 	 * These strappings are taken from the original vendor uboot port.
 	 */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,
diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c
index bac9ce5..3b1c8ec 100644
--- a/board/cloudengines/pogo_e02/pogo_e02.c
+++ b/board/cloudengines/pogo_e02/pogo_e02.c
@@ -45,7 +45,7 @@ int board_early_init_f(void)
 			POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c
index 11260fe..4187901 100644
--- a/board/d-link/dns325/dns325.c
+++ b/board/d-link/dns325/dns325.c
@@ -44,7 +44,7 @@ int board_early_init_f(void)
 			DNS325_OE_LOW, DNS325_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c
index 8cfb4e6..c54c95d 100644
--- a/board/iomega/iconnect/iconnect.c
+++ b/board/iomega/iconnect/iconnect.c
@@ -41,7 +41,7 @@ int board_early_init_f(void)
 			ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c
index 96410d7..7a4e7b3 100644
--- a/board/karo/tk71/tk71.c
+++ b/board/karo/tk71/tk71.c
@@ -47,7 +47,7 @@ int board_early_init_f(void)
 			TK71_OE_LOW, TK71_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index a90f112..6f407b7 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -121,7 +121,7 @@ int i2c_make_abort(void)
 {
 
 #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 
 	/*
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 0c4dddc..eda9199 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MASK_RBI_DEFECT_16	0x01
 
 /* Multi-Purpose Pins Functionality configuration */
-u32 kwmpp_config[] = {
+static const u32 kwmpp_config[] = {
 	MPP0_NF_IO2,
 	MPP1_NF_IO3,
 	MPP2_NF_IO4,
@@ -193,15 +193,6 @@ void set_bootcount_addr(void)
 
 int misc_init_r(void)
 {
-	char *str;
-	int mach_type;
-
-	str = getenv("mach_type");
-	if (str != NULL) {
-		mach_type = simple_strtoul(str, NULL, 10);
-		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
-		gd->bd->bi_arch_number = mach_type;
-	}
 #if defined(CONFIG_KM_MGCOGE3UN)
 	char *wait_for_ne;
 	wait_for_ne = getenv("waitforne");
@@ -258,11 +249,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	/*
-	 * arch number of board
-	 */
-	gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
-
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
index 6df2ad7..5aa0de2 100644
--- a/board/keymile/km_arm/kwbimage-memphis.cfg
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -55,9 +55,9 @@ DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
 DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
 DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
 DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 #Dram initalization
 DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
index b2f5193..e5e9942 100644
--- a/board/keymile/km_arm/kwbimage.cfg
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -52,9 +52,9 @@ DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
 DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
 DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
 DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 #Dram initalization
 DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg
index bcce907..5de8df7 100644
--- a/board/keymile/km_arm/kwbimage_128M16_1.cfg
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -98,29 +98,8 @@ DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
 # bit 19-18: 1, ECC RAM WTC RAM0
 # bit 31-20: ???,Reserve
 
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-# bit 23-0:  0x000200, Addr Config tuning
-# bit 31-24: 0,        Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-# bit 15-0:  0x1C00, Opmux Tuning
-# bit 31-16: 0,      Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
-# bit 1-0:   1, addr clk tune
-# bit 3-2:   0, reserved
-# bit 5-4:   0, dtcmp clk tune
-# bit 7-6:   0, reserved
-# bit 9-8:   0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 # SDRAM initalization
 DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg
index 3e1237b..d0a09f6 100644
--- a/board/keymile/km_arm/kwbimage_256M8_1.cfg
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -100,29 +100,8 @@ DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
 # bit 19-18: 1, ECC RAM WTC RAM0
 # bit 31-20: ?,Reserved
 
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-# bit 23-0:  0x000200, Addr Config tuning
-# bit 31-24: 0,        Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-# bit 15-0:  0x1C00, Opmux Tuning
-# bit 31-16: 0,      Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
-# bit 1-0:   1, addr clk tune
-# bit 3-2:   0, reserved
-# bit 5-4:   0, dtcmp clk tune
-# bit 7-6:   0, reserved
-# bit 9-8:   0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 # SDRAM initalization
 DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
index 5f0f396..cf4ca51 100644
--- a/board/raidsonic/ib62x0/ib62x0.c
+++ b/board/raidsonic/ib62x0/ib62x0.c
@@ -45,7 +45,7 @@ int board_early_init_f(void)
 	/* Set SATA activity LEDs to default off */
 	writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,
diff --git a/boards.cfg b/boards.cfg
index 388e4a4..1477f91 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -171,6 +171,7 @@ netspace_lite_v2             arm         arm926ejs   netspace_v2         LaCie
 netspace_max_v2              arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_MAX_V2
 netspace_mini_v2             arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_MINI_V2
 netspace_v2                  arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_V2
+wireless_space               arm         arm926ejs   wireless_space      LaCie          kirkwood
 dreamplug                    arm         arm926ejs   -                   Marvell        kirkwood
 guruplug                     arm         arm926ejs   -                   Marvell        kirkwood
 mv88f6281gtw_ge              arm         arm926ejs   -                   Marvell        kirkwood
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 483a920..e8da66d 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -26,6 +26,14 @@
 #include <netdev.h>
 #include "mv88e61xx.h"
 
+/*
+ * Uncomment either of the following line for local debug control;
+ * otherwise global debug control will apply.
+ */
+
+/* #undef DEBUG */
+/* #define DEBUG */
+
 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
 /* Chip Address mode
  * The Switch support two modes of operation
@@ -52,7 +60,8 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
 	return 0;
 }
 
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 data)
 {
 	u16 mii_dev_addr;
 
@@ -70,7 +79,8 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
 									 15));
 }
 
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 *data)
 {
 	u16 mii_dev_addr;
 
@@ -90,110 +100,51 @@ static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
 }
 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
 
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
-				       u32 max_prtnum, u32 ports_ofs)
-{
-	u32 prt;
-	u16 reg;
-	char *name = swconfig->name;
-	u32 cpu_port = swconfig->cpuport;
-	u32 port_mask = swconfig->ports_enabled;
-	enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
-
-	/* be sure all ports are disabled */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg);
-		reg &= ~0x3;
-		WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
-
-		if (!(cpu_port & (1 << prt)))
-			continue;
-		/* Set CPU port VID to 0x1 */
-		RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, &reg);
-		reg &= ~0xfff;
-		reg |= 0x1;
-		WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
-	}
-
-	/* Setting  Port default priority for all ports to zero */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg);
-		reg &= ~0xc000;
-		WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
-	}
-	/* Setting VID and VID map for all ports except CPU port */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		/* only for enabled ports */
-		if ((1 << prt) & port_mask) {
-			/* skip CPU port */
-			if ((1 << prt) & cpu_port) {
-				/*
-				 * Set Vlan map table for cpu_port to see
-				 * all ports
-				 */
-				RD_PHY(name, (ports_ofs + prt),
-				       MV88E61XX_PRT_VMAP_REG, &reg);
-				reg &= ~((1 << max_prtnum) - 1);
-				reg |= port_mask & ~(1 << prt);
-				WR_PHY(name, (ports_ofs + prt),
-				       MV88E61XX_PRT_VMAP_REG, reg);
-			} else {
-
-				/*
-				 *  set Ports VLAN Mapping.
-				 *      port prt <--> cpu_port VLAN #prt+1.
-				 */
-				RD_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VID_REG, &reg);
-				reg &= ~0x0fff;
-				reg |= (prt + 1);
-				WR_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VID_REG, reg);
-
-				RD_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VMAP_REG, &reg);
-				if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
-					/*
-					 * all any port can send frames to all other ports
-					 * ref: sec 3.2.1.1 of datasheet
-					 */
-					reg |= 0x03f;
-					reg &= ~(1 << prt);
-				} else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
-					/*
-					 * all other ports can send frames to CPU port only
-					 * ref: sec 3.2.1.2 of datasheet
-					 */
-					reg &= ~((1 << max_prtnum) - 1);
-					reg |= cpu_port;
-				}
-				WR_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VMAP_REG, reg);
-			}
-		}
-	}
+/*
+ * Convenience macros for switch device/port reads/writes
+ * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ */
 
-	/*
-	 * enable only appropriate ports to forwarding mode
-	 * and disable the others
-	 */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		if ((1 << prt) & port_mask) {
-			RD_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, &reg);
-			reg |= 0x3;
-			WR_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, reg);
-		} else {
-			/* Disable port */
-			RD_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, &reg);
-			reg &= ~0x3;
-			WR_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, reg);
-		}
-	}
+#ifndef DEBUG
+#define WR_SWITCH_REG wr_switch_reg
+#define RD_SWITCH_REG rd_switch_reg
+#define WR_SWITCH_PORT_REG(n, p, r, d) \
+	WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#define RD_SWITCH_PORT_REG(n, p, r, d) \
+	RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#else
+static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
+{
+	printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
+		name, dev_adr, reg_ofs, data);
+	wr_switch_reg(name, dev_adr, reg_ofs, data);
 }
+static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+{
+	rd_switch_reg(name, dev_adr, reg_ofs, data);
+	printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
+		name, dev_adr, reg_ofs, *data);
+}
+static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+	u16 data)
+{
+	printf("mv88e61xx %s port %02x reg %02x write %04x\n",
+		name, prt_adr, reg_ofs, data);
+	wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+}
+static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+	u16 *data)
+{
+	rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+	printf("mv88e61xx %s port %02x reg %02x read %04x\n",
+		name, prt_adr, reg_ofs, *data);
+}
+#endif
+
+/*
+ * Local functions to read/write registers on the switch PHYs.
+ * NOTE! This goes through switch, not direct miiphy, writes and reads!
+ */
 
 /*
  * Make sure SMIBusy bit cleared before another
@@ -204,7 +155,7 @@ static int mv88e61xx_busychk(char *name)
 	u16 reg = 0;
 	u32 timeout = MV88E61XX_PHY_TIMEOUT;
 	do {
-		RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
+		rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
 		       MV88E61XX_PHY_CMD, &reg);
 		if (timeout-- == 0) {
 			printf("SMI busy timeout\n");
@@ -214,34 +165,110 @@ static int mv88e61xx_busychk(char *name)
 	return 0;
 }
 
+static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
+	u32 reg, u16 data)
+{
+	/* write switch data reg then cmd reg then check completion */
+	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
+		data);
+	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+		(MV88E61XX_PHY_WRITE_CMD | (phy << 5)  | reg));
+	return mv88e61xx_busychk(name);
+}
+
+static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
+	u32 reg, u16 *data)
+{
+	/* write switch cmd reg, check for completion */
+	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+		(MV88E61XX_PHY_READ_CMD | (phy << 5)  | reg));
+	if (mv88e61xx_busychk(name))
+		return -1;
+	/* read switch data reg and return success */
+	rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
+	return 0;
+}
+
+/*
+ * Convenience macros for switch PHY reads/writes
+ */
+
+#ifndef DEBUG
+#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
+#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
+#else
+static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 data)
+{
+	int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
+	if (r)
+		printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
+			name, phy_adr, reg_ofs);
+	else
+		printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
+			name, phy_adr, reg_ofs, data);
+	return r;
+}
+static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 *data)
+{
+	int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
+	if (r)
+		printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
+			name, phy_adr, reg_ofs);
+	else
+		printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
+			name, phy_adr, reg_ofs, *data);
+	return r;
+}
+#endif
+
+static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
+{
+	u32 prt;
+	u16 reg;
+	char *name = swconfig->name;
+	u32 port_mask = swconfig->ports_enabled;
+
+	/* apply internal vlan config */
+	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
+		/* only for enabled ports */
+		if ((1 << prt) & port_mask) {
+			/* take vlan map from swconfig */
+			u8 vlanmap = swconfig->vlancfg[prt];
+			/* remove disabled ports from vlan map */
+			vlanmap &= swconfig->ports_enabled;
+			/* apply vlan map to port */
+			RD_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VMAP_REG, &reg);
+			reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
+			reg |= vlanmap;
+			WR_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VMAP_REG, reg);
+		}
+	}
+}
+
 /*
  * Power up the specified port and reset PHY
  */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
 {
 	char *name = swconfig->name;
 
-	/* Write Copper Specific control reg1 (0x14) for-
+	/* Write Copper Specific control reg1 (0x10) for-
 	 * Enable Phy power up
 	 * Energy Detect on (sense&Xmit NLP Periodically
 	 * reset other settings default
 	 */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
 		return -1;
 
 	/* Write PHY ctrl reg (0x0) to apply
 	 * Phy reset (set bit 15 low)
 	 * reset other default values
 	 */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
 		return -1;
 
 	return 0;
@@ -256,48 +283,26 @@ static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
  * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
  * Link status
  */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
 {
 	char *name = swconfig->name;
-	u16 reg;
 
 	if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
 		return 0;
 
 	/* set page address to 3 */
-	reg = 3;
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 22));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
 		return -1;
 
-	/* set LED Func Ctrl reg */
-	reg = 1;	/* LED[0] On-Link, Blink-Activity, Off-NoLink */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 16));
-
-	if (mv88e61xx_busychk(name))
+	/*
+	 * set LED Func Ctrl reg
+	 * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
+	 */
+	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
 		return -1;
 
 	/* set page address to 0 */
-	reg = 0;
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 22));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
 		return -1;
 
 	return 0;
@@ -312,23 +317,15 @@ static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
  * This is optional settings may be needed on some boards
  * for PHY<->magnetics h/w tuning
  */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
 {
 	char *name = swconfig->name;
-	u16 reg;
 
 	if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
 		return 0;
 
-	reg = 0x0f;		/*Reverse MDIP/N[3:0] bits */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 20));
-
-	if (mv88e61xx_busychk(name))
+	/*Reverse MDIP/N[3:0] bits */
+	if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
 		return -1;
 
 	return 0;
@@ -343,6 +340,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 	u16 reg;
 	char *idstr;
 	char *name = swconfig->name;
+	int time;
 
 	if (miiphy_set_current_dev(name)) {
 		printf("%s failed\n", __FUNCTION__);
@@ -354,7 +352,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 		printf("Invalid cpu port config, using default port5\n");
 	}
 
-	RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, &reg);
+	RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg);
 	switch (reg &= 0xfff0) {
 	case 0x1610:
 		idstr = "88E6161";
@@ -373,46 +371,183 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 		break;
 	}
 
-	/* Port based VLANs configuration */
-	if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
-	    || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
-		mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
-					   MV88E61XX_PRT_OFST);
-	else {
-		printf("Unsupported mode %s failed\n", __FUNCTION__);
-		return -1;
+	/* be sure all ports are disabled */
+	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
+		RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg);
+		reg &= ~0x3;
+		WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
 	}
 
+	/* wait 2 ms for queues to drain */
+	udelay(2000);
+
+	/* reset switch */
+	RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, &reg);
+	reg |= 0x8000;
+	WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+
+	/* wait up to 1 second for switch reset complete */
+	for (time = 1000; time; time--) {
+		RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
+			&reg);
+		if ((reg & 0xc800) == 0xc800)
+			break;
+		udelay(1000);
+	}
+	if (!time)
+		return -1;
+
+	/* Port based VLANs configuration */
+	mv88e61xx_port_vlan_config(swconfig);
+
 	if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
 		/*
 		 * Enable RGMII delay on Tx and Rx for CPU port
 		 * Ref: sec 9.5 of chip datasheet-02
 		 */
-		WR_PHY(name, MV88E61XX_PRT_OFST + 5,
-		       MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
-		WR_PHY(name, MV88E61XX_PRT_OFST + 4,
-		       MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
+		/*Force port link down */
+		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
+		/* configure port RGMII delay */
+		WR_SWITCH_PORT_REG(name, 4,
+			MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
+		RD_SWITCH_PORT_REG(name, 5,
+			MV88E61XX_RGMII_TIMECTRL_REG, &reg);
+		WR_SWITCH_PORT_REG(name, 5,
+			MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
+		WR_SWITCH_PORT_REG(name, 4,
+			MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
+		/* Force port to RGMII FDX 1000Base then up */
+		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
+		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
 	}
 
 	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		if (!((1 << prt) & swconfig->cpuport)) {
 
-			if (mv88361xx_led_init(swconfig, prt))
+		/* configure port's PHY */
+		if (!((1 << prt) & swconfig->cpuport)) {
+			/* port 4 has phy 6, not 4 */
+			int phy = (prt == 4) ? 6 : prt;
+			if (mv88361xx_powerup(swconfig, phy))
 				return -1;
-			if (mv88361xx_reverse_mdipn(swconfig, prt))
+			if (mv88361xx_reverse_mdipn(swconfig, phy))
 				return -1;
-			if (mv88361xx_powerup(swconfig, prt))
+			if (mv88361xx_led_init(swconfig, phy))
 				return -1;
 		}
 
+		/* set port VID to port+1 except for cpu port */
+		if (!((1 << prt) & swconfig->cpuport)) {
+			RD_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VID_REG, &reg);
+			WR_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VID_REG,
+				(reg & ~1023) | (prt+1));
+		}
+
 		/*Program port state */
-		RD_PHY(name, MV88E61XX_PRT_OFST + prt,
-		       MV88E61XX_PRT_CTRL_REG, &reg);
-		WR_PHY(name, MV88E61XX_PRT_OFST + prt,
-		       MV88E61XX_PRT_CTRL_REG,
-		       reg | (swconfig->portstate & 0x03));
+		RD_SWITCH_PORT_REG(name, prt,
+			MV88E61XX_PRT_CTRL_REG, &reg);
+		WR_SWITCH_PORT_REG(name, prt,
+			MV88E61XX_PRT_CTRL_REG,
+			reg | (swconfig->portstate & 0x03));
+
 	}
 
 	printf("%s Initialized on %s\n", idstr, name);
 	return 0;
 }
+
+#ifdef CONFIG_MV88E61XX_CMD
+static int
+do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *name, *endp;
+	int write = 0;
+	enum { dev, prt, phy } target = dev;
+	u32 addrlo, addrhi, addr;
+	u32 reglo, reghi, reg;
+	u16 data, rdata;
+
+	if (argc < 7)
+		return -1;
+
+	name = argv[1];
+
+	if (strcmp(argv[2], "phy") == 0)
+		target = phy;
+	else if (strcmp(argv[2], "port") == 0)
+		target = prt;
+	else if (strcmp(argv[2], "dev") != 0)
+		return 1;
+
+	addrlo = simple_strtoul(argv[3], &endp, 16);
+
+	if (!*endp) {
+		addrhi = addrlo;
+	} else {
+		while (*endp < '0' || *endp > '9')
+			endp++;
+		addrhi = simple_strtoul(endp, NULL, 16);
+	}
+
+	reglo = simple_strtoul(argv[5], &endp, 16);
+	if (!*endp) {
+		reghi = reglo;
+	} else {
+		while (*endp < '0' || *endp > '9')
+			endp++;
+		reghi = simple_strtoul(endp, NULL, 16);
+	}
+
+	if (strcmp(argv[6], "write") == 0)
+		write = 1;
+	else if (strcmp(argv[6], "read") != 0)
+		return 1;
+
+	data = simple_strtoul(argv[7], NULL, 16);
+
+	for (addr = addrlo; addr <= addrhi; addr++) {
+		for (reg = reglo; reg <= reghi; reg++) {
+			if (write) {
+				if (target == phy)
+					mv88e61xx_switch_miiphy_write(
+						name, addr, reg, data);
+				else if (target == prt)
+					wr_switch_reg(name,
+						addr+MV88E61XX_PRT_OFST,
+						reg, data);
+				else
+					wr_switch_reg(name, addr, reg, data);
+			} else {
+				if (target == phy)
+					mv88e61xx_switch_miiphy_read(
+						name, addr, reg, &rdata);
+				else if (target == prt)
+					rd_switch_reg(name,
+						addr+MV88E61XX_PRT_OFST,
+						reg, &rdata);
+				else
+					rd_switch_reg(name, addr, reg, &rdata);
+				printf("%s %s %s %02x %s %02x %s %04x\n",
+					argv[0], argv[1], argv[2], addr,
+					argv[4], reg, argv[6], rdata);
+				if (write && argc == 7 && rdata != data)
+					return 1;
+			}
+		}
+	}
+	return 0;
+}
+
+U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
+	"Read or write mv88e61xx switch registers",
+	"<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
+	"<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
+	"    - read/write switch device, port or phy at (addr,reg)\n"
+	"      addr=0..0x1C for dev, 0..5 for port or phy.\n"
+	"      reg=0..0x1F.\n"
+	"      data=0..0xFFFF (tested if present against actual read).\n"
+	"      All numeric parameters are assumed to be hex.\n"
+	"      <addr> and <<reg> arguments can be ranges (x..y)"
+);
+#endif /* CONFIG_MV88E61XX_CMD */
diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h
index 57762b6..55ded7e 100644
--- a/drivers/net/phy/mv88e61xx.h
+++ b/drivers/net/phy/mv88e61xx.h
@@ -28,35 +28,50 @@
 #include <miiphy.h>
 
 #define MV88E61XX_CPU_PORT		0x5
-#define MV88E61XX_MAX_PORTS_NUM		0x6
 
 #define MV88E61XX_PHY_TIMEOUT		100000
 
-#define MV88E61XX_PRT_STS_REG		0x1
+/* port dev-addr (= port + 0x10) */
+#define MV88E61XX_PRT_OFST		0x10
+/* port registers */
+#define MV88E61XX_PCS_CTRL_REG		0x1
 #define MV88E61XX_PRT_CTRL_REG		0x4
 #define MV88E61XX_PRT_VMAP_REG		0x6
 #define MV88E61XX_PRT_VID_REG		0x7
+#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
 
-#define MV88E61XX_PRT_OFST		0x10
+/* global registers dev-addr */
+#define MV88E61XX_GLBREG_DEVADR	0x1B
+/* global registers */
+#define MV88E61XX_SGSR			0x00
+#define MV88E61XX_SGCR			0x04
+
+/* global 2 registers dev-addr */
+#define MV88E61XX_GLB2REG_DEVADR	0x1C
+/* global 2 registers */
 #define MV88E61XX_PHY_CMD		0x18
 #define MV88E61XX_PHY_DATA		0x19
-#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
-#define MV88E61XX_GLB2REG_DEVADR	0x1C
+/* global 2 phy commands */
+#define MV88E61XX_PHY_WRITE_CMD		0x9400
+#define MV88E61XX_PHY_READ_CMD		0x9800
 
 #define MV88E61XX_BUSY_OFST		15
 #define MV88E61XX_MODE_OFST		12
-#define MV88E61XX_OP_OFST			10
+#define MV88E61XX_OP_OFST		10
 #define MV88E61XX_ADDR_OFST		5
 
 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
 static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
-#define WR_PHY mv88e61xx_wr_phy
-#define RD_PHY mv88e61xx_rd_phy
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 data);
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 *data);
+#define wr_switch_reg mv88e61xx_switch_write
+#define rd_switch_reg mv88e61xx_switch_read
 #else
-#define WR_PHY miiphy_write
-#define RD_PHY miiphy_read
+/* switch appears a s simple PHY and can thus use miiphy */
+#define wr_switch_reg miiphy_write
+#define rd_switch_reg miiphy_read
 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
 
 #endif /* _MV88E61XX_H */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index a7cda75..de81064 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -41,7 +41,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 {
 	struct spi_slave *slave;
 	u32 data;
-	u32 kwspi_mpp_config[] = { 0, 0 };
+	static const u32 kwspi_mpp_config[2][2] = {
+		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
+		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
+	};
 
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
@@ -68,12 +71,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	writel(KWSPI_IRQMASK, &spireg->irq_mask);
 
 	/* program mpp registers to select  SPI_CSn */
-	if (cs) {
-		kwspi_mpp_config[0] = MPP7_SPI_SCn;
-	} else {
-		kwspi_mpp_config[0] = MPP0_SPI_SCn;
-	}
-	kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back);
+	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
 
 	return slave;
 }
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 05480d4..f64748e 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -253,9 +253,6 @@
 	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
 	"mtdids=" MTDIDS_DEFAULT "\0"					\
 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
-	"stderr=serial\0"						\
-	"stdin=serial\0"						\
-	"stdout=serial\0"						\
 	""
 #endif /* CONFIG_KM_DEF_ENV */
 
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 8097f28..59f151a 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -146,7 +146,7 @@
 	"config_nc_dhcp=setenv autoload_old ${autoload}; "		\
 		"setenv autoload no "					\
 		"&& bootp "						\
-		"&& setenv ncip ${serverip} "				\
+		"&& setenv ncip "					\
 		"&& setenv autoload ${autoload_old}; "			\
 		"setenv autoload_old\0"					\
 	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; "	\
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 7086d1d..405a842 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -92,7 +92,7 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024) /* 1MiB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024 * 4) /* 4MiB for malloc() */
 
 /*
  * Other required minimal configurations
diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h
new file mode 100644
index 0000000..eb20492
--- /dev/null
+++ b/include/configs/wireless_space.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on the netspace_v2 code which is
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CONFIG_WIRELESS_SPACE_H
+#define _CONFIG_WIRELESS_SPACE_H
+
+/*
+ * Machine number definition
+ */
+#define MACH_TYPE_WIRELESS_SPACE	2500 /* is missing in mach-types.h */
+#define CONFIG_MACH_TYPE		MACH_TYPE_WIRELESS_SPACE
+#define CONFIG_IDENT_STRING		" Wireless Space"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SoC Family Name */
+/* SoC name */
+#define CONFIG_KW88F6281
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* no NOR or SPI flash */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_USB
+
+/*
+ * Core clock definition
+ */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+
+/*
+ * Different SDRAM configuration and size for some of the boards derived
+ * from the Network Space v2
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_RBTREE
+#undef CONFIG_SYS_IDE_MAXBUS
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXBUS           1
+#define CONFIG_SYS_IDE_MAXDEVICE        1
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"ws> "
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable only egiga0... */
+#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
+#define CONFIG_PHY_BASE_ADR 0xa		/* ... through a 'fake' PHY */
+#define CONFIG_MII
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_NETCONSOLE
+#define CONFIG_MV88E61XX_SWITCH
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_MV88E61XX_CMD
+#define CONFIG_CMD_TFTPPUT
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1 /* 8-bit device address */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * Partition support
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * File systems support
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Console configuration
+ */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment variables configurations
+ */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128KB */
+#define CONFIG_ENV_SIZE			0x20000	/* 128KB */
+#define CONFIG_ENV_OFFSET		0x80000	/* env starts here */
+
+/*
+ * Board-specific command to make using buttons etc easier
+ */
+
+#define CONFIG_WIRELESS_SPACE_CMD
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_PREBOOT
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#define CONFIG_BOOTCOMMAND					\
+	"if run usbload || run diskload; then bootm; fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"bootfile=uImage\0"					\
+	"loadaddr=0x800000\0"					\
+	"autoload=no\0"						\
+	"netconsole="						\
+		"set stdin $stdin,nc; "				\
+		"set stdout $stdout,nc; "			\
+		"set stderr $stderr,nc;\0"			\
+	"diskload=ide reset && "				\
+		"ext2load ide 0:1 $loadaddr /boot/$bootfile\0"	\
+	"usbload=usb start && "					\
+		"fatload usb 0:1 $loadaddr /boot/$bootfile\0"	\
+	"preboot="						\
+		"dhcp && run netconsole\0"
+
+#endif /* _CONFIG_WIRELESS_SPACE_H */
diff --git a/include/netdev.h b/include/netdev.h
index b8d303d..7f158d4 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -163,10 +163,9 @@ static inline int pci_eth_init(bd_t *bis)
  * the stuct and enums here are used to specify switch configuration params
  */
 #if defined(CONFIG_MV88E61XX_SWITCH)
-enum mv88e61xx_cfg_vlan {
-	MV88E61XX_VLANCFG_DEFAULT,
-	MV88E61XX_VLANCFG_ROUTER
-};
+
+/* constants for any 88E61xx switch */
+#define MV88E61XX_MAX_PORTS_NUM	6
 
 enum mv88e61xx_cfg_mdip {
 	MV88E61XX_MDIP_NOCHANGE,
@@ -192,7 +191,7 @@ enum mv88e61xx_cfg_prtstt {
 
 struct mv88e61xx_config {
 	char *name;
-	enum mv88e61xx_cfg_vlan vlancfg;
+	u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
 	enum mv88e61xx_cfg_rgmiid rgmii_delay;
 	enum mv88e61xx_cfg_prtstt portstate;
 	enum mv88e61xx_cfg_ledinit led_init;
@@ -201,6 +200,18 @@ struct mv88e61xx_config {
 	u8 cpuport;
 };
 
+/*
+ * Common mappings for Internal VLANs
+ * These mappings consider that all ports are useable; the driver
+ * will mask inexistent/unused ports.
+ */
+
+/* Switch mode : routes any port to any port */
+#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
+
+/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
+#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
+
 int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
 #endif /* CONFIG_MV88E61XX_SWITCH */