diff options
| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-12-15 23:26:31 +0900 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-05 12:08:55 -0500 |
| commit | d622ac39274a949b6445f1bfd92dc1644014388b (patch) | |
| tree | f2f2f587edee722bf5fb6634e4c8e09b9d89592c | |
| parent | 9067b30008e4c09fb6287d306caf2a6bed08370f (diff) | |
| download | u-boot-imx-d622ac39274a949b6445f1bfd92dc1644014388b.zip u-boot-imx-d622ac39274a949b6445f1bfd92dc1644014388b.tar.gz u-boot-imx-d622ac39274a949b6445f1bfd92dc1644014388b.tar.bz2 | |
powerpc: mpc824x: remove MPC824X cpu support
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>
105 files changed, 12 insertions, 16821 deletions
@@ -292,12 +292,6 @@ LIST_8xx="$(targets_by_cpu mpc8xx)" LIST_4xx="$(targets_by_cpu ppc4xx)" ######################################################################### -## MPC824x Systems -######################################################################### - -LIST_824x="$(targets_by_cpu mpc824x)" - -######################################################################### ## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### @@ -186,7 +186,6 @@ Directory Hierarchy: /mpc5xx Files specific to Freescale MPC5xx CPUs /mpc5xxx Files specific to Freescale MPC5xxx CPUs /mpc8xx Files specific to Freescale MPC8xx CPUs - /mpc824x Files specific to Freescale MPC824x CPUs /mpc8260 Files specific to Freescale MPC8260 CPUs /mpc85xx Files specific to Freescale MPC85xx CPUs /ppc4xx Files specific to AMCC PowerPC 4xx CPUs @@ -326,10 +325,6 @@ The following options need to be configured: multiple fs option at one time for marvell soc family -- MPC824X Family Member (if CONFIG_MPC824X is defined) - Define exactly one of - CONFIG_MPC8240, CONFIG_MPC8245 - - 8xx CPU Options: (if using an MPC8xx CPU) CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if get_gclk_freq() cannot work diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 6f96c7c..7a50301 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -19,9 +19,6 @@ config 5xx config MPC5xxx bool "MPC5xxx" -config MPC824X - bool "MPC824X" - config MPC8260 bool "MPC8260" @@ -46,7 +43,6 @@ source "arch/powerpc/cpu/74xx_7xx/Kconfig" source "arch/powerpc/cpu/mpc512x/Kconfig" source "arch/powerpc/cpu/mpc5xx/Kconfig" source "arch/powerpc/cpu/mpc5xxx/Kconfig" -source "arch/powerpc/cpu/mpc824x/Kconfig" source "arch/powerpc/cpu/mpc8260/Kconfig" source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" diff --git a/arch/powerpc/cpu/mpc824x/Kconfig b/arch/powerpc/cpu/mpc824x/Kconfig deleted file mode 100644 index 4f98423..0000000 --- a/arch/powerpc/cpu/mpc824x/Kconfig +++ /dev/null @@ -1,48 +0,0 @@ -menu "mpc824x CPU" - depends on MPC824X - -config SYS_CPU - default "mpc824x" - -choice - prompt "Target select" - -config TARGET_A3000 - bool "Support A3000" - -config TARGET_CPC45 - bool "Support CPC45" - -config TARGET_CU824 - bool "Support CU824" - -config TARGET_EXALION - bool "Support eXalion" - -config TARGET_MUSENKI - bool "Support MUSENKI" - -config TARGET_MVBLUE - bool "Support MVBLUE" - -config TARGET_SANDPOINT8240 - bool "Support Sandpoint8240" - -config TARGET_SANDPOINT8245 - bool "Support Sandpoint8245" - -config TARGET_UTX8245 - bool "Support utx8245" - -endchoice - -source "board/a3000/Kconfig" -source "board/cpc45/Kconfig" -source "board/cu824/Kconfig" -source "board/eXalion/Kconfig" -source "board/musenki/Kconfig" -source "board/mvblue/Kconfig" -source "board/sandpoint/Kconfig" -source "board/utx8245/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile deleted file mode 100644 index 2c8be92..0000000 --- a/arch/powerpc/cpu/mpc824x/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \ - drivers/epic/epic1.o drivers/i2c/i2c.o pci.o -obj-y += ../mpc8260/bedbug_603e.o diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk deleted file mode 100644 index ecfb07e..0000000 --- a/arch/powerpc/cpu/mpc824x/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mstring -mcpu=603e -msoft-float diff --git a/arch/powerpc/cpu/mpc824x/cpu.c b/arch/powerpc/cpu/mpc824x/cpu.c deleted file mode 100644 index eaa4e87..0000000 --- a/arch/powerpc/cpu/mpc824x/cpu.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <mpc824x.h> -#include <common.h> -#include <command.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkcpu (void) -{ - unsigned int pvr = get_pvr (); - unsigned int version = pvr >> 16; - unsigned char revision; - ulong clock = gd->cpu_clk; - char buf[32]; - - puts ("CPU: "); - - switch (version) { - case CPU_TYPE_8240: - puts ("MPC8240"); - break; - - case CPU_TYPE_8245: - puts ("MPC8245"); - break; - - default: - return -1; /*not valid for this source */ - } - - CONFIG_READ_BYTE (REVID, revision); - - if (revision) { - printf (" Revision %d.%d", - (revision & 0xf0) >> 4, - (revision & 0x0f)); - } else { - return -1; /* no valid CPU revision info */ - } - - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ - -int checkicache (void) -{ - /*TODO*/ - return 128 * 4 * 32; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ - -int checkdcache (void) -{ - /*TODO*/ - return 128 * 4 * 32; - -}; - -/*------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr, addr; - - /* Interrupts and MMU off */ - __asm__ ("mtspr 81, 0"); - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~0x1030; - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on - * your system and assign it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; - -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * This is the sys_logic_clk (memory bus) divided by 4 - */ -unsigned long get_tbclk (void) -{ - return ((get_bus_freq (0) + 2L) / 4L); -} - -/* ------------------------------------------------------------------------- */ - -/* - * The MPC824x has an integrated PCI controller known as the MPC107. - * The following are MPC107 Bridge Controller and PCI Support functions - * - */ - -/* - * This procedure reads a 32-bit address MPC107 register, and returns - * a 32 bit value. It swaps the address to little endian before - * writing it to config address, and swaps the value to big endian - * before returning to the caller. - */ -unsigned int mpc824x_mpc107_getreg (unsigned int regNum) -{ - unsigned int temp; - - /* swap the addr. to little endian */ - *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); - temp = *(volatile unsigned int *) CHRP_REG_DATA; - return PCISWAP (temp); /* swap the data upon return */ -} - -/* - * This procedure writes a 32-bit address MPC107 register. It swaps - * the address to little endian before writing it to config address. - */ - -void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal) -{ - /* swap the addr. to little endian */ - *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); - *(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal); - return; -} - - -/* - * Write a byte (8 bits) to a memory location. - */ -void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data) -{ - *(unsigned char *) addr = data; - __asm__ ("sync"); -} - -/* - * Write a word (16 bits) to a memory location after the value - * has been byte swapped (big to little endian or vice versa) - */ - -void mpc824x_mpc107_write16 (unsigned int address, unsigned short data) -{ - *(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data); - __asm__ ("sync"); -} - -/* - * Write a long word (32 bits) to a memory location after the value - * has been byte swapped (big to little endian or vice versa) - */ - -void mpc824x_mpc107_write32 (unsigned int address, unsigned int data) -{ - *(volatile unsigned int *) address = LONGSWAP (data); - __asm__ ("sync"); -} - -/* - * Read a byte (8 bits) from a memory location. - */ -unsigned char mpc824x_mpc107_read8 (unsigned int addr) -{ - return *(volatile unsigned char *) addr; -} - - -/* - * Read a word (16 bits) from a memory location, and byte swap the - * value before returning to the caller. - */ -unsigned short mpc824x_mpc107_read16 (unsigned int address) -{ - unsigned short retVal; - - retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address); - return retVal; -} - - -/* - * Read a long word (32 bits) from a memory location, and byte - * swap the value before returning to the caller. - */ -unsigned int mpc824x_mpc107_read32 (unsigned int address) -{ - unsigned int retVal; - - retVal = LONGSWAP (*(unsigned int *) address); - return (retVal); -} - - -/* - * Read a register in the Embedded Utilities Memory Block address - * space. - * Input: regNum - register number + utility base address. Example, - * the base address of EPIC is 0x40000, the register number - * being passed is 0x40000+the address of the target register. - * (See epic.h for register addresses). - * Output: The 32 bit little endian value of the register. - */ - -unsigned int mpc824x_eummbar_read (unsigned int regNum) -{ - unsigned int temp; - - temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum); - temp = PCISWAP (temp); - return temp; -} - - -/* - * Write a value to a register in the Embedded Utilities Memory - * Block address space. - * Input: regNum - register number + utility base address. Example, - * the base address of EPIC is 0x40000, the register - * number is 0x40000+the address of the target register. - * (See epic.h for register addresses). - * regVal - value to be written to the register. - */ - -void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal) -{ - *(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal); - return; -} - -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c deleted file mode 100644 index 68d88e9..0000000 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor. Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <mpc824x.h> - -#ifndef CONFIG_SYS_BANK0_ROW -#define CONFIG_SYS_BANK0_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK1_ROW -#define CONFIG_SYS_BANK1_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK2_ROW -#define CONFIG_SYS_BANK2_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK3_ROW -#define CONFIG_SYS_BANK3_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK4_ROW -#define CONFIG_SYS_BANK4_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK5_ROW -#define CONFIG_SYS_BANK5_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK6_ROW -#define CONFIG_SYS_BANK6_ROW 0 -#endif -#ifndef CONFIG_SYS_BANK7_ROW -#define CONFIG_SYS_BANK7_ROW 0 -#endif -#ifndef CONFIG_SYS_DBUS_SIZE2 -#define CONFIG_SYS_DBUS_SIZE2 0 -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - */ -void -cpu_init_f (void) -{ - register unsigned long val; - CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ -/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ - -#if defined(CONFIG_MUSENKI) -/* Why is this here, you ask? Try, just try setting 0x8000 - * in PCIACR with CONFIG_WRITE_HALFWORD() - * this one was a stumper, and we are annoyed - */ - -#define M_CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__(" \ - stw %2,0(%0)\n \ - sync\n \ - sth %3,2(%1)\n \ - sync\n \ - " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ - "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ - ); - - M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); -#endif - - CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ - CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */ - /* - * Note that although this bit is cleared after a hard reset, it - * must be explicitly set and then cleared by software during - * initialization in order to guarantee correct operation of the - * DLL and the SDRAM_CLK[0:3] signals (if they are used). - */ - CONFIG_READ_BYTE (AMBOR, val); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); - CONFIG_WRITE_BYTE(AMBOR, val | 0x20); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); -#ifdef CONFIG_MPC8245 - /* silicon bug 28 MPC8245 */ - CONFIG_READ_BYTE(AMBOR,val); - CONFIG_WRITE_BYTE(AMBOR,val|0x1); - -#if 0 - /* - * The following bug only affects older (XPC8245) processors. - * DMA transfers initiated by external devices get corrupted due - * to a hardware scheduling problem. - * - * The effect is: - * when transferring X words, the first 32 words are transferred - * OK, the next 3 x 32 words are 'old' data (from previous DMA) - * while the rest of the X words is xferred fine. - * - * Disabling 3 of the 4 32 word hardware buffers solves the problem - * with no significant performance loss. - */ - - CONFIG_READ_BYTE(PCMBCR,val); - /* in order not to corrupt data which is being read over the PCI bus - * with the PPC as slave, we need to reduce the number of PCMRBs to 1, - * 4.11 in the processor user manual - * */ - -#if 1 - CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */ -#else - CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */ - CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */ - /* default, 4 PCMRBs are used */ -#endif -#endif -#endif - - CONFIG_READ_WORD(PICR1, val); -#if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | - PIRC1_MSK | PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_EN_PCS | - PICR1_CF_APARK ); -#elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_RCS0)) | - PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_NO_BUSW_CK | - PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - CONFIG_READ_WORD(PICR2, val); - val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ - val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ - CONFIG_WRITE_WORD(PICR2, val); - - CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR); -#ifndef CONFIG_SYS_RAMBOOT - CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | - (CONFIG_SYS_BANK0_ROW) | - (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | - (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | - (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | - (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | - (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | - (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | - (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | - (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)); -#endif - -#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL) - CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT | - CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT | - CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT); -#else - CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT); -#endif - -#if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR3, - (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | - (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)); -#elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD(MCCR3, - (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT)); -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -/* this is gross. We think these should all be the same, and various boards - * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if - * its not set, we define it to zero in this file - */ -#if defined(CONFIG_CU824) - CONFIG_WRITE_WORD(MCCR4, - (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - MCCR4_BIT21 | - (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) | - CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | - (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) | - (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); -#elif defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR4, - (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - MCCR4_BIT21 | - (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) | - (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) | - (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); -#elif defined(CONFIG_MPC8245) - CONFIG_READ_WORD(MCCR1, val); - val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */ - - CONFIG_WRITE_WORD(MCCR4, - (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - (CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) | - (CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) | - (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) | - (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) | - (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) | - (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) | - (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - CONFIG_WRITE_WORD(MSAR1, - ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR1, - ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MSAR2, - ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR2, - ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR1, - ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR1, - ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR2, - ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR2, - ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - - CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR); -#ifdef CONFIG_SYS_DLL_MAX_DELAY - CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */ -#endif -#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL) - CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL); -#endif -#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD) - CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */ -#endif /* setup & hold time */ - - CONFIG_WRITE_BYTE(MBER, - CONFIG_SYS_BANK0_ENABLE | - (CONFIG_SYS_BANK1_ENABLE << 1) | - (CONFIG_SYS_BANK2_ENABLE << 2) | - (CONFIG_SYS_BANK3_ENABLE << 3) | - (CONFIG_SYS_BANK4_ENABLE << 4) | - (CONFIG_SYS_BANK5_ENABLE << 5) | - (CONFIG_SYS_BANK6_ENABLE << 6) | - (CONFIG_SYS_BANK7_ENABLE << 7)); - -#ifdef CONFIG_SYS_PGMAX - CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX); -#endif - - /* ! Wait 200us before initialize other registers */ - /*FIXME: write a decent udelay wait */ - __asm__ __volatile__( - " mtctr %0 \n \ - 0: bdnz 0b\n" - : - : "r" (0x10000)); - - CONFIG_READ_WORD(MCCR1, val); - CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ - __asm__ __volatile__("eieio"); -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - return (0); -} diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic.h b/arch/powerpc/cpu/mpc824x/drivers/epic.h deleted file mode 100644 index 2803f63..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic.h +++ /dev/null @@ -1 +0,0 @@ -#include "epic/epic.h" diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/README b/arch/powerpc/cpu/mpc824x/drivers/epic/README deleted file mode 100644 index 5798996..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/README +++ /dev/null @@ -1,102 +0,0 @@ -CONTENT: - - epic.h - epic1.c - epic2.s - -WHAT ARE THESE FILES: - -These files contain MPC8240 (Kahlua) EPIC -driver routines. The driver routines are not -written for any specific operating system. -They serves the purpose of code sample, and -jump-start for using the MPC8240 EPIC unit. - -For the reason of correctness of C language -syntax, these files are compiled by Metaware -C compiler and assembler. - -ENDIAN NOTATION: - -The algorithm is designed for big-endian mode, -software is responsible for byte swapping. - -USAGE: - -1. The host system that is running on MPC8240 - shall link the files listed here. The memory - location of driver routines shall take into - account of that driver routines need to run - in supervisor mode and they process external - interrupts. - - The routine epic_exception shall be called by - exception vector at location 0x500, i.e., - 603e core external exception vector. - -2. The host system is responsible for configuring - the MPC8240 including Embedded Utilities Memory - Block. All EPIC driver functions require the - content of Embedded Utilities Memory Block - Base Address Register, EUMBBAR, as the first - parameter. - -3. Before EPIC unit of MPC8240 can be used, - initialize EPIC unit by calling epicInit - with the corresponding parameters. - - The initialization shall disable the 603e - core External Exception by calling CoreExtIntDisable( ). - Next, call epicInit( ). Last, enable the 603e core - External Exception by calling CoreExtIntEnable( ). - -4. After EPIC unit has been successfully initialized, - epicIntSourceSet( ) shall be used to register each - external interrupt source. Anytime, an external - interrupt source can be disabled or enabled by - calling corresponding function, epicIntDisable( ), - or epicIntEnable( ). - - Global Timers' resource, base count and frequency, - can be changed by calling epicTmFrequencySet( ) - and epicTmBaseSet( ). - - To stop counting a specific global timer, use - the function, epicTmInhibit while epicTmEnable - can be used to start counting a timer. - -5. To mask a set of external interrupts that are - are certain level below, epicIntPrioritySet( ) - can be used. For example, if the processor's - current task priority register is set to 0x7, - only interrupts of priority 0x8 or higher will - be passed to the processor. - - Be careful when using this function. It may - corrupt the current interrupt pending, selector, - and request registers, resulting an invalid vetor. - - After enabling an interrupt, disable it may also - cause an invalid vector. User may consider using - the spurious vector interrupt service routine to - handle this case. - -6. The EPIC driver routines contains a set - of utilities, Set and Get, for host system - to query and modify the desired EPIC source - registers. - -7. Each external interrupt source shall register - its interrupt service routine. The routine - shall contain all interrupt source specific - processes and keep as short as possible. - - Special customized end of interrupt routine - is optional. If it is needed, it shall contain - the external interrupt source specific end of - interrupt process. - - External interrupt exception vector at 0x500 - shall always call the epicEOI just before - rfi instruction. Refer to the routine, - epic_exception, for a code sample. diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h b/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h deleted file mode 100644 index 58f81c5..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic.h +++ /dev/null @@ -1,163 +0,0 @@ -/********************************************************************* - * mpc8240epic.h - EPIC module of the MPC8240 micro-controller - * - * Copyrigh 1999 Motorola Inc. - * - * Modification History: - * ===================== - * 01a,04Feb99,My Created. - * 15Nov200, robt -modified to use in U-Boot - * -*/ - -#ifndef __INCEPICh -#define __INCEPICh - -#define ULONG unsigned long -#define MAXVEC 20 -#define MAXIRQ 5 /* IRQs */ -#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */ - -/* EPIC register addresses */ - -#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */ -#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */ -#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */ -#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */ -#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */ -#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */ -#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */ -#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */ - -#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/ -#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/ -#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/ -#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */ - -#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/ -#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/ -#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/ -#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */ - -#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/ -#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/ -#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/ -#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */ - -#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/ -#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/ -#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/ -#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */ - -#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */ -#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/ -#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */ -#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/ -#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */ -#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/ -#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */ -#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/ -#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */ -#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/ - -#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */ -#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */ -#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */ -#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/ -#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */ -#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/ -#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */ -#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/ -#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */ -#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/ - -#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */ -#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/ -#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */ -#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/ -#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */ -#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/ -#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */ -#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/ -#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */ -#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/ - -#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */ -#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/ -#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */ -#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/ -#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */ -#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/ -#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */ -#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/ -#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */ -#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/ -#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */ -#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/ - -#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/ -#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */ -#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/ -#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */ -#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/ -#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */ -#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/ -#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */ - -#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/ -#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */ -#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */ - -#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */ -#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */ - -/* Error code */ - -#define OK 0 -#define ERROR -1 - -/* function prototypes */ - -void epicVendorId( unsigned int *step, - unsigned int *devId, - unsigned int *venId - ); -void epicFeatures( unsigned int *noIRQs, - unsigned int *noCPUs, - unsigned int *VerId ); -extern void epicInit( unsigned int IRQType, unsigned int clkRatio); -ULONG sysEUMBBARRead ( ULONG regNum ); -void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); -extern void epicTmFrequencySet( unsigned int frq ); -extern unsigned int epicTmFrequencyGet(void); -extern unsigned int epicTmBaseSet( ULONG srcAddr, - unsigned int cnt, - unsigned int inhibit ); -extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); -extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); -extern unsigned int epicTmInhibit( unsigned int timer ); -extern unsigned int epicTmEnable( ULONG srcAdr ); -extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */ -extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */ -extern unsigned char epicIntTaskGet(void); -extern void epicIntTaskSet( unsigned char val ); -extern unsigned int epicIntAck(void); -extern void epicSprSet( unsigned int eumbbar, unsigned char ); -extern void epicConfigGet( unsigned int *clkRatio, - unsigned int *serEnable ); -extern void SrcVecTableInit(void); -extern unsigned int epicModeGet(void); -extern void epicIntEnable(int Vect); -extern void epicIntDisable(int Vect); -extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio); -extern unsigned int epicIntAck(void); -extern void epicEOI(void); -extern int epicCurTaskPrioSet(int Vect); - -struct SrcVecTable - { - ULONG srcAddr; - char srcName[40]; - }; - -#endif /* EPIC_H */ diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c b/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c deleted file mode 100644 index ecbb42d..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic1.c +++ /dev/null @@ -1,517 +0,0 @@ -/************************************************** - * - * copyright @ motorola, 1999 - * - *************************************************/ -#include <mpc824x.h> -#include <common.h> -#include "epic.h" - - -#define PRINT(format, args...) printf(format , ## args) - -typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */ -struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */ - { - { EPIC_EX_INT0_VEC_REG, "External Direct/Serial Source 0"}, - { EPIC_EX_INT1_VEC_REG, "External Direct/Serial Source 1"}, - { EPIC_EX_INT2_VEC_REG, "External Direct/Serial Source 2"}, - { EPIC_EX_INT3_VEC_REG, "External Direct/Serial Source 3"}, - { EPIC_EX_INT4_VEC_REG, "External Direct/Serial Source 4"}, - - { EPIC_SR_INT5_VEC_REG, "External Serial Source 5"}, - { EPIC_SR_INT6_VEC_REG, "External Serial Source 6"}, - { EPIC_SR_INT7_VEC_REG, "External Serial Source 7"}, - { EPIC_SR_INT8_VEC_REG, "External Serial Source 8"}, - { EPIC_SR_INT9_VEC_REG, "External Serial Source 9"}, - { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"}, - { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"}, - { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"}, - { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"}, - { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"}, - { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"}, - - { EPIC_I2C_INT_VEC_REG, "Internal I2C Source"}, - { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"}, - { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"}, - { EPIC_MSG_INT_VEC_REG, "Internal Message Source"}, - }; - -VOIDFUNCPTR intVecTbl[MAXVEC]; /* Interrupt vector table */ - - -/**************************************************************************** -* epicInit - Initialize the EPIC registers -* -* This routine resets the Global Configuration Register, thus it: -* - Disables all interrupts -* - Sets epic registers to reset values -* - Sets the value of the Processor Current Task Priority to the -* highest priority (0xF). -* epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass -* Through or 8259 compatible mode). -* -* If IRQType (input) is Direct IRQs: -* - IRQType is written to the SIE bit of the EPIC Interrupt -* Configuration register (ICR). -* - clkRatio is ignored. -* If IRQType is Serial IRQs: -* - both IRQType and clkRatio will be written to the ICR register -*/ - -void epicInit - ( - unsigned int IRQType, /* Direct or Serial */ - unsigned int clkRatio /* Clk Ratio for Serial IRQs */ - ) - { - ULONG tmp; - - tmp = sysEUMBBARRead(EPIC_GLOBAL_REG); - tmp |= 0xa0000000; /* Set the Global Conf. register */ - sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp); - /* - * Wait for EPIC to reset - CLH - */ - while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1); - sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000); - tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */ - - if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff); - else /* Serial mode */ - { - tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp); - } - - while (epicIntAck() != 0xff) /* Clear all pending interrupts */ - epicEOI(); -} - -/**************************************************************************** - * epicIntEnable - Enable an interrupt source - * - * This routine clears the mask bit of an external, an internal or - * a Timer register to enable the interrupt. - * - * RETURNS: None - */ -void epicIntEnable(int intVec) -{ - ULONG tmp; - ULONG srAddr; - - srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */ - tmp = sysEUMBBARRead(srAddr); - tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */ - tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */ - tmp |= intVec; /* Set Vector number */ - sysEUMBBARWrite(srAddr, tmp); - - return; - } - -/**************************************************************************** - * epicIntDisable - Disable an interrupt source - * - * This routine sets the mask bit of an external, an internal or - * a Timer register to disable the interrupt. - * - * RETURNS: OK or ERROR - * - */ - -void epicIntDisable - ( - int intVec /* Interrupt vector number */ - ) - { - - ULONG tmp, srAddr; - - srAddr = SrcVecTable[intVec].srcAddr; - tmp = sysEUMBBARRead(srAddr); - tmp |= 0x80000000; /* Set the mask bit */ - sysEUMBBARWrite(srAddr, tmp); - return; - } - -/**************************************************************************** - * epicIntSourceConfig - Set properties of an interrupt source - * - * This function sets interrupt properites (Polarity, Sense, Interrupt - * Prority, and Interrupt Vector) of an Interrupt Source. The properties - * can be set when the current source is not in-request or in-service, - * which is determined by the Activity bit. This routine return ERROR - * if the the Activity bit is 1 (in-request or in-service). - * - * This function assumes that the Source Vector/Priority register (input) - * is a valid address. - * - * RETURNS: OK or ERROR - */ - -int epicIntSourceConfig - ( - int Vect, /* interrupt source vector number */ - int Polarity, /* interrupt source polarity */ - int Sense, /* interrupt source Sense */ - int Prio /* interrupt source priority */ - ) - - { - ULONG tmp, newVal; - ULONG actBit, srAddr; - - srAddr = SrcVecTable[Vect].srcAddr; - tmp = sysEUMBBARRead(srAddr); - actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */ - if (actBit == 1) - return ERROR; - - tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */ - newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect; - sysEUMBBARWrite(srAddr, tmp | newVal ); - return (OK); - } - -/**************************************************************************** - * epicIntAck - acknowledge an interrupt - * - * This function reads the Interrupt acknowldge register and return - * the vector number of the highest pending interrupt. - * - * RETURNS: Interrupt Vector number. - */ - -unsigned int epicIntAck(void) -{ - return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG )); -} - -/**************************************************************************** - * epicEOI - signal an end of interrupt - * - * This function writes 0x0 to the EOI register to signal end of interrupt. - * It is usually called after an interrupt routine is served. - * - * RETURNS: None - */ - -void epicEOI(void) - { - sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0); - } - -/**************************************************************************** - * epicCurTaskPrioSet - sets the priority of the Processor Current Task - * - * This function should be called after epicInit() to lower the priority - * of the processor current task. - * - * RETURNS: OK or ERROR - */ - -int epicCurTaskPrioSet - ( - int prioNum /* New priority value */ - ) - { - - if ( (prioNum < 0) || (prioNum > 0xF)) - return ERROR; - sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum); - return OK; - } - - -/************************************************************************ - * function: epicIntTaskGet - * - * description: Get value of processor current interrupt task priority register - * - * note: - ***********************************************************************/ -unsigned char epicIntTaskGet() -{ - /* get the interrupt task priority register */ - ULONG reg; - unsigned char rec; - - reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG ); - rec = ( reg & 0x0F ); - return rec; -} - - -/************************************************************** - * function: epicISR - * - * description: EPIC service routine called by the core exception - * at 0x500 - * - * note: - **************************************************************/ -unsigned int epicISR(void) -{ - return 0; -} - - -/************************************************************ - * function: epicModeGet - * - * description: query EPIC mode, return 0 if pass through mode - * return 1 if mixed mode - * - * note: - *************************************************************/ -unsigned int epicModeGet(void) -{ - ULONG val; - - val = sysEUMBBARRead( EPIC_GLOBAL_REG ); - return (( val & 0x20000000 ) >> 29); -} - - -/********************************************* - * function: epicConfigGet - * - * description: Get the EPIC interrupt Configuration - * return 0 if not error, otherwise return 1 - * - * note: - ********************************************/ -void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable) -{ - ULONG val; - - val = sysEUMBBARRead( EPIC_INT_CONF_REG ); - *clkRatio = ( val & 0x70000000 ) >> 28; - *serEnable = ( val & 0x8000000 ) >> 27; -} - - -/******************************************************************* - * sysEUMBBARRead - Read a 32-bit EUMBBAR register - * - * This routine reads the content of a register in the Embedded - * Utilities Memory Block, and swaps to big endian before returning - * the value. - * - * RETURNS: The content of the specified EUMBBAR register. - */ - -ULONG sysEUMBBARRead - ( - ULONG regNum - ) - { - ULONG temp; - - temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum); - return ( LONGSWAP(temp)); - } - -/******************************************************************* - * sysEUMBBARWrite - Write a 32-bit EUMBBAR register - * - * This routine swaps the value to little endian then writes it to - * a register in the Embedded Utilities Memory Block address space. - * - * RETURNS: N/A - */ - -void sysEUMBBARWrite - ( - ULONG regNum, /* EUMBBAR register address */ - ULONG regVal /* Value to be written */ - ) - { - - *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal); - return ; - } - - -/******************************************************** - * function: epicVendorId - * - * description: return the EPIC Vendor Identification - * register: - * - * siliccon version, device id, and vendor id - * - * note: - ********************************************************/ -void epicVendorId - ( - unsigned int *step, - unsigned int *devId, - unsigned int *venId - ) - { - ULONG val; - val = sysEUMBBARRead( EPIC_VENDOR_ID_REG ); - *step = ( val & 0x00FF0000 ) >> 16; - *devId = ( val & 0x0000FF00 ) >> 8; - *venId = ( val & 0x000000FF ); - } - -/************************************************** - * function: epicFeatures - * - * description: return the number of IRQ supported, - * number of CPU, and the version of the - * OpenEPIC - * - * note: - *************************************************/ -void epicFeatures - ( - unsigned int *noIRQs, - unsigned int *noCPUs, - unsigned int *verId - ) - { - ULONG val; - - val = sysEUMBBARRead( EPIC_FEATURES_REG ); - *noIRQs = ( val & 0x07FF0000 ) >> 16; - *noCPUs = ( val & 0x00001F00 ) >> 8; - *verId = ( val & 0x000000FF ); -} - - -/********************************************************* - * function: epciTmFrequncySet - * - * description: Set the timer frequency reporting register - ********************************************************/ -void epicTmFrequencySet( unsigned int frq ) -{ - sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq); -} - -/******************************************************* - * function: epicTmFrequncyGet - * - * description: Get the current value of the Timer Frequency - * Reporting register - * - ******************************************************/ -unsigned int epicTmFrequencyGet(void) -{ - return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ; -} - - -/**************************************************** - * function: epicTmBaseSet - * - * description: Set the #n global timer base count register - * return 0 if no error, otherwise return 1. - * - * note: - ****************************************************/ -unsigned int epicTmBaseSet - ( - ULONG srcAddr, /* Address of the Timer Base register */ - unsigned int cnt, /* Base count */ - unsigned int inhibit /* 1 - count inhibit */ - ) -{ - - unsigned int val = 0x80000000; - /* First inhibit counting the timer */ - sysEUMBBARWrite(srcAddr, val) ; - - /* set the new value */ - val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31); - sysEUMBBARWrite(srcAddr, val) ; - return 0; -} - -/*********************************************************************** - * function: epicTmBaseGet - * - * description: Get the current value of the global timer base count register - * return 0 if no error, otherwise return 1. - * - * note: - ***********************************************************************/ -unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val ) -{ - *val = sysEUMBBARRead( srcAddr ); - *val = *val & 0x7fffffff; - return 0; -} - -/*********************************************************** - * function: epicTmCountGet - * - * description: Get the value of a given global timer - * current count register - * return 0 if no error, otherwise return 1 - * note: - **********************************************************/ -unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ) -{ - *val = sysEUMBBARRead( srcAddr ); - *val = *val & 0x7fffffff; - return 0; -} - - -/*********************************************************** - * function: epicTmInhibit - * - * description: Stop counting of a given global timer - * return 0 if no error, otherwise return 1 - * - * note: - ***********************************************************/ -unsigned int epicTmInhibit( unsigned int srcAddr ) -{ - ULONG val; - - val = sysEUMBBARRead( srcAddr ); - val |= 0x80000000; - sysEUMBBARWrite( srcAddr, val ); - return 0; -} - -/****************************************************************** - * function: epicTmEnable - * - * description: Enable counting of a given global timer - * return 0 if no error, otherwise return 1 - * - * note: - *****************************************************************/ -unsigned int epicTmEnable( ULONG srcAddr ) -{ - ULONG val; - - val = sysEUMBBARRead( srcAddr ); - val &= 0x7fffffff; - sysEUMBBARWrite( srcAddr, val ); - return 0; -} - -void epicSourcePrint(int Vect) - { - ULONG srcVal; - - srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr); - PRINT("%s\n", SrcVecTable[Vect].srcName); - PRINT("Address = 0x%lx\n", SrcVecTable[Vect].srcAddr); - PRINT("Vector = %ld\n", (srcVal & 0x000000FF) ); - PRINT("Mask = %ld\n", srcVal >> 31); - PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30); - PRINT("Polarity = %ld\n", (srcVal & 0x00800000) >> 23); - PRINT("Sense = %ld\n", (srcVal & 0x00400000) >> 22); - PRINT("Priority = %ld\n", (srcVal & 0x000F0000) >> 16); - } diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S b/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S deleted file mode 100644 index 52d19aa..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epic2.S +++ /dev/null @@ -1,196 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - **************************************/ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/processor.h> - -/********************************************* - * function: CoreExtIntEnable - * - * description: Enable 603e core external interrupt - * - * note: mtmsr is context-synchronization - **********************************************/ - .text - .align 2 - .global CoreExtIntEnable -CoreExtIntEnable: - mfmsr r3 - - ori r3,r3,0x8000 /* enable external interrupt */ - mtmsr r3 - - bclr 20, 0 - -/******************************************* - * function: CoreExtIntDisable - * - * description: Disable 603e core external interrupt - * - * note: - *******************************************/ - .text - .align 2 - .global CoreExtIntDisable -CoreExtIntDisable: - mfmsr r4 - - xor r3,r3,r3 - or r3,r3,r4 - - andis. r4,r4,0xffff - andi. r3,r3,0x7fff /* disable external interrupt */ - - or r3,r3,r4 - mtmsr r3 - - bclr 20, 0 - -/********************************************************* - * function: epicEOI - * - * description: signal the EOI and restore machine status - * Input: r3 - value of eumbbar - * Output: r3 - value of eumbbar - * r4 - ISR vector value - * note: - ********************************************************/ - .text - .align 2 - .global epicEOI -epicEOI: - lis r5,0x0006 /* Build End Of Interrupt Register offset */ - ori r5,r5,0x00b0 - xor r7,r7,r7 /* Clear r7 */ - stwbrx r7,r5,r3 /* Save r7, writing to this register will - * intidate the end of processing the - * highest interrupt. - */ - sync - - /* ---RESTORE MACHINE STATE */ - mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ - or r7,r7,r13 - - andis. r7,r7,0xffff - andi. r13,r13,0x7ffd /* (and disable interrupts) */ - or r13,r13,r7 - mtmsr r13 - - lwz r13,0x1c(r1) /* pull ctr */ - mtctr r13 - - lwz r13,0x18(r1) /* pull xer */ - mtctr r13 - - lwz r13,0x14(r1) /* pull lr */ - mtctr r13 - - lwz r13,0x10(r1) /* Pull SRR1 from stack */ - mtspr SRR1,r13 /* Restore SRR1 */ - - lwz r13,0xc(r1) /* Pull SRR0 from stack */ - mtspr SRR0,r13 /* Restore SRR0 */ - - lwz r13,0x8(r1) /* Pull User stack pointer from stack */ - mtspr SPRG1,r13 /* Restore SPRG1 */ - - lwz r4,0x4(r1) /* vector value */ - lwz r3,0x0(r1) /* eumbbar */ - sync - - addi r1,r1,0x20 /* Deallocate stack */ - mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */ - mfspr r1,SPRG1 /* Restore User stack pointer */ - - bclr 20,0 - -/*********************************************************** - * function: exception routine called by exception vector - * at 0x500, external interrupt - * - * description: Kahlua EPIC controller - * - * input: r3 - content of eumbbar - * output: r3 - ISR return value - * r4 - Interrupt vector number - * note: - ***********************************************************/ - - .text - .align 2 - .global epic_exception - -epic_exception: - - /*---SAVE MACHINE STATE TO A STACK */ - mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */ - mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */ - - stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */ - - mfspr r3,SPRG1 /* Push User stack pointer onto stack */ - stw r3,0x8(r1) - mfspr r3,SRR0 /* Push SRR0 onto stack */ - stw r1,0xc(r1) - mfspr r3,SRR1 /* Push SRR1 onto stack */ - stw r3,0x10(r1) - mflr r3 - stw r3,0x14(r1) /* Push LR */ - mfxer r3 - stw r3,0x18(r1) /* Push Xer */ - mfctr r3 - stw r3,0x1c(r1) /* Push CTR */ - - mtspr SPRG0,r1 /* Save updated Supervisor stack pointer - * value to SPRG0 - */ - mfmsr r3 - ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ - mtmsr r3 - - /* ---READ IN THE EUMBAR REGISTER */ - lwz r6,0(r1) /* this is eumbbar */ - sync - - /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ - lis r5,0x0006 /* Build Interrupt Acknowledge Register - * offset - */ - ori r5,r5,0x00a0 - lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ - sync - - /* --MASK OFF ALL BITS EXCEPT THE VECTOR */ - xor r3,r3,r3 - xor r4,r4,r4 - or r3, r3, r6 /* eumbbar in r3 */ - andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ - - stw r4,0x04(r1) /* save the vector value */ - - lis r5,epicISR@ha - ori r5,r5,epicISR@l - mtlr r5 - blrl - - xor r30,r30,r30 - or r30,r30,r3 /* save the r3 which containts the return value from epicISR */ - - /* ---READ IN THE EUMBAR REGISTER */ - lwz r3,0(r1) - sync - - lis r5,epicEOI@ha - ori r5,r5,epicEOI@l - mtlr r5 - blrl - - xor r3,r3,r3 - or r3,r3,r30 /* restore the ISR return value */ - - bclr 20,0 diff --git a/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S b/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S deleted file mode 100644 index 4877050..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/epic/epicutil.S +++ /dev/null @@ -1,57 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - * - * This file contains two commonly used - * lower level utility routines. - * - * The utility routines are also in other - * Kahlua device driver libraries. The - * need to be linked in only once. - **************************************/ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -/********************************************************** - * function: load_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * - * output: r3 - register content - **********************************************************/ - .text - .align 2 - .global load_runtime_reg - -load_runtime_reg: - - xor r5,r5,r5 - or r5,r5,r3 /* save eumbbar */ - - lwbrx r3,r4,r5 - sync - - bclr 20, 0 - -/**************************************************************** - * function: store_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * r5 - new value to be stored - * - ****************************************************************/ - .text - .align 2 - .global store_runtime_reg -store_runtime_reg: - - xor r0,r0,r0 - - stwbrx r5, r4, r3 - sync - - bclr 20,0 diff --git a/arch/powerpc/cpu/mpc824x/drivers/errors.h b/arch/powerpc/cpu/mpc824x/drivers/errors.h deleted file mode 100644 index 20794a2..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/errors.h +++ /dev/null @@ -1,212 +0,0 @@ -/* Copyright Motorola, Inc. 1993, 1994 - ALL RIGHTS RESERVED - - You are hereby granted a copyright license to use, modify, and - distribute the SOFTWARE so long as this entire notice is retained - without alteration in any modified and/or redistributed versions, - and that such modified versions are clearly identified as such. - No licenses are granted by implication, estoppel or otherwise under - any patents or trademarks of Motorola, Inc. - - The SOFTWARE is provided on an "AS IS" basis and without warranty. - To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS - ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED - WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS - THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. - - To the maximum extent permitted by applicable law, IN NO EVENT SHALL - MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER - (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF - BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS - INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR - INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility - for the maintenance and support of the SOFTWARE. - -*/ - - -#include "config.h" - -/* - 1 2 3 4 5 6 7 8 -01234567890123456789012345678901234567890123456789012345678901234567890123456789 -*/ -/* List define statements here */ - -/* These are for all the toolboxes and functions to use. These will help -to standardize the error handling in the current project */ - - /* this is the "data type" for the error - messages in the system */ -#define STATUS unsigned int - - /* this is a success status code */ -#define SUCCESS 1 - - /* likewise this is failure */ -#define FAILURE 0 - -#define NUM_ERRORS 47 - -/* This first section of "defines" are for error codes ONLY. The called - routine will return one of these error codes to the caller. If the final - returned code is "VALID", then everything is a-okay. However, if one - of the functions returns a non-valid status, that error code should be - propogated back to all the callers. At the end, the last caller will - call an error_processing function, and send in the status which was - returned. It's up to the error_processing function to determine which - error occured (as indicated by the status), and print an appropriate - message back to the user. -*/ -/*----------------------------------------------------------------------*/ -/* these are specifically for the parser routines */ - -#define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */ -#define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/ -#define ILLEGAL_RD_STAGE 0xfb02 /* cannot specify reg. family in range*/ -#define ILLEGAL_REG_FAMILY 0xfb03 /* "cannot specify a range of special - or miscellaneous registers"*/ -#define RANGE_CROSS_FAMILY 0xfb04 /* "cannot specify a range across - register families" */ -#define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */ -#define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/ -#define INVALID_FILENAME 0xfb07 /* "invalid download filename" */ -#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ -#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ -#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */ - - -/*----------------------------------------------------------------------*/ -/* these are for the error checking toolbox */ - -#define INVALID 0xfd00 /* NOT valid */ -#define VALID 0xfd01 /* valid */ - - /* This error is found in the fcn: - is_right_size_input() to indicate - that the input was not 8 characters - long. */ -#define INVALID_SIZE 0xfd02 - - /* This error is found in the fcn: - is_valid_address_range() to indicate - that the address given falls outside - of valid memory defined by MEM_START - to MEM_END. - */ -#define OUT_OF_BOUNDS_ADDRESS 0xfd03 - - /* This error is found in the fcn: - is_valid_hex_input() to indicate that - one of more of the characters entered - are not valid hex characters. Valid - hex characters are 0-9, A-F, a-f. - */ -#define INVALID_HEX_INPUT 0xfd04 - - /* This error is found in the fcn: - is_valid_register_number() to indicate - that a given register does not exist. - */ -#define REG_NOT_READABLE 0xfd05 - - /* This error is found in the fcn: - is_word_aligned_address() to indicate - that the given address is not word- - aligned. A word-aligned address ends - in 0x0,0x4,0x8,0xc. - */ -#define NOT_WORD_ALIGNED 0xfd07 - - /* This error is found in the fcn: - is_valid_address_range() to indicate - that the starting address is greater - than the ending address. - */ -#define REVERSED_ADDRESS 0xfd08 - - /* this error tells us that the address - specified as the destination is within - the source addresses */ -#define RANGE_OVERLAP 0xfd09 - - -#define ERROR 0xfd0a /* An error occured */ -#define INVALID_PARAM 0xfd0b /* "invalid input parameter " */ - - -#define INVALID_FLAG 0xfd0c /* invalid flag */ - -/*----------------------------------------------------------------------*/ -/* these are for the getarg toolbox */ - -#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ -#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/ - - -/*----------------------------------------------------------------------*/ -/* these are for the tokenizer toolbox */ - -#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ -#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ -#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ -#define INVALID_STRING 0xFF03 /* unable to extract string from input */ -#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ -#define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/ -#define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */ -#define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */ -#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */ - - -/* these are for the read from screen toolbox */ - -#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/ - - -/* these are for the breakpoint routines */ - -#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */ - - -/* THESE are for the downloader */ - -#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ -#define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */ -#define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */ -#define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */ - - -/* these are for the compression and decompression stuff */ - -#define COMP_UNK_CHARACTER 0xf800 /* "unknown compressed character " */ - -#define COMP_UNKNOWN_STATE 0xf801 /* "unknown binary state" */ - -#define NOT_IN_COMPRESSED_FORMAT 0xf802 /* not in compressed S-Record format */ - - -/* these are for the DUART handling things */ - - /* "unrecognized serial port configuration" */ -#define UNKNOWN_PORT_STATE 0xf700 - - -/* these are for the register toolbox */ - - /* "cannot find register in special - purpose register file " */ -#define SPR_NOT_FOUND 0xf600 - - -/* these are for the duart specific stuff */ - - /* "transparent mode needs access to - two serial ports" */ -#define TM_NEEDS_BOTH_PORTS 0xf500 - - -/*----------------------------------------------------------------------*/ -/* these are specifically for the flash routines */ -#define FLASH_ERROR 0xf100 /* general flash error */ diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c b/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c deleted file mode 100644 index 3638ab0..0000000 --- a/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2003 - * Gleb Natapov <gnatapov@mrv.com> - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#undef I2CDBG - -#ifdef CONFIG_HARD_I2C -#include <i2c.h> - -#define TIMEOUT (CONFIG_SYS_HZ/4) - -#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[1] -#define I2CCCR &I2C_Addr[2] -#define I2CCSR &I2C_Addr[3] -#define I2CCDR &I2C_Addr[4] - -#define MPC107_CCR_MEN 0x80 -#define MPC107_CCR_MIEN 0x40 -#define MPC107_CCR_MSTA 0x20 -#define MPC107_CCR_MTX 0x10 -#define MPC107_CCR_TXAK 0x08 -#define MPC107_CCR_RSTA 0x04 - -#define MPC107_CSR_MCF 0x80 -#define MPC107_CSR_MAAS 0x40 -#define MPC107_CSR_MBB 0x20 -#define MPC107_CSR_MAL 0x10 -#define MPC107_CSR_SRW 0x04 -#define MPC107_CSR_MIF 0x02 -#define MPC107_CSR_RXAK 0x01 - -#define I2C_READ 1 -#define I2C_WRITE 0 - -/* taken from linux include/asm-ppc/io.h */ -inline unsigned in_le32 (volatile unsigned *addr) -{ - unsigned ret; - - __asm__ __volatile__ ("lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync":"=r" (ret): "r" (addr), "m" (*addr)); - return ret; -} - -inline void out_le32 (volatile unsigned *addr, int val) -{ - __asm__ __volatile__ ("stwbrx %1,0,%2; eieio":"=m" (*addr):"r" (val), - "r" (addr)); -} - -#define writel(val, addr) out_le32(addr, val) -#define readl(addr) in_le32(addr) - -void i2c_init (int speed, int slaveadd) -{ - /* stop I2C controller */ - writel (0x0, I2CCCR); - /* set clock */ - writel (0x1020, I2CFDR); - /* write slave address */ - writel (slaveadd, I2CADR); - /* clear status register */ - writel (0x0, I2CCSR); - /* start I2C controller */ - writel (MPC107_CCR_MEN, I2CCCR); - - return; -} - -static __inline__ int i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - - while (readl (I2CCSR) & MPC107_CSR_MBB) - if (get_timer (timeval) > TIMEOUT) - return -1; - - return 0; -} - -static __inline__ int i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer (0); - - do { - csr = readl (I2CCSR); - - if (!(csr & MPC107_CSR_MIF)) - continue; - - writel (0x0, I2CCSR); - - if (csr & MPC107_CSR_MAL) { -#ifdef I2CDBG - printf ("i2c_wait: MAL\n"); -#endif - return -1; - } - - if (!(csr & MPC107_CSR_MCF)) { -#ifdef I2CDBG - printf ("i2c_wait: unfinished\n"); -#endif - return -1; - } - - if (write == I2C_WRITE && (csr & MPC107_CSR_RXAK)) { -#ifdef I2CDBG - printf ("i2c_wait: No RXACK\n"); -#endif - return -1; - } - - return 0; - } while (get_timer (timeval) < TIMEOUT); - -#ifdef I2CDBG - printf ("i2c_wait: timed out\n"); -#endif - return -1; -} - -static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX | - (rsta ? MPC107_CCR_RSTA : 0), I2CCCR); - - writel ((dev << 1) | dir, I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int __i2c_write (u8 * data, int length) -{ - int i; - - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX, I2CCCR); - - for (i = 0; i < length; i++) { - writel (data[i], I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int __i2c_read (u8 * data, int length) -{ - int i; - - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | - ((length == 1) ? MPC107_CCR_TXAK : 0), I2CCCR); - - /* dummy read */ - readl (I2CCDR); - - for (i = 0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | - MPC107_CCR_TXAK, I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writel (MPC107_CCR_MEN | MPC107_CCR_TXAK, I2CCCR); - - data[i] = readl (I2CCDR); - } - - return i; -} - -int i2c_read (u8 dev, uint addr, int alen, u8 * data, int length) -{ - int i = 0; - u8 *a = (u8 *) & addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - -exit: - writel (MPC107_CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_write (u8 dev, uint addr, int alen, u8 * data, int length) -{ - int i = 0; - u8 *a = (u8 *) & addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - -exit: - writel (MPC107_CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an <ACK> back. - */ - udelay (10000); - return i2c_read (chip, 0, 1, (uchar *) &tmp, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc824x/interrupts.c b/arch/powerpc/cpu/mpc824x/interrupts.c deleted file mode 100644 index fad103f..0000000 --- a/arch/powerpc/cpu/mpc824x/interrupts.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/pci_io.h> -#include <commproc.h> -#include "drivers/epic.h" - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - *decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ; - - /* - * It's all broken at the moment and I currently don't need - * interrupts. If you want to fix it, have a look at the epic - * drivers in dink32 v12. They do everthing and Motorola said - * I could use the dink source in this project as long as - * copyright notices remain intact. - */ - - epicInit (EPIC_DIRECT_IRQ, 0); - /* EPIC won't generate INT unless Current Task Pri < 15 */ - epicCurTaskPrioSet(0); - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - register unsigned long temp; - - pci_readl (CONFIG_SYS_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); - sync (); /* i'm not convinced this is needed, but dink source has it */ - temp &= 0xff; /*get vector */ - - /*TODO: handle them -... */ - epicEOI (); -} - -/****************************************************************************/ - -/* - * blank int handlers. - */ - -void -irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ -} - -void irq_free_handler (int vec) -{ - -} - -/*TODO: some handlers for winbond and 87308 interrupts - and what about generic pci inteerupts? - vga? - */ - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} diff --git a/arch/powerpc/cpu/mpc824x/pci.c b/arch/powerpc/cpu/mpc824x/pci.c deleted file mode 100644 index 1257b08..0000000 --- a/arch/powerpc/cpu/mpc824x/pci.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * arch/powerpc/kernel/mpc10x_common.c - * - * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, - * Mem ctlr, EPIC, etc. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Copyright 2001 MontaVista Software Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#ifdef CONFIG_PCI - -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> -#include <mpc824x.h> - -void pci_mpc824x_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - CHRP_PCI_MEMORY_BUS, - CHRP_PCI_MEMORY_PHYS, - CHRP_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CHRP_PCI_MEM_BUS, - CHRP_PCI_MEM_PHYS, - CHRP_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CHRP_ISA_MEM_BUS, - CHRP_ISA_MEM_PHYS, - CHRP_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CHRP_PCI_IO_BUS, - CHRP_PCI_IO_PHYS, - CHRP_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CHRP_ISA_IO_BUS, - CHRP_ISA_IO_PHYS, - CHRP_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - CHRP_REG_ADDR, - CHRP_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} - -#endif diff --git a/arch/powerpc/cpu/mpc824x/speed.c b/arch/powerpc/cpu/mpc824x/speed.c deleted file mode 100644 index e6064a1..0000000 --- a/arch/powerpc/cpu/mpc824x/speed.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on - * PCI_SYNC_IN . - * - * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240 - * boards. It should be defined as the PCI to Memory Multiplier as - * documented in the MPC8240 Hardware Specs. - * - * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER - * because they can determine it from the PCR. - * - * Gary Milliorn <gary.milliorn@motorola.com> (who should know since - * he designed the Sandpoint) told us that the PCR is not in all revs - * of the MPC8240 CPU, so it's not guaranteeable and we cannot do - * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether. - */ -/* ------------------------------------------------------------------------- */ - -/* This gives the PCI to Memory multiplier times 10 */ -/* The index is the value of PLL_CFG[0:4] */ -/* This is documented in the MPC8240/5 Hardware Specs */ - -short pll_pci_to_mem_multiplier[] = { -#if defined(CONFIG_MPC8240) - 30, 30, 10, 10, 20, 10, 0, 10, - 10, 0, 20, 0, 20, 0, 20, 0, - 30, 0, 15, 0, 20, 0, 20, 0, - 25, 0, 10, 0, 15, 15, 0, 0, -#elif defined(CONFIG_MPC8245) - 30, 30, 10, 10, 20, 10, 10, 10, - 10, 20, 20, 15, 20, 15, 20, 30, - 30, 40, 15, 40, 20, 25, 20, 40, - 25, 20, 10, 20, 15, 15, 15, 0, -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -}; - -#define CU824_PLL_STATE_REG 0xFE80002F -#define PCR 0x800000E2 - -/* ------------------------------------------------------------------------- */ - -/* compute the memory bus clock frequency */ -ulong get_bus_freq (ulong dummy) -{ - unsigned char pll_cfg; -#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824) - return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER); -#elif defined(CONFIG_CU824) - pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG); - pll_cfg &= 0x1f; -#else - CONFIG_READ_BYTE(PCR, pll_cfg); - pll_cfg = (pll_cfg >> 3) & 0x1f; -#endif - return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10; -} - - -/* ------------------------------------------------------------------------- */ - -/* This gives the Memory to CPU Core multiplier times 10 */ -/* The index is the value of PLLRATIO in HID1 */ -/* This is documented in the MPC8240 Hardware Specs */ -/* This is not documented for MPC8245 ? FIXME */ -short pllratio_to_factor[] = { - 0, 0, 0, 10, 20, 20, 25, 45, - 30, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 10, 0, 0, 0, 45, - 30, 0, 40, 0, 0, 0, 35, 0, -}; - -/* compute the CPU and memory bus clock frequencies */ -int get_clocks (void) -{ - uint hid1 = mfspr(HID1); - hid1 = (hid1 >> (32-5)) & 0x1f; - gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5) - / 10; - gd->bus_clk = get_bus_freq(0); - return (0); -} diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S deleted file mode 100644 index 55238df..0000000 --- a/arch/powerpc/cpu/mpc824x/start.S +++ /dev/null @@ -1,724 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0x00000100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include <asm-offsets.h> -#include <config.h> -#include <mpc824x.h> -#include <version.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/u-boot.h> - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* FP, Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI ) - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set FP, ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - addis r0,0,0x0000 /* lets make sure that r0 is really 0 */ - mtspr HID0, r0 /* disable I and D caches */ - - mfspr r3, ICR /* clear Interrupt Cause Register */ - - mfmsr r3 /* turn off address translation */ - addis r4,0,0xffff - ori r4,r4,0xffcf - and r3,r3,r4 - mtmsr r3 - isync - sync /* the MMU should be off... */ - - -in_flash: - /* - * Setup BATs - cannot be done in C since we don't have a stack yet - */ - bl setup_bats - - /* Enable MMU. - */ - mfmsr r3 - ori r3, r3, (MSR_IR | MSR_DR) - mtmsr r3 - - /* Enable and invalidate data cache. - */ - mfspr r3, HID0 - mr r2, r3 - ori r3, r3, HID0_DCE | HID0_DCI - ori r2, r2, HID0_DCE - sync - mtspr HID0, r3 - mtspr HID0, r2 - sync - - /* Allocate Initial RAM in data cache. - */ - lis r3, CONFIG_SYS_INIT_RAM_ADDR@h - ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - li r2, 128 - mtctr r2 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock way0 in data cache. - */ - mfspr r3, 1011 - lis r2, 0xffff - ori r2, r2, 0xff1f - and r3, r3, r2 - ori r3, r3, 0x0080 - sync - mtspr 1011, r3 - - /* - * Thisk the stack pointer *somewhere* sensible. Doesnt - * matter much where as we'll move it when we relocate - */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - bl board_init_f /* run 1st part of board init code (from Flash) */ - - /* NOTREACHED - board_init_f() does not return */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = EXC_OFF_ALIGN -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = EXC_OFF_PROGRAM -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - - STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException) - - STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException) - STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException) - - STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException) - STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException) - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - STD_EXCEPTION(0x1c00, ReservedC, UnknownException) - STD_EXCEPTION(0x1d00, ReservedD, UnknownException) - STD_EXCEPTION(0x1e00, ReservedE, UnknownException) - STD_EXCEPTION(0x1f00, ReservedF, UnknownException) - - STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) -#if 0 - andi. r23,r23,MSR_PR - mfspr r23,SPRG3 /* if from user, fix up tss.regs */ - beq 2f - addi r24,r1,STACK_FRAME_OVERHEAD - stw r24,PT_REGS(r23) -2: addi r2,r23,-TSS /* set r2 to current */ - tovirt(r2,r2,r23) -#endif - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ -#if 0 - addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ - cmplw 0,r1,r2 - cmplw 1,r1,r24 - crand 1,1,4 - bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ -#endif - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - ori r20,r20,0x30 /* enable IR, DR */ - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* Cache functions. -*/ - .globl icache_enable -icache_enable: - mfspr r5,HID0 /* turn on the I cache. */ - ori r5,r5,0x8800 /* Instruction cache only! */ - addis r6,0,0xFFFF - ori r6,r6,0xF7FF - and r6,r5,r6 /* clear the invalidate bit */ - sync - mtspr HID0,r5 - mtspr HID0,r6 - isync - sync - blr - - .globl icache_disable -icache_disable: - mfspr r5,HID0 - addis r6,0,0xFFFF - ori r6,r6,0x7FFF - and r5,r5,r6 - sync - mtspr HID0,r5 - isync - sync - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */ - andi. r3, r3, 1 - blr - - .globl dcache_enable -dcache_enable: - mfspr r5,HID0 /* turn on the D cache. */ - ori r5,r5,0x4400 /* Data cache only! */ - mfspr r4, PVR /* read PVR */ - srawi r3, r4, 16 /* shift off the least 16 bits */ - cmpi 0, 0, r3, 0xC /* Check for Max pvr */ - bne NotMax - ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */ -NotMax: - addis r6,0,0xFFFF - ori r6,r6,0xFBFF - and r6,r5,r6 /* clear the invalidate bit */ - sync - mtspr HID0,r5 - mtspr HID0,r6 - isync - sync - blr - - .globl dcache_disable -dcache_disable: - mfspr r5,HID0 - addis r6,0,0xFFFF - ori r6,r6,0xBFFF - and r5,r5,r6 - sync - mtspr HID0,r5 - isync - sync - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */ - andi. r3, r3, 1 - blr - - .globl dc_read -dc_read: -/*TODO : who uses this, what should it do? -*/ - blr - - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ -#ifdef CONFIG_SYS_RAMBOOT - lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_SDRAM_BASE@l -#else - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l -#endif - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -4: -/* Unlock the data cache and invalidate locked area */ - xor r0, r0, r0 - mtspr 1011, r0 - lis r4, CONFIG_SYS_INIT_RAM_ADDR@h - ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l - li r0, 128 - mtctr r0 -41: - dcbi r0, r4 - addi r4, r4, 32 - bdnz 41b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ - cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - blt 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - - /* Setup the BAT registers. - */ -setup_bats: - lis r4, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - lis r3, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - lis r4, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - lis r3, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - lis r4, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - lis r3, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - lis r4, CONFIG_SYS_DBAT1L@h - ori r4, r4, CONFIG_SYS_DBAT1L@l - lis r3, CONFIG_SYS_DBAT1U@h - ori r3, r3, CONFIG_SYS_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - lis r4, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - lis r3, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - lis r4, CONFIG_SYS_DBAT2L@h - ori r4, r4, CONFIG_SYS_DBAT2L@l - lis r3, CONFIG_SYS_DBAT2U@h - ori r3, r3, CONFIG_SYS_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - lis r4, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - lis r3, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - lis r4, CONFIG_SYS_DBAT3L@h - ori r4, r4, CONFIG_SYS_DBAT3L@l - lis r3, CONFIG_SYS_DBAT3U@h - ori r3, r3, CONFIG_SYS_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - - /* Invalidate TLBs. - * -> for (val = 0; val < 0x20000; val+=0x1000) - * -> tlbie(val); - */ - lis r3, 0 - lis r5, 2 - -1: - tlbie r3 - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 - blt 1b - - blr diff --git a/arch/powerpc/cpu/mpc824x/traps.c b/arch/powerpc/cpu/mpc824x/traps.c deleted file mode 100644 index 6abf41d..0000000 --- a/arch/powerpc/cpu/mpc824x/traps.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include <common.h> -#include <asm/processor.h> - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x00400000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds deleted file mode 100644 index 04aba84..0000000 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 2ed51b1..db8cc8c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1360,8 +1360,6 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #elif defined(CONFIG_MPC8260) #define _machine _MACH_8260 #define have_of 0 -#elif defined(CONFIG_SANDPOINT) -#define _machine _MACH_sandpoint #else #error "Machine not defined correctly" #endif diff --git a/board/a3000/Kconfig b/board/a3000/Kconfig deleted file mode 100644 index 21a9e48..0000000 --- a/board/a3000/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_A3000 - -config SYS_BOARD - default "a3000" - -config SYS_CONFIG_NAME - default "A3000" - -endif diff --git a/board/a3000/MAINTAINERS b/board/a3000/MAINTAINERS deleted file mode 100644 index 303e5fd..0000000 --- a/board/a3000/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -A3000 BOARD -#M: - -S: Maintained -F: board/a3000/ -F: include/configs/A3000.h -F: configs/A3000_defconfig diff --git a/board/a3000/Makefile b/board/a3000/Makefile deleted file mode 100644 index 9b9b048..0000000 --- a/board/a3000/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = a3000.o flash.o diff --git a/board/a3000/README b/board/a3000/README deleted file mode 100644 index f0e92c5..0000000 --- a/board/a3000/README +++ /dev/null @@ -1,17 +0,0 @@ -U-Boot for Artis SBC-A3000 ---------------------------- - -Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB) -or 28F064J3A (8MB) chips. - -In board's notation, bank 0 is the one at the address of 0xFF000000. -bank 1 is the one at the address of 0xFF800000 - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFFFE0000. - -There is a National ns83815 10/100M ethernet controller on-board. diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c deleted file mode 100644 index 3e2f6b0..0000000 --- a/board/a3000/a3000.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * Modified during 2003 by - * Ken Chou, kchou@ieee.org - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <pci.h> -#include <netdev.h> - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_a3000_config_table[] = { - /* vendor, device, class */ - /* bus, dev, func */ - { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ - pci_cfgfunc_config_device, { PCI_ENET2_IOADDR, - PCI_ENET2_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */ - pci_cfgfunc_config_device, { PCI_ENET3_IOADDR, - PCI_ENET3_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_a3000_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/a3000/flash.c b/board/a3000/flash.c deleted file mode 100644 index f2dd3c2..0000000 --- a/board/a3000/flash.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <mpc824x.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - - -/*---------------------------------------------------------------------*/ -#define DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define BS(b) (b) -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS; - unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - - DEBUGF("Get flash bank %d @ 0x%08lx\n", i, flash_banks[i]); -/* - size_b[i] = flash_get_size((vu_char *)flash_banks[i], &flash_info[i]); -*/ - size_b[i] = flash_get_size((vu_char *) 0xff800000 , &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) - { - printf ("## Unknown FLASH on Bank %d: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - i, flash_info[i].flash_id, - size_b[i], size_b[i]<<20); - } - else - { - DEBUGF("## Flash bank %d at 0x%08lx sizes: 0x%08lx \n", - i, flash_banks[i], size_b[i]); - - flash_get_offsets (flash_banks[i], &flash_info[i]); - flash_info[i].size = size_b[i]; - } - } - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - size = 0; - DEBUGF("## Final Flash bank sizes: "); - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) - { - DEBUGF("%08lx ", size_b[i]); - size += size_b[i]; - } - DEBUGF("\n"); - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - -#if 1 - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -#endif - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cpc45/Kconfig b/board/cpc45/Kconfig deleted file mode 100644 index c564caf..0000000 --- a/board/cpc45/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CPC45 - -config SYS_BOARD - default "cpc45" - -config SYS_CONFIG_NAME - default "CPC45" - -endif diff --git a/board/cpc45/MAINTAINERS b/board/cpc45/MAINTAINERS deleted file mode 100644 index 163e09c..0000000 --- a/board/cpc45/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -CPC45 BOARD -M: Josef Wagner <Wagner@Microsys.de> -S: Maintained -F: board/cpc45/ -F: include/configs/CPC45.h -F: configs/CPC45_defconfig -F: configs/CPC45_ROMBOOT_defconfig diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile deleted file mode 100644 index 1310f93..0000000 --- a/board/cpc45/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpc45.o flash.o plx9030.o pd67290.o ide.o diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c deleted file mode 100644 index f182e79..0000000 --- a/board/cpc45/cpc45.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> -#include <i2c.h> -#include <netdev.h> - -int sysControlDisplay(int digit, uchar ascii_code); -extern void Plx9030Init(void); -extern void SPD67290Init(void); - - /* We have to clear the initial data area here. Couldn't have done it - * earlier because DRAM had not been initialized. - */ -int board_early_init_f(void) -{ - - /* enable DUAL UART Mode on CPC45 */ - *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */ - - return 0; -} - -int checkboard(void) -{ -/* - char revision = BOARD_REV; -*/ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - puts ("CPC45 "); -/* - printf("Revision %d ", revision); -*/ - printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); - - return 0; -} - -phys_size_t initdram (int board_type) -{ - int m, row, col, bank, i, ref; - unsigned long start, end; - uint32_t mccr1, mccr2; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - unsigned int tmp; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (i2c_reg_read (0x50, 2) != 0x04) - return 0; /* Memory type */ - - m = i2c_reg_read (0x50, 5); /* # of physical banks */ - row = i2c_reg_read (0x50, 3); /* # of rows */ - col = i2c_reg_read (0x50, 4); /* # of columns */ - bank = i2c_reg_read (0x50, 17); /* # of logical banks */ - ref = i2c_reg_read (0x50, 12); /* refresh rate / type */ - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - CONFIG_READ_WORD(MCCR2, mccr2); - mccr2 &= 0xffff0000; - - start = CONFIG_SYS_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - switch(ref) { - case 0x00: - case 0x80: - tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22; - break; - case 0x01: - case 0x81: - tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22; - break; - case 0x02: - case 0x82: - tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22; - break; - case 0x03: - case 0x83: - tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22; - break; - case 0x04: - case 0x84: - tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22; - break; - case 0x05: - case 0x85: - tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22; - break; - default: - tmp = 0x512; - break; - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - - -/* - * Initialize PCI Devices, report devices found. - */ - -static struct pci_config_table pci_cpc45_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR, - PCI_PLX9030_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCMCIA_IO_BASE, - PCMCIA_IO_BASE, - PCI_COMMAND_MEMORY | PCI_COMMAND_IO }}, -#endif /*CONFIG_PCI_PNP*/ - { } -}; - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_cpc45_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); - - /* init PCI_to_LOCAL Bus BRIDGE */ - Plx9030Init(); - - /* Clear Display */ - DISP_CWORD = 0x0; - - sysControlDisplay(0,' '); - sysControlDisplay(1,'C'); - sysControlDisplay(2,'P'); - sysControlDisplay(3,'C'); - sysControlDisplay(4,' '); - sysControlDisplay(5,'4'); - sysControlDisplay(6,'5'); - sysControlDisplay(7,' '); - -} - -/************************************************************************** -* -* sysControlDisplay - controls one of the Alphanum. Display digits. -* -* This routine will write an ASCII character to the display digit requested. -* -* SEE ALSO: -* -* RETURNS: NA -*/ - -int sysControlDisplay (int digit, /* number of digit 0..7 */ - uchar ascii_code /* ASCII code */ - ) -{ - if ((digit < 0) || (digit > 7)) - return (-1); - - *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code; - - return (0); -} - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - rc = i82365_init(); - - return rc; -} - -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c deleted file mode 100644 index 917db34..0000000 --- a/board/cpc45/flash.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT_SIZE 0x8000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t * info, ulong dest, ulong * data); -static void write_via_fpu (vu_long * addr, ulong * data); -static __inline__ unsigned long get_msr (void); -static __inline__ void set_msr (unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - uchar tempChar; - vu_long *tmpaddr; - - /* Enable flash writes on CPC45 */ - - tempChar = BOARD_CTRL; - - tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1); - - tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0); - - BOARD_CTRL = tempChar; - - __asm__ volatile ("sync\n eieio"); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0] = 0x00900090; - - __asm__ volatile ("sync\n eieio"); - - udelay (100); - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong) (&addr[0]), addr[0], - (ulong) (&addr[2]), addr[2]); - - - if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) { - - flash_info[i].flash_id = - (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160F3T & FLASH_TYPEMASK); - - } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) - && (addr[2] == addr[3]) - && (addr[2] == INTEL_ID_28F160C3T)) { - - flash_info[i].flash_id = - (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160C3T & FLASH_TYPEMASK); - - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFFFFFFFF; - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - addr[0] = 0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j > 30) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - (MAIN_SECT_SIZE * 31) + (j - - 31) * - PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE; - } - } - - /* unlock sectors, if 160C3T */ - - for (j = 0; j < flash_info[i].sector_count; j++) { - tmpaddr = (vu_long *) flash_info[i].start[j]; - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) { - tmpaddr[0] = 0x00600060; - tmpaddr[0] = 0x00D000D0; - tmpaddr[1] = 0x00600060; - tmpaddr[1] = 0x00D000D0; - } - } - - size += flash_info[i].size; - - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_INTEL & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (INTEL_ID_28F160F3T & FLASH_TYPEMASK): - printf ("28F160F3T (16Mbit)\n"); - break; - - case (INTEL_ID_28F160C3T & FLASH_TYPEMASK): - printf ("28F160C3T (16Mbit)\n"); - break; - - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", - sect, (ulong) addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts (); - - addr[0] = 0x00500050; /* clear status register */ - addr[0] = 0x00200020; /* erase setup */ - addr[0] = 0x00D000D0; /* erase confirm */ - - addr[1] = 0x00500050; /* clear status register */ - addr[1] = 0x00200020; /* erase setup */ - addr[1] = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if ((now = get_timer (start)) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0x00B000B0; /* suspend erase */ - addr[0] = 0x00FF00FF; /* to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = 0x00FF00FF; - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong) src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr (); - set_msr (msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp = *src++; - - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *) src; - *datal = *(ulong *) (src + 4); - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr (msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp = *src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> - 24); - } - - *datal = (*datal << 8) | tmp; - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> - 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - - rc = write_data (info, wp, data); - set_msr (msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, ulong * data) -{ - vu_long *addr = (vu_long *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0] = 0x00400040; /* write setup */ - write_via_fpu (addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr[0] = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c deleted file mode 100644 index 1944e36..0000000 --- a/board/cpc45/ide.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ide.h> -#include <ata.h> -#include <asm/io.h> - -#define EIEIO __asm__ volatile ("eieio") -#define SYNC __asm__ volatile ("sync") - -void ide_input_swap_data(int dev, ulong *sect_buf, int words) -{ - uchar i; - volatile uchar *pbuf_even = - (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - volatile uchar *pbuf_odd = - (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - ushort *dbuf = (ushort *) sect_buf; - - while (words--) { - for (i = 0; i < 2; i++) { - *(((uchar *) (dbuf)) + 1) = *pbuf_even; - *(uchar *) dbuf = *pbuf_odd; - dbuf += 1; - } - } -} - -void ide_input_data(int dev, ulong *sect_buf, int words) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (words--) { - *dbuf++ = *pbuf_even; - EIEIO; - SYNC; - *dbuf++ = *pbuf_odd; - EIEIO; - SYNC; - *dbuf++ = *pbuf_even; - EIEIO; - SYNC; - *dbuf++ = *pbuf_odd; - EIEIO; - SYNC; - } -} - -void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (shorts--) { - EIEIO; - *dbuf++ = *pbuf_even; - EIEIO; - *dbuf++ = *pbuf_odd; - } -} - -void ide_output_data(int dev, const ulong *sect_buf, int words) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (words--) { - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - } -} - -void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (shorts--) { - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - } -} - -void ide_led(uchar led, uchar status) -{ - u_char val; - /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ - val = readb(BCSR_BASE + 0x04); - if (status) /* led on */ - val |= B_CTRL_LED0; - else - val &= ~B_CTRL_LED0; - - writeb(val, BCSR_BASE + 0x04); -} diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c deleted file mode 100644 index 23d87f6..0000000 --- a/board/cpc45/pd67290.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - ******************************************************************** - * - * Lots of code copied from: - * - * i82365.c 1.352 - Linux driver for Intel 82365 and compatible - * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. - * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net> - */ - -#include <common.h> - -#ifdef CONFIG_I82365 - -#include <command.h> -#include <pci.h> -#include <pcmcia.h> -#include <asm/io.h> - -#include <pcmcia/ss.h> -#include <pcmcia/i82365.h> -#include <pcmcia/yenta.h> -#include <pcmcia/cirrus.h> - -static struct pci_device_id supported[] = { - {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, - {0, 0} -}; - -#define CYCLE_TIME 120 - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev); -#endif - -typedef struct socket_info_t { - pci_dev_t dev; - u_short bcr; - u_char pci_lat, cb_lat, sub_bus, cache; - u_int cb_phys; - - socket_cap_t cap; - u_short type; - u_int flags; - cirrus_state_t c_state; -} socket_info_t; - -/* These definitions must match the pcic table! */ -typedef enum pcic_id { - IS_PD6710, IS_PD672X, IS_VT83C469 -} pcic_id; - -typedef struct pcic_t { - char *name; -} pcic_t; - -static pcic_t pcic[] = { - {" Cirrus PD6710: "}, - {" Cirrus PD672x: "}, - {" VIA VT83C469: "}, -}; - -static socket_info_t socket; -static socket_state_t state; -static struct pccard_mem_map mem; -static struct pccard_io_map io; - -/*====================================================================*/ - -/* Some PCI shortcuts */ - -static int pci_readb (socket_info_t * s, int r, u_char * v) -{ - return pci_read_config_byte (s->dev, r, v); -} -static int pci_writeb (socket_info_t * s, int r, u_char v) -{ - return pci_write_config_byte (s->dev, r, v); -} -static int pci_readw (socket_info_t * s, int r, u_short * v) -{ - return pci_read_config_word (s->dev, r, v); -} -static int pci_writew (socket_info_t * s, int r, u_short v) -{ - return pci_write_config_word (s->dev, r, v); -} - -/*====================================================================*/ - -#define cb_readb(s) readb((s)->cb_phys + 1) -#define cb_writeb(s, v) writeb(v, (s)->cb_phys) -#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - u_char val; -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - val = cb_readb (s); - - debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); - return val; -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - u_char val; - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - cb_writeb2 (s, data); - - debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); -} - -static void i365_bset (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) | mask); -} - -static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) & ~mask); -} - -#if 0 /* not used */ -static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) -{ - u_char d = i365_get (s, reg); - - i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); -} - -static u_short i365_get_pair (socket_info_t * s, u_short reg) -{ - return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); -} -#endif /* not used */ - -static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) -{ - i365_set (s, reg, data & 0xff); - i365_set (s, reg + 1, data >> 8); -} - -/*====================================================================== - - Code to save and restore global state information for Cirrus - PD67xx controllers, and to set and report global configuration - options. - -======================================================================*/ - -#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) - -static void cirrus_get_state (socket_info_t * s) -{ - int i; - cirrus_state_t *p = &s->c_state; - - p->misc1 = i365_get (s, PD67_MISC_CTL_1); - p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - p->misc2 = i365_get (s, PD67_MISC_CTL_2); - for (i = 0; i < 6; i++) - p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); - -} - -static void cirrus_set_state (socket_info_t * s) -{ - int i; - u_char misc; - cirrus_state_t *p = &s->c_state; - - misc = i365_get (s, PD67_MISC_CTL_2); - i365_set (s, PD67_MISC_CTL_2, p->misc2); - if (misc & PD67_MC2_SUSPEND) - udelay (50000); - misc = i365_get (s, PD67_MISC_CTL_1); - misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); - for (i = 0; i < 6; i++) - i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); -} - -static u_int cirrus_set_opts (socket_info_t * s) -{ - cirrus_state_t *p = &s->c_state; - u_int mask = 0xffff; - char buf[200] = {0}; - - if (has_ring == -1) - has_ring = 1; - flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); - flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); -#if DEBUG - if (p->misc2 & PD67_MC2_IRQ15_RI) - strcat (buf, " [ring]"); - if (p->misc2 & PD67_MC2_DYNAMIC_MODE) - strcat (buf, " [dyn mode]"); - if (p->misc1 & PD67_MC1_INPACK_ENA) - strcat (buf, " [inpack]"); -#endif - - if (p->misc2 & PD67_MC2_IRQ15_RI) - mask &= ~0x8000; - if (has_led > 0) { -#if DEBUG - strcat (buf, " [led]"); -#endif - mask &= ~0x1000; - } - if (has_dma > 0) { -#if DEBUG - strcat (buf, " [dma]"); -#endif - mask &= ~0x0600; - flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); -#if DEBUG - if (p->misc2 & PD67_MC2_FREQ_BYPASS) - strcat (buf, " [freq bypass]"); -#endif - } - - if (setup_time >= 0) - p->timer[0] = p->timer[3] = setup_time; - if (cmd_time > 0) { - p->timer[1] = cmd_time; - p->timer[4] = cmd_time * 2 + 4; - } - if (p->timer[1] == 0) { - p->timer[1] = 6; - p->timer[4] = 16; - if (p->timer[0] == 0) - p->timer[0] = p->timer[3] = 1; - } - if (recov_time >= 0) - p->timer[2] = p->timer[5] = recov_time; - - debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", - buf, - p->timer[0], p->timer[1], p->timer[2], - p->timer[3], p->timer[4], p->timer[5]); - - return mask; -} - -/*====================================================================== - - Routines to handle common CardBus options - -======================================================================*/ - -/* Default settings for PCI command configuration register */ -#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ - PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) - -static void cb_get_state (socket_info_t * s) -{ - pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); - pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); - pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); - pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); - pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); - pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); -} - -static void cb_set_state (socket_info_t * s) -{ - pci_writew (s, PCI_COMMAND, CMD_DFLT); - pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); - pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); - pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); - pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); - pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); - pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); -} - -static void cb_set_opts (socket_info_t * s) -{ -} - -/*====================================================================== - - Power control for Cardbus controllers: used both for 16-bit and - Cardbus cards. - -======================================================================*/ - -static int cb_set_power (socket_info_t * s, socket_state_t * state) -{ - u_int reg = 0; - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - if (state->Vpp != 0) { - if (state->Vpp == 120) { - reg |= I365_VPP1_12V; - puts (" 12V card found: "); - } else if (state->Vpp == state->Vcc) { - reg |= I365_VPP1_5V; - } else { - puts (" power not found: "); - return -1; - } - } - if (state->Vcc != 0) { - reg |= I365_VCC_5V; - if (state->Vcc == 33) { - puts (" 3.3V card found: "); - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else if (state->Vcc == 50) { - puts (" 5V card found: "); - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - puts (" power not found: "); - return -1; - } - } - - if (reg != i365_get (s, I365_POWER)) { - reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); - i365_set (s, I365_POWER, reg); - } - - return 0; -} - -/*====================================================================== - - Generic routines to get and set controller options - -======================================================================*/ - -static void get_bridge_state (socket_info_t * s) -{ - cirrus_get_state (s); - cb_get_state (s); -} - -static void set_bridge_state (socket_info_t * s) -{ - cb_set_state (s); - i365_set (s, I365_GBLCTL, 0x00); - i365_set (s, I365_GENCTL, 0x00); - cirrus_set_state (s); -} - -static void set_bridge_opts (socket_info_t * s) -{ - cirrus_set_opts (s); - cb_set_opts (s); -} - -/*====================================================================*/ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ -#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) - -#define pd67_ext_get(s, r) \ - (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) - -static int i365_get_status (socket_info_t * s, u_int * value) -{ - u_int status; - u_char val; - u_char power, vcc, vpp; - u_int powerstate; - - status = i365_get (s, I365_IDENT); - status = i365_get (s, I365_STATUS); - *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; - if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { - *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; - } else { - *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; - *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; - } - *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; - *value |= (status & I365_CS_READY) ? SS_READY : 0; - *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; - - /* Check for Cirrus CL-PD67xx chips */ - i365_set (s, PD67_CHIP_INFO, 0); - val = i365_get (s, PD67_CHIP_INFO); - s->type = -1; - if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { - val = i365_get (s, PD67_CHIP_INFO); - if ((val & PD67_INFO_CHIP_ID) == 0) { - s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; - i365_set (s, PD67_EXT_INDEX, 0xe5); - if (i365_get (s, PD67_EXT_INDEX) != 0xe5) - s->type = IS_VT83C469; - } - } else { - printf ("no Cirrus Chip found\n"); - *value = 0; - return -1; - } - - power = i365_get (s, I365_POWER); - state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; - state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; - vcc = power & I365_VCC_MASK; - vpp = power & I365_VPP1_MASK; - state.Vcc = state.Vpp = 0; - if((vcc== 0) || (vpp == 0)) { - /* - * On the Cirrus we get the info which card voltage - * we have in EXTERN DATA and write it to MISC_CTL1 - */ - powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); - if (powerstate & PD67_EXD_VS1(0)) { - /* 5V Card */ - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - /* 3.3V Card */ - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } - i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); - power = i365_get (s, I365_POWER); - } - if (power & I365_VCC_5V) { - state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; - } - - if (power == I365_VPP1_12V) - state.Vpp = 120; - - /* IO card, RESET flags, IO interrupt */ - power = i365_get (s, I365_INTCTL); - state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; - if (power & I365_PC_IOCARD) - state.flags |= SS_IOCARD; - state.io_irq = power & I365_IRQ_MASK; - - /* Card status change mask */ - power = i365_get (s, I365_CSCINT); - state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; - if (state.flags & SS_IOCARD) - state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; - else { - state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; - state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; - state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; - } - debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " - "io_irq %d, csc_mask %#2.2x\n", state.flags, - state.Vcc, state.Vpp, state.io_irq, state.csc_mask); - - return 0; -} /* i365_get_status */ - -static int i365_set_socket (socket_info_t * s, socket_state_t * state) -{ - u_char reg; - - set_bridge_state (s); - - /* IO card, RESET flag */ - reg = 0; - reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; - reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; - i365_set (s, I365_INTCTL, reg); - - cb_set_power (s, state); - -#if 0 - /* Card status change interrupt mask */ - reg = s->cs_irq << 4; - if (state->csc_mask & SS_DETECT) - reg |= I365_CSC_DETECT; - if (state->flags & SS_IOCARD) { - if (state->csc_mask & SS_STSCHG) - reg |= I365_CSC_STSCHG; - } else { - if (state->csc_mask & SS_BATDEAD) - reg |= I365_CSC_BVD1; - if (state->csc_mask & SS_BATWARN) - reg |= I365_CSC_BVD2; - if (state->csc_mask & SS_READY) - reg |= I365_CSC_READY; - } - i365_set (s, I365_CSCINT, reg); - i365_get (s, I365_CSC); -#endif /* 0 */ - - return 0; -} /* i365_set_socket */ - -/*====================================================================*/ - -static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) -{ - u_short base, i; - u_char map; - - debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", - mem->map, mem->flags, mem->speed, - mem->sys_start, mem->sys_stop, mem->card_start); - - map = mem->map; - if ((map > 4) || - (mem->card_start > 0x3ffffff) || - (mem->sys_start > mem->sys_stop) || - (mem->speed > 1000)) { - return -1; - } - - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); - - /* Take care of high byte, for PCI controllers */ - i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); - - base = I365_MEM (map); - i = (mem->sys_start >> 12) & 0x0fff; - if (mem->flags & MAP_16BIT) - i |= I365_MEM_16BIT; - if (mem->flags & MAP_0WS) - i |= I365_MEM_0WS; - i365_set_pair (s, base + I365_W_START, i); - - i = (mem->sys_stop >> 12) & 0x0fff; - switch (mem->speed / CYCLE_TIME) { - case 0: - break; - case 1: - i |= I365_MEM_WS0; - break; - case 2: - i |= I365_MEM_WS1; - break; - default: - i |= I365_MEM_WS1 | I365_MEM_WS0; - break; - } - i365_set_pair (s, base + I365_W_STOP, i); - - i = 0; - if (mem->flags & MAP_WRPROT) - i |= I365_MEM_WRPROT; - if (mem->flags & MAP_ATTRIB) - i |= I365_MEM_REG; - i365_set_pair (s, base + I365_W_OFF, i); - - /* set System Memory map Upper Adress */ - i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); - i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); - - /* Turn on the window if necessary */ - if (mem->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); - return 0; -} /* i365_set_mem_map */ - -static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) -{ - u_char map, ioctl; - - map = io->map; - /* comment out: comparison is always false due to limited range of data type */ - if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ - (io->stop < io->start)) - return -1; - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); - i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); - i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); - ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); - if (io->speed) - ioctl |= I365_IOCTL_WAIT (map); - if (io->flags & MAP_0WS) - ioctl |= I365_IOCTL_0WS (map); - if (io->flags & MAP_16BIT) - ioctl |= I365_IOCTL_16BIT (map); - if (io->flags & MAP_AUTOSZ) - ioctl |= I365_IOCTL_IOCS16 (map); - i365_set (s, I365_IOCTL, ioctl); - /* Turn on the window if necessary */ - if (io->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); - return 0; -} /* i365_set_io_map */ - -/*====================================================================*/ - -/* - * PCI_ADDR = (HOST_ADDR - 0xfe000000) - * see MPC 8245 Users Manual Adress Map B - */ -#define HOST_TO_PCI(addr) ((addr) - 0xfe000000) -#define PCI_TO_HOST(addr) ((addr) + 0xfe000000) - -static int i82365_init (void) -{ - u_int val; - int i; - - if ((socket.dev = pci_find_devices (supported, 0)) < 0) { - /* Controller not found */ - printf ("No PD67290 device found !!\n"); - return 1; - } - debug ("i82365 Device Found!\n"); - - socket.cb_phys = PCMCIA_IO_BASE; - - /* set base address */ - pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0, - HOST_TO_PCI(socket.cb_phys)); - - /* enable mapped memory and IO addresses */ - pci_write_config_dword (socket.dev, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | PCI_COMMAND_WAIT); - - get_bridge_state (&socket); - set_bridge_opts (&socket); - - i = i365_get_status (&socket, &val); - - if (i > -1) { - puts (pcic[socket.type].name); - } else { - printf ("i82365: Controller not found.\n"); - return 1; - } - if((val & SS_DETECT) != SS_DETECT){ - puts ("No card\n"); - return 1; - } - - state.flags |= SS_OUTPUT_ENA; - - i365_set_socket (&socket, &state); - - for (i = 500; i; i--) { - if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) - break; - udelay (1000); - } - - if (i == 0) { - /* PC Card not ready for data transfer */ - puts ("i82365 PC Card not ready for data transfer\n"); - return 1; - } - debug (" PC Card ready for data transfer: "); - - mem.map = 0; - mem.flags = MAP_ATTRIB | MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - - mem.map = 1; - mem.flags = MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - -#ifdef DEBUG - i82365_dump_regions (socket.dev); -#endif - - return 0; -} - -static void i82365_exit (void) -{ - io.map = 0; - io.flags = 0; - io.speed = 0; - io.start = 0; - io.stop = 0x1; - - i365_set_io_map (&socket, &io); - - mem.map = 0; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - - mem.map = 1; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - - state.Vcc = state.Vpp = 0; - - i365_set_socket (&socket, &state); -} - -int pcmcia_on (void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - rc = i82365_init(); - if (rc) - goto exit; - - rc = check_ide_device(0); - if (rc == 0) - goto exit; - - i82365_exit(); - -exit: - return rc; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_off (void) -{ - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - i82365_exit(); - - return 0; -} -#endif - -/*====================================================================== - - Debug stuff - -======================================================================*/ - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev) -{ - u_int tmp[2]; - u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); - - pci_read_config_dword (dev, 0x00, tmp + 0); - pci_read_config_dword (dev, 0x80, tmp + 1); - - printf ("PCI CONF: %08X ... %08X\n", - tmp[0], tmp[1]); - printf ("PCI MEM: ... %08X ... %08X\n", - mem[0x8 / 4], mem[0x800 / 4]); - printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", - cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], - cis[0x40], cis[0x42], cis[0x44], cis[0x48]); - printf ("CIS CONF: %02X %02X %02X ...\n", - cis[0x200], cis[0x202], cis[0x204]); - printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", - ide[0], ide[1], ide[2], ide[3], - ide[4], ide[5], ide[6], ide[7]); -} -#endif /* DEBUG */ - -#endif /* CONFIG_I82365 */ diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c deleted file mode 100644 index 06fb8d6..0000000 --- a/board/cpc45/plx9030.c +++ /dev/null @@ -1,156 +0,0 @@ -/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */ -/* - * (C) Copyright 2002-2003 - * Josef Wagner, MicroSys GmbH, wagner@microsys.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * Date Modification by - * ------- ---------------------------------------------- --- - * 30sep02 converted from VxWorks to LINUX wa -*/ - - -/* -DESCRIPTION - -This is the configuration module for the PLX9030 PCI to Local Bus Bridge. -It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local -registers (CS3) on CPC45. -*/ - -/* includes */ - -#include <common.h> -#include <malloc.h> -#include <net.h> -#include <asm/io.h> -#include <pci.h> - -/* imports */ - - -/* defines */ -#define PLX9030_VENDOR_ID 0x10B5 -#define PLX9030_DEVICE_ID 0x9030 - -#undef PLX_DEBUG - -/* PLX9030 register offsets */ -#define P9030_LAS0RR 0x00 -#define P9030_LAS1RR 0x04 -#define P9030_LAS2RR 0x08 -#define P9030_LAS3RR 0x0c -#define P9030_EROMRR 0x10 -#define P9030_LAS0BA 0x14 -#define P9030_LAS1BA 0x18 -#define P9030_LAS2BA 0x1c -#define P9030_LAS3BA 0x20 -#define P9030_EROMBA 0x24 -#define P9030_LAS0BRD 0x28 -#define P9030_LAS1BRD 0x2c -#define P9030_LAS2BRD 0x30 -#define P9030_LAS3BRD 0x34 -#define P9030_EROMBRD 0x38 -#define P9030_CS0BASE 0x3C -#define P9030_CS1BASE 0x40 -#define P9030_CS2BASE 0x44 -#define P9030_CS3BASE 0x48 -#define P9030_INTCSR 0x4c -#define P9030_CNTRL 0x50 -#define P9030_GPIOC 0x54 - -/* typedefs */ - - -/* locals */ - -static struct pci_device_id supported[] = { - { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID }, - { } -}; - -/* forward declarations */ -void sysOutLong(ulong address, ulong value); - - -/*************************************************************************** -* -* Plx9030Init - init CS0..CS3 for CPC45 -* -* -* RETURNS: N/A -*/ - -void Plx9030Init (void) -{ - pci_dev_t devno; - ulong membaseCsr; /* base address of device memory space */ - int idx = 0; /* general index */ - - - /* find plx9030 device */ - - if ((devno = pci_find_devices(supported, idx++)) < 0) - { - printf("No PLX9030 device found !!\n"); - return; - } - - -#ifdef PLX_DEBUG - printf("PLX 9030 device found ! devno = 0x%x\n",devno); -#endif - - membaseCsr = PCI_PLX9030_MEMADDR; - - /* set base address */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr); - - /* enable mapped memory and IO addresses */ - pci_write_config_dword(devno, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - - - /* configure GBIOC */ - sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */ - - /* configure CS0 (SRAM) */ - sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */ - sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */ - /* remap CS0 (SRAM) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE); - - /* configure CS1 (ST16552 / CHAN A) */ - sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */ - /* remap CS1 (ST16552 / CHAN A) */ - /* remap CS1 (ST16552 / CHAN A) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE); - - /* configure CS2 (ST16552 / CHAN B) */ - sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */ - /* remap CS2 (ST16552 / CHAN B) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE); - - /* configure CS3 (BCSR) */ - sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */ - sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */ - /* remap CS3 (DISPLAY and BCSR) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE); -} - -void sysOutLong(ulong address, ulong value) -{ - *(ulong*)address = cpu_to_le32(value); -} diff --git a/board/cu824/Kconfig b/board/cu824/Kconfig deleted file mode 100644 index 7927b05..0000000 --- a/board/cu824/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CU824 - -config SYS_BOARD - default "cu824" - -config SYS_CONFIG_NAME - default "CU824" - -endif diff --git a/board/cu824/MAINTAINERS b/board/cu824/MAINTAINERS deleted file mode 100644 index b1b7190..0000000 --- a/board/cu824/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CU824 BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/cu824/ -F: include/configs/CU824.h -F: configs/CU824_defconfig diff --git a/board/cu824/Makefile b/board/cu824/Makefile deleted file mode 100644 index e7bd7ca..0000000 --- a/board/cu824/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cu824.o flash.o diff --git a/board/cu824/README b/board/cu824/README deleted file mode 100644 index cc0d207..0000000 --- a/board/cu824/README +++ /dev/null @@ -1,453 +0,0 @@ -ppcboot for a CU824 board ---------------------------- - -CU824 has two banks of flash 8MB each. In board's notation, bank 0 is -the one at the address of 0xFF800000 and bank 1 is the one at the -address of 0xFF000000. On power-up the processor jumps to the address -of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus, -U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is not embedded in the U-Boot code -and is located in flash separately from U-Boot, at the address of -0xFF008000. - - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>he -go - start application at address 'addr' -run - run commands in an environment variable -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -rarpboot- boot image via network using RARP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -loads - load S-Record file over serial line -loadb - load binary file over serial line (kermit mode) -md - memory display -mm - memory modify (auto-incrementing) -nm - memory modify (constant address) -mw - memory write (fill) -cp - memory copy -cmp - memory compare -crc32 - checksum calculation -base - print or set address offset -printenv- print environment variables -setenv - set environment variables -saveenv - save environment variables to persistent storage -protect - enable or disable FLASH write protection -erase - erase FLASH memory -flinfo - print FLASH memory information -bdinfo - print Board Info structure -iminfo - print header information for application image -coninfo - print console devices and informations -loop - infinite loop on address range -mtest - simple RAM test -icache - enable or disable instruction cache -dcache - enable or disable data cache -reset - Perform RESET of the CPU -echo - echo args to console -version - print monitor version -help - print online help -? - alias for 'help' -=> - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - -x.x.x Erase Operation - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=>md ff000000 -ff000000: 27051956 70706362 6f6f7420 302e382e '..Vppcboot 0.8. -ff000010: 3320284d 61792031 31203230 3031202d 3 (May 11 2001 - -ff000020: 2031343a 35373a30 33290000 00000000 14:57:03)...... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -=>erase ff000000 ff007fff -Erase Flash from 0xff000000 to 0xff007fff - done -Erased 1 sectors -=>md ff000000 -ff000000: ffffffff ffffffff ffffffff ffffffff ................ -ff000010: ffffffff ffffffff ffffffff ffffffff ................ -ff000020: ffffffff ffffffff ffffffff ffffffff ................ -ff000030: ffffffff ffffffff ffffffff ffffffff ................ -ff000040: ffffffff ffffffff ffffffff ffffffff ................ -ff000050: ffffffff ffffffff ffffffff ffffffff ................ -ff000060: ffffffff ffffffff ffffffff ffffffff ................ -ff000070: ffffffff ffffffff ffffffff ffffffff ................ -ff000080: ffffffff ffffffff ffffffff ffffffff ................ -ff000090: ffffffff ffffffff ffffffff ffffffff ................ -ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ -=> - -x.x.x Information - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=> -=>flinfo - -Bank # 1: Intel: 28F160F3B (16Mbit) - Size: 8 MB in 39 Sectors - Sector Start Addresses: - FF000000 FF008000 (RO) FF010000 FF018000 FF020000 - FF028000 FF030000 FF038000 FF040000 FF080000 - FF0C0000 FF100000 FF140000 FF180000 FF1C0000 - FF200000 FF240000 FF280000 FF2C0000 FF300000 - FF340000 FF380000 FF3C0000 FF400000 FF440000 - FF480000 FF4C0000 FF500000 FF540000 FF580000 - FF5C0000 FF600000 FF640000 FF680000 FF6C0000 - FF700000 FF740000 FF780000 FF7C0000 - -Bank # 2: Intel: 28F160F3B (16Mbit) - Size: 8 MB in 39 Sectors - Sector Start Addresses: - FF800000 FF808000 FF810000 FF818000 FF820000 - FF828000 FF830000 FF838000 FF840000 FF880000 - FF8C0000 FF900000 FF940000 FF980000 FF9C0000 - FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 - FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 - FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 - FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 - FFF00000 (RO) FFF40000 FFF80000 FFFC0000 -=> - -x.x.x Flash Programming - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=> -=>cp 0 ff000000 20 -Copy to Flash... done -=>md 0 -00000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ -00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ -00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. -00000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ -00000040: 00000000 00000000 00000000 00000000 ................ -00000050: 00000000 00000000 00000000 00000000 ................ -00000060: 00000000 00000000 00000000 00000000 ................ -00000070: 00000000 00000000 00000000 00000000 ................ -00000080: 00000000 00000000 00000000 00000000 ................ -00000090: 00000000 00000000 00000000 00000000 ................ -000000a0: 00000000 00000000 00000000 00000000 ................ -000000b0: 00000000 00000000 00000000 00000000 ................ -000000c0: 00000000 00000000 00000000 00000000 ................ -000000d0: 00000000 00000000 00000000 00000000 ................ -000000e0: 00000000 00000000 00000000 00000000 ................ -000000f0: 00000000 00000000 00000000 00000000 ................ -=>md ff000000 -ff000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ -ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ -ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. -ff000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: ffffffff ffffffff ffffffff ffffffff ................ -ff000090: ffffffff ffffffff ffffffff ffffffff ................ -ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ -=> - -x.x.x Storage of environment variables in flash - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>printenv -bootargs= -bootcmd=bootm FE020000 -bootdelay=5 -baudrate=9600 -ipaddr=192.168.4.2 -serverip=192.168.4.1 -ethaddr=00:40:42:01:00:a0 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 167/32764 bytes -=>setenv myvar 1234 -=>save_env -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=>reset - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>printenv -bootargs= -bootcmd=bootm FE020000 -bootdelay=5 -baudrate=9600 -ipaddr=192.168.4.2 -serverip=192.168.4.1 -ethaddr=00:40:42:01:00:a0 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 178/32764 bytes -=> - -x.x Image Download and run over serial port - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=>mw 40000 0 10000 -=>md 40000 -00040000: 00000000 00000000 00000000 00000000 ................ -00040010: 00000000 00000000 00000000 00000000 ................ -00040020: 00000000 00000000 00000000 00000000 ................ -00040030: 00000000 00000000 00000000 00000000 ................ -00040040: 00000000 00000000 00000000 00000000 ................ -00040050: 00000000 00000000 00000000 00000000 ................ -00040060: 00000000 00000000 00000000 00000000 ................ -00040070: 00000000 00000000 00000000 00000000 ................ -00040080: 00000000 00000000 00000000 00000000 ................ -00040090: 00000000 00000000 00000000 00000000 ................ -000400a0: 00000000 00000000 00000000 00000000 ................ -000400b0: 00000000 00000000 00000000 00000000 ................ -000400c0: 00000000 00000000 00000000 00000000 ................ -000400d0: 00000000 00000000 00000000 00000000 ................ -000400e0: 00000000 00000000 00000000 00000000 ................ -000400f0: 00000000 00000000 00000000 00000000 ................ -=>loads -## Ready for S-Record download ... - -(Back at xpert.denx.de) -[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0 -[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c -Connecting to /dev/ttyS0, speed 9600. -The escape character is Ctrl-\ (ASCII 28, FS) -Type the escape character followed by C to get back, -or followed by ? to see other options. -md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... -000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... -000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 -000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=>go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "<NULL>" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> - -x.x Image download and run over ethernet interface - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=>mw 40000 0 10000 -=>md 40000 -00040000: 00000000 00000000 00000000 00000000 ................ -00040010: 00000000 00000000 00000000 00000000 ................ -00040020: 00000000 00000000 00000000 00000000 ................ -00040030: 00000000 00000000 00000000 00000000 ................ -00040040: 00000000 00000000 00000000 00000000 ................ -00040050: 00000000 00000000 00000000 00000000 ................ -00040060: 00000000 00000000 00000000 00000000 ................ -00040070: 00000000 00000000 00000000 00000000 ................ -00040080: 00000000 00000000 00000000 00000000 ................ -00040090: 00000000 00000000 00000000 00000000 ................ -000400a0: 00000000 00000000 00000000 00000000 ................ -000400b0: 00000000 00000000 00000000 00000000 ................ -000400c0: 00000000 00000000 00000000 00000000 ................ -000400d0: 00000000 00000000 00000000 00000000 ................ -000400e0: 00000000 00000000 00000000 00000000 ................ -000400f0: 00000000 00000000 00000000 00000000 ................ -=>tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 192.168.4.1; our IP address is 192.168.4.2 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65912 (10178 hex) -=>md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... -000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... -000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 -000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=>go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "<NULL>" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c deleted file mode 100644 index 6b23c53..0000000 --- a/board/cu824/cu824.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2001-2006 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <pci.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define BOARD_REV_REG 0xFE80002B - -int checkboard (void) -{ - char revision = *(volatile char *)(BOARD_REV_REG); - char buf[32]; - - puts ("Board: CU824 "); - printf("Revision %d ", revision); - printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); - - return 0; -} - -phys_size_t initdram(int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/cu824/flash.c b/board/cu824/flash.c deleted file mode 100644 index 3a6d954..0000000 --- a/board/cu824/flash.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT_SIZE 0x8000 - -#define BOARD_CTRL_REG 0xFE800013 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t *info, ulong dest, ulong *data); -static void write_via_fpu(vu_long *addr, ulong *data); -static __inline__ unsigned long get_msr(void); -static __inline__ void set_msr(unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - int i, j; - ulong size = 0; - volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG); - - DEBUGF("Write protect was: 0x%02X\n", *bcr); - *bcr &= 0x1; /* FWPT must be 0 */ - *bcr |= 0x6; /* FWP0 = FWP1 = 1 */ - DEBUGF("Write protect is: 0x%02X\n", *bcr); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0] = 0x00900090; - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong)(&addr[0]), addr[0], - (ulong)(&addr[2]), addr[2]); - - if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B)) - { - flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160F3B & FLASH_TYPEMASK); - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFFFFFFFF; - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - addr[0] = 0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 7) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - j * PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + - i * FLASH_BANK_SIZE + - (j - 7)*MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#else - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_INTEL & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (INTEL_ID_28F160F3B & FLASH_TYPEMASK): - printf ("28F160F3B (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", - sect, (ulong)addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts(); - - addr[0] = 0x00500050; /* clear status register */ - addr[0] = 0x00200020; /* erase setup */ - addr[0] = 0x00D000D0; /* erase confirm */ - - addr[1] = 0x00500050; /* clear status register */ - addr[1] = 0x00200020; /* erase setup */ - addr[1] = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080) ) { - if ((now=get_timer(start)) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0x00B000B0; /* suspend erase */ - addr[0] = 0x00FF00FF; /* to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = 0x00FF00FF; - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong)src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr(); - set_msr(msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *)cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - set_msr(msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *)src; - *datal = *(ulong *)(src + 4); - if ((rc = write_data(info, wp, data)) != 0) { - set_msr(msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr(msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *)cp); - } - - rc = write_data(info, wp, data); - set_msr(msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong *data) -{ - vu_long *addr = (vu_long *)dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1]) ) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0] = 0x00400040; /* write setup */ - write_via_fpu(addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080) ) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr[0] = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu(vu_long *addr, ulong *data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); -} -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} diff --git a/board/eXalion/Kconfig b/board/eXalion/Kconfig deleted file mode 100644 index a22f58a..0000000 --- a/board/eXalion/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_EXALION - -config SYS_BOARD - default "eXalion" - -config SYS_CONFIG_NAME - default "eXalion" - -endif diff --git a/board/eXalion/MAINTAINERS b/board/eXalion/MAINTAINERS deleted file mode 100644 index 0ea74ca..0000000 --- a/board/eXalion/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EXALION BOARD -M: Torsten Demke <torsten.demke@fci.com> -S: Maintained -F: board/eXalion/ -F: include/configs/eXalion.h -F: configs/eXalion_defconfig diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile deleted file mode 100644 index 9192e28..0000000 --- a/board/eXalion/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = eXalion.o diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c deleted file mode 100644 index 304ff21..0000000 --- a/board/eXalion/eXalion.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> -#include <ide.h> -#include <netdev.h> -#include <timestamp.h> -#include "piix_pci.h" -#include "eXalion.h" - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - printf ("Board: eXalion MPC824x - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return (0); -} - -phys_size_t initdram (int board_type) -{ - int i, cnt; - volatile uchar *base = CONFIG_SYS_SDRAM_BASE; - volatile ulong *addr; - ulong save[32]; - ulong val, ret = 0; - - for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; - cnt >>= 1) { - addr = (volatile ulong *) base + cnt; - save[i++] = *addr; - *addr = ~cnt; - } - - addr = (volatile ulong *) base; - save[i] = *addr; - *addr = 0; - - if (*addr != 0) { - *addr = save[i]; - goto Done; - } - - for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - val = *addr; - *addr = save[--i]; - if (val != ~cnt) { - ulong new_bank0_end = cnt * sizeof (long) - 1; - ulong mear1 = mpc824x_mpc107_getreg (MEAR1); - ulong emear1 = mpc824x_mpc107_getreg (EMEAR1); - - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> - MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> - MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - ret = cnt * sizeof (long); - goto Done; - } - } - - ret = CONFIG_SYS_MAX_RAM_SIZE; - Done: - return ret; -} - -int misc_init_r (void) -{ - pci_dev_t bdf; - u32 val32; - u8 val8; - - puts ("ISA: "); - bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0); - if (bdf == -1) { - puts ("Unable to find PIIX4 ISA bridge !\n"); - hang (); - } - - /* set device for normal ISA instead EIO */ - pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32); - val32 |= 0x00000001; - pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32); - printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf), - PCI_DEV (bdf), PCI_FUNC (bdf)); - - puts ("ISA: "); - bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0); - if (bdf == -1) { - puts ("Unable to find PIIX4 IDE controller !\n"); - hang (); - } - - /* Init BMIBA register */ - /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */ - /* val32 |= 0x1000; */ - /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */ - - /* Enable BUS master and IO access */ - val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO; - pci_write_config_dword (bdf, PCI_COMMAND, val32); - - /* Set latency */ - pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8); - val8 = 0x40; - pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8); - - /* Enable Primary ATA/IDE */ - pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32); - /* val32 = 0xa307a307; */ - val32 = 0x00008000; - pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32); - - - printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf), - PCI_DEV (bdf), PCI_FUNC (bdf)); - - /* Try to get FAT working... */ - /* fat_register_read(ide_read); */ - - - return (0); -} - -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line; - - switch (PCI_DEV (dev)) { - case 16: - line = PCI_INT_A; - break; - case 17: - line = PCI_INT_B; - break; - case 18: - line = PCI_INT_C; - break; - case 19: - line = PCI_INT_D; - break; -#if defined (CONFIG_MPC8245) - case 20: - line = PCI_INT_A; - break; - case 21: - line = PCI_INT_B; - break; - case 22: - line = PCI_INT_NA; - break; -#endif - default: - line = PCI_INT_A; - break; - } - pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line); -} - - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -#if defined (CONFIG_MPC8240) -static struct pci_config_table pci_eXalion_config_table[] = { - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 PCI to ISA bridge */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 IDE controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - {} -}; -#elif defined (CONFIG_MPC8245) -static struct pci_config_table pci_eXalion_config_table[] = { - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, - pci_cfgfunc_config_device, {PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Broadcom BCM5690 Gigabit switch */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, - pci_cfgfunc_config_device, {PCI_ENET2_IOADDR, - PCI_ENET2_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Broadcom BCM5690 Gigabit switch */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00, - pci_cfgfunc_config_device, {PCI_ENET3_IOADDR, - PCI_ENET3_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 PCI to ISA bridge */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 IDE controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - {} -}; -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#endif /* #ifndef CONFIG_PCI_PNP */ - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_eXalion_config_table, - fixup_irq:pci_eXalion_fixup_irq, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h deleted file mode 100644 index 7804f4f..0000000 --- a/board/eXalion/eXalion.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * James Dougherty (jfd@broadcom.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __EXALION_H -#define __EXALION_H - -/* IRQ settings */ -#define PCI_INT_NA (0xff) /* PCI Intr. not used */ -#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */ -#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */ -#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */ -#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */ -#if defined (CPU_MPC8245) -#define LN_1_INT PCI_INT_B /* ethernet interrupt level */ -#define LN_2_INT PCI_INT_C /* ethernet interrupt level */ -#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */ -#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */ -#elif defined (CPU_MPC8240) -#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */ -#define LN_INT PCI_INT_C /* ethernet interrupt level */ -#endif - -#ifndef __ASSEMBLY__ -#endif /* !__ASSEMBLY__ */ - -#endif /* __EXALION_H */ diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h deleted file mode 100644 index 21c636f..0000000 --- a/board/eXalion/piix_pci.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _PIIX4_PCI_H -#define _PIIX4_PCI_H - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> - -#define PIIX4_VENDOR_ID 0x8086 -#define PIIX4_ISA_DEV_ID 0x7110 -#define PIIX4_IDE_DEV_ID 0x7111 - -/* Function 0 ISA Bridge */ -#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ -#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ -#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ -#define PCI_CFG_PIIX4_SERIRQ 0x64 -#define PCI_CFG_PIIX4_TOM 0x69 -#define PCI_CFG_PIIX4_MSTAT 0x6A -#define PCI_CFG_PIIX4_MBDMA 0x76 -#define PCI_CFG_PIIX4_APICBS 0x80 -#define PCI_CFG_PIIX4_DLC 0x82 -#define PCI_CFG_PIIX4_PDMACFG 0x90 -#define PCI_CFG_PIIX4_DDMABS 0x92 -#define PCI_CFG_PIIX4_GENCFG 0xB0 -#define PCI_CFG_PIIX4_RTCCFG 0xCB - -/* IO Addresses */ -#define PIIX4_ISA_DMA1_CH0BA 0x00 -#define PIIX4_ISA_DMA1_CH0CA 0x01 -#define PIIX4_ISA_DMA1_CH1BA 0x02 -#define PIIX4_ISA_DMA1_CH1CA 0x03 -#define PIIX4_ISA_DMA1_CH2BA 0x04 -#define PIIX4_ISA_DMA1_CH2CA 0x05 -#define PIIX4_ISA_DMA1_CH3BA 0x06 -#define PIIX4_ISA_DMA1_CH3CA 0x07 -#define PIIX4_ISA_DMA1_CMDST 0x08 -#define PIIX4_ISA_DMA1_REQ 0x09 -#define PIIX4_ISA_DMA1_WSBM 0x0A -#define PIIX4_ISA_DMA1_CH_MOD 0x0B -#define PIIX4_ISA_DMA1_CLR_PT 0x0C -#define PIIX4_ISA_DMA1_M_CLR 0x0D -#define PIIX4_ISA_DMA1_CLR_M 0x0E -#define PIIX4_ISA_DMA1_RWAMB 0x0F - -#define PIIX4_ISA_DMA2_CH0BA 0xC0 -#define PIIX4_ISA_DMA2_CH0CA 0xC1 -#define PIIX4_ISA_DMA2_CH1BA 0xC2 -#define PIIX4_ISA_DMA2_CH1CA 0xC3 -#define PIIX4_ISA_DMA2_CH2BA 0xC4 -#define PIIX4_ISA_DMA2_CH2CA 0xC5 -#define PIIX4_ISA_DMA2_CH3BA 0xC6 -#define PIIX4_ISA_DMA2_CH3CA 0xC7 -#define PIIX4_ISA_DMA2_CMDST 0xD0 -#define PIIX4_ISA_DMA2_REQ 0xD2 -#define PIIX4_ISA_DMA2_WSBM 0xD4 -#define PIIX4_ISA_DMA2_CH_MOD 0xD6 -#define PIIX4_ISA_DMA2_CLR_PT 0xD8 -#define PIIX4_ISA_DMA2_M_CLR 0xDA -#define PIIX4_ISA_DMA2_CLR_M 0xDC -#define PIIX4_ISA_DMA2_RWAMB 0xDE - -#define PIIX4_ISA_INT1_ICW1 0x20 -#define PIIX4_ISA_INT1_OCW2 0x20 -#define PIIX4_ISA_INT1_OCW3 0x20 -#define PIIX4_ISA_INT1_ICW2 0x21 -#define PIIX4_ISA_INT1_ICW3 0x21 -#define PIIX4_ISA_INT1_ICW4 0x21 -#define PIIX4_ISA_INT1_OCW1 0x21 - -#define PIIX4_ISA_INT1_ELCR 0x4D0 - -#define PIIX4_ISA_INT2_ICW1 0xA0 -#define PIIX4_ISA_INT2_OCW2 0xA0 -#define PIIX4_ISA_INT2_OCW3 0xA0 -#define PIIX4_ISA_INT2_ICW2 0xA1 -#define PIIX4_ISA_INT2_ICW3 0xA1 -#define PIIX4_ISA_INT2_ICW4 0xA1 -#define PIIX4_ISA_INT2_OCW1 0xA1 -#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ - -#define PIIX4_ISA_INT2_ELCR 0x4D1 - -#define PIIX4_ISA_TMR0_CNT_ST 0x40 -#define PIIX4_ISA_TMR1_CNT_ST 0x41 -#define PIIX4_ISA_TMR2_CNT_ST 0x42 -#define PIIX4_ISA_TMR_TCW 0x43 - -#define PIIX4_ISA_RST_XBUS 0x60 - -#define PIIX4_ISA_NMI_CNT_ST 0x61 -#define PIIX4_ISA_NMI_ENABLE 0x70 - -#define PIIX4_ISA_RTC_INDEX 0x70 -#define PIIX4_ISA_RTC_DATA 0x71 -#define PIIX4_ISA_RTCEXT_IND 0x70 -#define PIIX4_ISA_RTCEXT_DATA 0x71 - -#define PIIX4_ISA_DMA1_CH2LPG 0x81 -#define PIIX4_ISA_DMA1_CH3LPG 0x82 -#define PIIX4_ISA_DMA1_CH1LPG 0x83 -#define PIIX4_ISA_DMA1_CH0LPG 0x87 -#define PIIX4_ISA_DMA2_CH2LPG 0x89 -#define PIIX4_ISA_DMA2_CH3LPG 0x8A -#define PIIX4_ISA_DMA2_CH1LPG 0x8B -#define PIIX4_ISA_DMA2_LPGRFR 0x8F - -#define PIIX4_ISA_PORT_92 0x92 - -#define PIIX4_ISA_APM_CONTRL 0xB2 -#define PIIX4_ISA_APM_STATUS 0xB3 - -#define PIIX4_ISA_COCPU_ERROR 0xF0 - -/* Function 1 IDE Controller */ -#define PCI_CFG_PIIX4_BMIBA 0x20 -#define PCI_CFG_PIIX4_IDETIM 0x40 -#define PCI_CFG_PIIX4_SIDETIM 0x44 -#define PCI_CFG_PIIX4_UDMACTL 0x48 -#define PCI_CFG_PIIX4_UDMATIM 0x4A - -/* Function 2 USB Controller */ -#define PCI_CFG_PIIX4_SBRNUM 0x60 -#define PCI_CFG_PIIX4_LEGSUP 0xC0 - -/* Function 3 Power Management */ -#define PCI_CFG_PIIX4_PMAB 0x40 -#define PCI_CFG_PIIX4_CNTA 0x44 -#define PCI_CFG_PIIX4_CNTB 0x48 -#define PCI_CFG_PIIX4_GPICTL 0x4C -#define PCI_CFG_PIIX4_DEVRESD 0x50 -#define PCI_CFG_PIIX4_DEVACTA 0x54 -#define PCI_CFG_PIIX4_DEVACTB 0x58 -#define PCI_CFG_PIIX4_DEVRESA 0x5C -#define PCI_CFG_PIIX4_DEVRESB 0x60 -#define PCI_CFG_PIIX4_DEVRESC 0x64 -#define PCI_CFG_PIIX4_DEVRESE 0x68 -#define PCI_CFG_PIIX4_DEVRESF 0x6C -#define PCI_CFG_PIIX4_DEVRESG 0x70 -#define PCI_CFG_PIIX4_DEVRESH 0x74 -#define PCI_CFG_PIIX4_DEVRESI 0x78 -#define PCI_CFG_PIIX4_PMMISC 0x80 -#define PCI_CFG_PIIX4_SMBBA 0x90 - - -#endif /* _PIIX4_PCI_H */ diff --git a/board/musenki/Kconfig b/board/musenki/Kconfig deleted file mode 100644 index 26b680f..0000000 --- a/board/musenki/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MUSENKI - -config SYS_BOARD - default "musenki" - -config SYS_CONFIG_NAME - default "MUSENKI" - -endif diff --git a/board/musenki/MAINTAINERS b/board/musenki/MAINTAINERS deleted file mode 100644 index 4196c80..0000000 --- a/board/musenki/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MUSENKI BOARD -#M: Jim Thompson <jim@musenki.com> -S: Orphan (since 2014-04) -F: board/musenki/ -F: include/configs/MUSENKI.h -F: configs/MUSENKI_defconfig diff --git a/board/musenki/Makefile b/board/musenki/Makefile deleted file mode 100644 index d2b79ff..0000000 --- a/board/musenki/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = musenki.o flash.o diff --git a/board/musenki/README b/board/musenki/README deleted file mode 100644 index 084ab54..0000000 --- a/board/musenki/README +++ /dev/null @@ -1,298 +0,0 @@ -U-Boot for a Musenki M-3/M-1 board ---------------------------- - -Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each. - -In board's notation, bank 0 is the one at the address of 0xFF800000 -and bank 1 is the one at the address of 0xFF000000. - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFF800000. - -There is a Davicom 9102A on-board, but I don't have it working yet. - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> help -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -icache - enable or disable instruction cache -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -source - run script from memory -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - - -Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> md ff800000 -ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot -ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd -ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate= -ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m -ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria -ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial. -ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip -ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4 -ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1 -ff800090: 36382e30 2e380000 00000000 00000000 68.0.8.......... -ff8000a0: 00000000 00000000 00000000 00000000 ................ -ff8000b0: 00000000 00000000 00000000 00000000 ................ -ff8000c0: 00000000 00000000 00000000 00000000 ................ -ff8000d0: 00000000 00000000 00000000 00000000 ................ -ff8000e0: 00000000 00000000 00000000 00000000 ................ -ff8000f0: 00000000 00000000 00000000 00000000 ................ -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> erase ff800000 ff81ffff -Erase Flash from 0xff800000 to 0xff81ffff - done -Erased 1 sectors -=> md ff800000 -ff800000: ffffffff ffffffff ffffffff ffffffff ................ -ff800010: ffffffff ffffffff ffffffff ffffffff ................ -ff800020: ffffffff ffffffff ffffffff ffffffff ................ -ff800030: ffffffff ffffffff ffffffff ffffffff ................ -ff800040: ffffffff ffffffff ffffffff ffffffff ................ -ff800050: ffffffff ffffffff ffffffff ffffffff ................ -ff800060: ffffffff ffffffff ffffffff ffffffff ................ -ff800070: ffffffff ffffffff ffffffff ffffffff ................ -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - -x.x.x Information - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> flinfo - -Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32) - Size: 4 MB in 32 Sectors - Sector Start Addresses: - FF800000 (RO) FF820000 FF840000 FF860000 FF880000 - FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000 - FF940000 FF960000 FF980000 FF9A0000 FF9C0000 - FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000 - FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000 - FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000 - FFBC0000 FFBE0000 - -Bank # 2: missing or unknown FLASH type -=> - - -x.x.x Flash Programming - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> -=> -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> cp 0 ff800000 20 -Copy to Flash... done -=> md ff800000 -ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5. -ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6. -ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3. -ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3. -ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3. -ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3..... -ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w. -ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3. -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - - -x.x.x Storage of environment variables in flash - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 106/16380 bytes -=> setenv myvar 1234 -=> saveenv -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 117/16380 bytes - -x.x Image Download and run over serial port - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> loads -## Ready for S-Record download ... - -## First Load Addr = 0x00040000 -## Last Load Addr = 0x00050177 -## Total Size = 0x00010178 = 65912 Bytes -## Start Addr = 0x00040004 -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "<NULL>" -Hit any key to exit ... - -## Application terminated, rc = 0x0 - - -x.x Image download and run over ethernet interface - -untested (not working yet, actually) diff --git a/board/musenki/flash.c b/board/musenki/flash.c deleted file mode 100644 index 080ec7f..0000000 --- a/board/musenki/flash.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/* - * don't ask. its stupid, but more than one soul has had to live with this mistake - * "swaptab[i]" is the value of "i" with the bits reversed. - */ - -#define MUSENKI_BROKEN_FLASH 1 - -#ifdef MUSENKI_BROKEN_FLASH -unsigned char swaptab[256] = { - 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, - 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, - 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, - 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, - 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, - 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, - 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, - 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, - 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, - 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, - 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, - 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, - 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, - 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, - 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, - 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, - 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, - 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, - 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, - 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, - 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, - 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, - 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, - 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, - 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, - 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, - 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, - 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, - 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, - 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, - 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, - 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, -}; - -#define BS(b) (swaptab[b]) - -#else - -#define BS(b) (b) - -#endif - -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE0_PRELIM); - - size_b0 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id, - size_b0, size_b0<<20); - } - - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE1_PRELIM); - size_b1 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE1_PRELIM, &flash_info[1]); - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info[1].size = size_b1; - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c deleted file mode 100644 index aa92fc4..0000000 --- a/board/musenki/musenki.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <pci.h> -#include <netdev.h> - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { -#if 0 - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth1 device */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, -#endif - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/mvblue/Kconfig b/board/mvblue/Kconfig deleted file mode 100644 index cee206b..0000000 --- a/board/mvblue/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MVBLUE - -config SYS_BOARD - default "mvblue" - -config SYS_CONFIG_NAME - default "MVBLUE" - -endif diff --git a/board/mvblue/MAINTAINERS b/board/mvblue/MAINTAINERS deleted file mode 100644 index 5955f1a..0000000 --- a/board/mvblue/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBLUE BOARD -#M: - -S: Maintained -F: board/mvblue/ -F: include/configs/MVBLUE.h -F: configs/MVBLUE_defconfig diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile deleted file mode 100644 index 76c10f8..0000000 --- a/board/mvblue/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mvblue.o flash.o diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c deleted file mode 100644 index 5dd658f..0000000 --- a/board/mvblue/flash.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001-2003 - * - * Changes for MATRIX Vision mvBLUE devices - * MATRIX Vision GmbH / hg,as info@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> - -#if 0 - #define mvdebug(p) printf ##p -#else - #define mvdebug(p) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define FLASH_BUS_WIDTH 8 - -#if (FLASH_BUS_WIDTH==32) - #define FLASH_DATA_MASK 0xffffffff - #define FLASH_SHIFT 1 - #define FDT vu_long -#elif (FLASH_BUS_WIDTH==16) - #define FLASH_DATA_MASK 0xff - #define FLASH_SHIFT 0 - #define FDT vu_short -#elif (FLASH_BUS_WIDTH==8) - #define FLASH_DATA_MASK 0xff - #define FLASH_SHIFT 0 - #define FDT vu_char -#else - #error FLASH_BUS_WIDTH undefined -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *address, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b0 = flash_get_size((vu_long *)0xffc00000, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH : Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - flash_get_offsets (0xffc00000, &flash_info[0]); - flash_info[0].size = size_b0; - - /* monitor protection OFF by default */ - flash_protect ( FLAG_PROTECT_CLEAR, 0xffc00000, 0x2000, flash_info ); - - return size_b0; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) - { /* bottom boot sector types - these are the useful ones! */ - /* set sector offsets for bottom boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) - { /* AMDLV320B has 8 x 8k bottom boot sectors */ - for (i = 0; i < 8; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT); - } - else - { /* other types have 4 bottom boot sectors (16,8,8,32) */ - i = 0; - info->start[i++] = base + 0x00000000; /* - */ - info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */ - info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */ - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT); - } - } - else - { /* top boot sector types - not so useful */ - /* set sector offsets for top boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) - { /* AMDLV320T has 8 x 8k top boot sectors */ - for (i = 0; i < info->sector_count - 8; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - } - else - { /* other types have 4 top boot sectors (32,8,8,16) */ - for (i = 0; i < info->sector_count - 4; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - - info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */ - info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */ - info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */ - info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */ - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_STM: printf ("ST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK) -#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK) -#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK) -#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK) -#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK) -#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK) -#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK) -#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK) -#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK) - -#if (FLASH_BUS_WIDTH >= 16) - #define AUTOSELECT_ADDR1 0x0555 - #define AUTOSELECT_ADDR2 0x02AA - #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 -#else - #define AUTOSELECT_ADDR1 0x0AAA - #define AUTOSELECT_ADDR2 0x0555 - #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 -#endif - -#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK) - -#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK) - - -static ulong flash_get_size (vu_long *address, flash_info_t *info) -{ - short i; - FDT value; - FDT *addr = (FDT *)address; - - ulong base = (ulong)address; - addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1; - addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2; - addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3; - __asm__ __volatile__("sync"); - - udelay(180); - - value = addr[0]; /* manufacturer ID */ - switch (value) { - case AMD_MANUFACT_MVS: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT_MVS: - info->flash_id = FLASH_MAN_FUJ; - break; - case STM_MANUFACT_MVS: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } -#if (FLASH_BUS_WIDTH >= 16) - value = addr[1]; /* device ID */ -#else - value = addr[2]; /* device ID */ -#endif - - switch (value) { - case AMD_ID_LV160T_MVS: - info->flash_id += FLASH_AM160T; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV160B_MVS: - info->flash_id += FLASH_AM160B; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV320T_MVS: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case AMD_ID_LV320B_MVS: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - case STM_ID_W320DT_MVS: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case STM_ID_W320DB_MVS: - info->flash_id += FLASH_STMW320DB; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - flash_get_offsets (base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (FDT *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (FDT *)info->start[0]; - *addr = RESET_BANK_DATA; /* reset bank */ - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -#if (FLASH_BUS_WIDTH >= 16) - #define ERASE_ADDR1 0x0555 - #define ERASE_ADDR2 0x02AA -#else - #define ERASE_ADDR1 0x0AAA - #define ERASE_ADDR2 0x0555 -#endif - -#define ERASE_ADDR3 ERASE_ADDR1 -#define ERASE_ADDR4 ERASE_ADDR1 -#define ERASE_ADDR5 ERASE_ADDR2 - -#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK) -#define ERASE_DATA4 ERASE_DATA1 -#define ERASE_DATA5 ERASE_DATA2 - -#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) -#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) -#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FDT *addr = (FDT *)(info->start[0]); - - int prot, sect, l_sect, flag; - ulong start, now, last; - - __asm__ __volatile__ ("sync"); - addr[0] = 0xf0; - udelay(1000); - - printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] ); - printf(" last = %d @ 0x%08lx\n", s_last , info->start[s_last ] ); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ERASE_ADDR1] = ERASE_DATA1; - addr[ERASE_ADDR2] = ERASE_DATA2; - addr[ERASE_ADDR3] = ERASE_DATA3; - addr[ERASE_ADDR4] = ERASE_DATA4; - addr[ERASE_ADDR5] = ERASE_DATA5; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { - addr = (FDT *)(info->start[sect]); - addr[0] = ERASE_SECTOR_DATA; - l_sect = sect; - } - } - - if (flag) - enable_interrupts(); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FDT *)(info->start[l_sect]); - - while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#define BUFF_INC 4 - ulong cp, wp, data; - int i, l, rc; - - mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt)); - - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt)); - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<BUFF_INC && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<BUFF_INC; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += BUFF_INC; - } - - /* - * handle (half)word aligned part - */ - mvdebug ((" handle word aligned part (cnt = 0x%08lx)\n", cnt)); - while (cnt >= BUFF_INC) { - data = 0; - for (i=0; i<BUFF_INC; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += BUFF_INC; - cnt -= BUFF_INC; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - mvdebug ((" handle unaligned tail bytes (cnt = 0x%08lx)\n", cnt)); - data = 0; - for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<BUFF_INC; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -#if (FLASH_BUS_WIDTH >= 16) - #define WRITE_ADDR1 0x0555 - #define WRITE_ADDR2 0x02AA -#else - #define WRITE_ADDR1 0x0AAA - #define WRITE_ADDR2 0x0555 - #define WRITE_ADDR3 WRITE_ADDR1 -#endif - -#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK) - -#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_char (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - printf(" *** ERROR: Flash not erased !\n"); - return (2); - } - flag = disable_interrupts(); - - addr[WRITE_ADDR1] = WRITE_DATA1; - addr[WRITE_ADDR2] = WRITE_DATA2; - addr[WRITE_ADDR3] = WRITE_DATA3; - *((vu_char *)dest) = data; - - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - addr = (vu_char *)dest; - while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - printf(" *** ERROR: Flash write timeout !"); - return (1); - } - } - mvdebug (("-write_byte\n")); - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - int i, - result = 0; - - mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest)); - for ( i=0; (i < 4) && (result == 0); i++, dest+=1 ) - result = write_char (info, dest, (data >> (8*(3-i))) & 0xff ); - mvdebug (("-write_word\n")); - return result; -} -/*---------------------------------------------------------------- */ diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c deleted file mode 100644 index 63503e8..0000000 --- a/board/mvblue/mvblue.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * GNU General Public License for more details. - * - * MATRIX Vision GmbH / June 2002-Nov 2003 - * Andre Schwarz - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/io.h> -#include <ns16550.h> -#include <netdev.h> - -#ifdef CONFIG_PCI -#include <pci.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -u32 get_BoardType (void); - -#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \ - | ((d&0x1f)<<11) \ - | ((f&0x7)<<7) \ - | (r&0xfc) ) - -int mv_pci_read (int bus, int dev, int func, int reg) -{ - *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg); - asm ("sync"); - return cpu_to_le32 (*(u32 *) (0xfee00cfc)); -} - -u32 get_BoardType () -{ - return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1); -} - -void init_2nd_DUART (void) -{ - NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2; - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE; - - *(u8 *) (0xfc004511) = 0x1; - NS16550_init (console, clock_divisor); -} -void hw_watchdog_reset (void) -{ - if (get_BoardType () == 0) { - *(u32 *) (0xff000005) = 0; - asm ("sync"); - } -} -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - u32 BoardType = get_BoardType (); - char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; - char *p; - - hw_watchdog_reset (); - - printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION); - printf (" Found %s running at %s MHz memory clock.\n", - BoardName[BoardType], strmhz (buf, busfreq)); - - init_2nd_DUART (); - - if ((p = getenv ("console_nr")) != NULL) { - unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - - gd->baudrate &= ~3; - gd->baudrate |= con_nr & 3; - } - return 0; -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - /* my DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv ("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - return e; -} - -u8 *dhcp_vendorex_proc (u8 * popt) -{ - return NULL; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Initialize PCI Devices - */ -#ifdef CONFIG_PCI -void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev) -{ - u32 cnt; - - printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev), - PCI_FUNC (dev)); - for (cnt = 0; cnt < 6; cnt++) - pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt), - 0x0); - printf ("done\n"); -} - -void duart_setup (u32 base, u16 divisor) -{ - printf ("duart setup ..."); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03); - out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07); - printf ("done\n"); -} - -void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose, - pci_dev_t bridge, unsigned char irq) -{ - pci_dev_t d; - unsigned char bus; - unsigned short vendor, class; - - pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus); - for (d = PCI_BDF (bus, 0, 0); - d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); - d += PCI_BDF (0, 0, 1)) { - pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor); - if (vendor != 0xffff && vendor != 0x0000) { - pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE, - &class); - if (class == PCI_CLASS_BRIDGE_PCI) - pci_mvblue_fixup_irq_behind_bridge (hose, d, - irq); - else - pci_hose_write_config_byte (hose, d, - PCI_INTERRUPT_LINE, - irq); - } - } -} - -#define MV_MAX_PCI_BUSSES 3 -#define SLOT0_IRQ 3 -#define SLOT1_IRQ 4 -void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - unsigned short class; - - if (PCI_BUS (dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xd: - if (get_BoardType () == 0) { - line = 1; - } else - /* mvBL */ - line = 2; - break; - case 0xe: - /* mvBB: IDE */ - line = 2; - pci_hose_write_config_byte (hose, dev, 0x8a, 0x20); - break; - case 0xf: - /* mvBB: Slot0 (Grabber) */ - pci_hose_read_config_word (hose, dev, - PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_BRIDGE_PCI) { - pci_mvblue_fixup_irq_behind_bridge (hose, dev, - SLOT0_IRQ); - line = 0xff; - } else - line = SLOT0_IRQ; - break; - case 0x10: - /* mvBB: Slot1 */ - pci_hose_read_config_word (hose, dev, - PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_BRIDGE_PCI) { - pci_mvblue_fixup_irq_behind_bridge (hose, dev, - SLOT1_IRQ); - line = 0xff; - } else - line = SLOT1_IRQ; - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", - PCI_DEV (dev)); - line = 0xff; - break; - } - pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, - line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvblue_fixup_irq -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} -#endif diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds deleted file mode 100644 index 5034a96..0000000 --- a/board/mvblue/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2001-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - lib/built-in.o (.text*) - net/built-in.o (.text*) - drivers/pci/built-in.o (.text*) - arch/powerpc/cpu/mpc824x/built-in.o (.text*) - board/mvblue/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sandpoint/Kconfig b/board/sandpoint/Kconfig deleted file mode 100644 index c19b63e..0000000 --- a/board/sandpoint/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if TARGET_SANDPOINT8240 - -config SYS_BOARD - default "sandpoint" - -config SYS_CONFIG_NAME - default "Sandpoint8240" - -endif - -if TARGET_SANDPOINT8245 - -config SYS_BOARD - default "sandpoint" - -config SYS_CONFIG_NAME - default "Sandpoint8245" - -endif diff --git a/board/sandpoint/MAINTAINERS b/board/sandpoint/MAINTAINERS deleted file mode 100644 index 569cf42..0000000 --- a/board/sandpoint/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -SANDPOINT BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/sandpoint/ -F: include/configs/Sandpoint8240.h -F: configs/Sandpoint8240_defconfig - -SANDPOINT8245 BOARD -#M: Jim Thompson <jim@musenki.com> -S: Orphan (since 2014-04) -F: include/configs/Sandpoint8245.h -F: configs/Sandpoint8245_defconfig diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile deleted file mode 100644 index 58f5a89..0000000 --- a/board/sandpoint/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sandpoint.o flash.o diff --git a/board/sandpoint/README b/board/sandpoint/README deleted file mode 100644 index c9996a8..0000000 --- a/board/sandpoint/README +++ /dev/null @@ -1,411 +0,0 @@ -This port of U-Boot will run on a Motorola Sandpoint 3 development -system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a -snapshot of work in progress and far from being completed. In order -to run it on the target system, it has to be downloaded using the -DINK32 monitor program that came with your Sandpoint system. Please -note that DINK32 does not accept the S-Record file created by the -U-Boot build process unmodified, because it contains CR/LF line -terminators. You have to strip the CR characters first. There is a -tiny script named 'dinkdl' I created for this purpose. - -The Sandpoint port is based on the work of Rob Taylor, who does not -seem to maintain it any more. I can be reached by mail as -tkoeller@gmx.net. - -Thomas Koeller - - -The port was tested on a Sandpoint 8240 X3 board, with U-Boot -installed in the flash memory of the CPU card. Please use the -following DIP switch settings: - -Motherboard: - -SW1.1: on SW1.2: on SW1.3: on SW1.4: on -SW1.5: on SW1.6: on SW1.7: on SW1.8: on - -SW2.1: on SW2.2: on SW2.3: on SW2.4: on -SW2.5: on SW2.6: on SW2.7: on SW2.8: on - - -CPU Card: - -SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on -SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF - -SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF -SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on - - -The followind detailed description of installation and initial steps -with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>: - - -Directions for installing U-Boot on Sandpoint+Unity8240 -using the Abatron BDI2000 BDM/JTAG debugger ... - -Background and Reference info: -http://u-boot.sourceforge.net/ -http://www.abatron.ch/ -http://www.abatron.ch/BDI/bdihw.html -http://www.abatron.ch/DataSheets/BDI2000.pdf -http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf -http://e-www.motorola.com/collateral/SPX3UM.pdf -http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf - - -Connection Diagram: - =========== - === ===== |----- | -| | <---------------> | | | | | -|PC | rs232 | BDI |=============[] | | -| | |2000 | BDM probe | | | -| | <---------------> | | |----- | - === ethernet ===== | | - | | - =========== - Sandpoint X3 with - Unity 8240 proc - - -PART 1) - DIP Switch Settings: - -Sandpoint X3 8240 processor board DIP switch settings, with -U-Boot to be installed in the flash memory of the CPU card: - -Motorola Sandpoint X3 Motherboard: -SW1.1: on SW1.2: on SW1.3: on SW1.4: on -SW1.5: on SW1.6: on SW1.7: on SW1.8: on -SW2.1: on SW2.2: on SW2.3: on SW2.4: on -SW2.5: on SW2.6: on SW2.7: on SW2.8: on - -Motorola Unity 8240 CPU Card: -SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on -SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF -SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF -SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on - - -PART 2) - Connect the BDI2000 Cable to the Sandpoint/Unity 8240: - -BDM Pin 1 on the Unity 8240 processor board is towards the -PCI PMC connectors, or away from the socketed SDRAM, i.e.: - - ==================== - | ---------------- | - | | SDRAM | | - | | | | - | ---------------- | - | |~| | - | |B| ++++++ | - | |D| + uP + | - | |M| +8240+ | - | ~ 1 ++++++ | - | | - | | - | | - | PMC conn ====== | - | ===== ====== | - | | - ==================== - - -PART 3) - Setting up the BDI2000, and preparing for TCP/IP network comms: - -Connect the BDI2000 to the PC using the supplied serial cable. -Download the BDI2000 software and install it using setup.exe. - -[Note: of course you can also use the Linux command line tool -"bdisetup" to configure your BDI2000 - the sources are included on -the floppy disk that comes with your BDI2000. Just in case you don't -have any Windows PC's - like me :-) -- wd ] - -Power up the BDI2000; then follow directions to assign the IP -address and related network information. Note that U-Boot -will be loaded to the Sandpoint via tftp. You need to either -use the Abatron-provided tftp application or provide a tftp -server (e.g. Linux/Solaris/*BSD) somewhere on your network. -Once the IP address etc are assigned via the RS232 port, -further communication with the BDI2000 will happen via the -ethernet connection. - -PART 4) - Making a TCP/IP network connection to the Abatron BDI2000: - -Telnet to the Abatron BDI2000. Assuming that all of the -networking info was loaded via RS232 correctly, you will see -the following (scrolling): - -- TARGET: waiting for target Vcc -- TARGET: waiting for target Vcc - - -PART 5) - Power up the target Sandpoint: -If the BDM connections are correct, the following will now appear: - -- TARGET: waiting for target Vcc -- TARGET: waiting for target Vcc -- TARGET: processing power-up delay -- TARGET: processing user reset request -- BDI asserts HRESET -- Reset JTAG controller passed -- Bypass check: 0x55 => 0xAA -- Bypass check: 0x55 => 0xAA -- JTAG exists check passed -- Target PVR is 0x00810101 -- COP status is 0x01 -- Check running state passed -- BDI scans COP freeze command -- BDI removes HRESET -- COP status is 0x05 -- Check stopped state passed -- Check LSRL length passed -- BDI sets breakpoint at 0xFFF00100 -- BDI resumes program execution -- Waiting for target stop passed -- TARGET: Target PVR is 0x00810101 -- TARGET: reseting target passed -- TARGET: processing target startup .... -- TARGET: processing target startup passed -BDI> - - -PART 6) - Erase the current contents of the flash memory: - -BDI>era 0xFFF00000 - Erasing flash at 0xfff00000 - Erasing flash passed -BDI>era 0xFFF04000 - Erasing flash at 0xfff04000 - Erasing flash passed -BDI>era 0xFFF06000 - Erasing flash at 0xfff06000 - Erasing flash passed -BDI>era 0xFFF08000 - Erasing flash at 0xfff08000 - Erasing flash passed -BDI>era 0xFFF10000 - Erasing flash at 0xfff10000 - Erasing flash passed -BDI>era 0xFFF20000 - Erasing flash at 0xfff20000 - Erasing flash passed - - -PART 7) - Program the flash memory with the U-Boot image: - -BDI>prog 0xFFF00000 u-boot.bin bin - Programming u-boot.bin , please wait .... - Programming flash passed - - -PART 8) - Connect PC to Sandpoint: -Using a crossover serial cable, attach the PC serial port to the -Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. - - -PART 9) - Reset the Unity and begin U-Boot execution: - -BDI>reset -- TARGET: processing user reset request -- TARGET: Target PVR is 0x00810101 -- TARGET: reseting target passed -- TARGET: processing target init list .... -- TARGET: processing target init list passed - -BDI>go - -Now see output from U-Boot running, sent via serial port: - -U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) - -CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: Sandpoint 8240 Unity -DRAM: 64 MB -FLASH: 2 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 - 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 - 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 -In: serial -Out: serial -Err: serial -=> - - -PART 10) - Set and save any required environmental variables, examples of some: - -=> setenv ethaddr 00:03:47:97:D0:79 -=> setenv bootfile your_qnx_image_here -=> setenv hostname sandpointX -=> setenv netmask 255.255.255.0 -=> setenv ipaddr 192.168.0.11 -=> setenv serverip 192.168.0.10 -=> setenv gatewayip=192.168.0.1 -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - -**** Example environment: **** - -=> printenv -baudrate=9600 -bootfile=telemetry -hostname=sp1 -ethaddr=00:03:47:97:E4:6B -load=tftp 100000 u-boot.bin -update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv -filesize=1f304 -gatewayip=145.17.228.1 -netmask=255.255.255.0 -ipaddr=145.17.228.42 -serverip=145.17.242.46 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 332/8188 bytes -=> - -here's some text useful stuff for cut-n-paste: -setenv hostname sandpoint1 -setenv netmask 255.255.255.0 -setenv ipaddr 145.17.228.81 -setenv serverip 145.17.242.46 -setenv gatewayip 145.17.228.1 -saveenv - -PART 11) - Test U-Boot by tftp'ing new U-Boot, overwriting current: - -=> protect off all -Un-Protect Flash Bank # 1 -=> tftp 100000 u-boot.bin -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 127628 (1f28c hex) -=> era all -Erase Flash Bank # 1 - done -Erase Flash Bank # 2 - missing -=> cp.b 0x100000 FFF00000 1f28c -Copy to Flash... done -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> reset - -You can put these commands into some environment variables; - -=> setenv load tftp 100000 u-boot.bin -=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv -=> saveenv - -Then you just have to type "run load" then "run update" - -=> run load -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 127748 (1f304 hex) -=> run update -Un-Protect Flash Bank # 1 -Un-Protect Flash Bank # 2 -Erase Flash from 0xfff00000 to 0xfff3ffff - done -Erased 7 sectors -Copy to Flash... done -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - - -PART 12) - Load OS image (ELF format) via U-Boot using tftp - - -=> tftp 800000 sandpoint-simple.elf -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'sandpoint-simple.elf'. -Load address: 0x800000 -Loading: ################################################################# - ################################################################# - ################################################################# - ######################## -done -Bytes transferred = 1120284 (11181c hex) -==> - -PART 13) - Begin OS image execution: (note that unless you have the -serial parameters of your OS image set to 9600 (i.e. same as -the U-Boot binary) you will get garbage here until you change -the serial communications speed. - -=> bootelf 800000 -Loading @ 0x001f0100 (1120028 bytes) -## Starting application at 0x001f1d28 ... -Replace init_hwinfo() with a board specific version - -Loading QNX6.... - -Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 -<...loader and kernel messages snipped...> - -Welcome to Neutrino on the Sandpoint -# - - -other information: - -CVS Retrieval Notes: - -U-Boot's SourceForge CVS repository can be checked out -through anonymous (pserver) CVS with the following -instruction set. The module you wish to check out must -be specified as the modulename. When prompted for a -password for anonymous, simply press the Enter key. - -cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login - -cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl deleted file mode 100644 index f281452..0000000 --- a/board/sandpoint/dinkdl +++ /dev/null @@ -1,2 +0,0 @@ -#! /bin/bash -tr -d "\r" <$1 >/dev/tts/1 diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c deleted file mode 100644 index 1ab668c..0000000 --- a/board/sandpoint/flash.c +++ /dev/null @@ -1,748 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/pci_io.h> -#include <w83c553f.h> - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif /* 0 */ - -/*flash command address offsets*/ - -#if 0 -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) -#else -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) -#endif - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -#if 0 -static int byte_parity_odd(unsigned char x) __attribute__ ((const)); -#endif /* 0 */ -static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); - -typedef struct -{ - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -#if 0 -static int -byte_parity_odd(unsigned char x) -{ - x ^= x >> 4; - x ^= x >> 2; - x ^= x >> 1; - return (x & 0x1) != 0; -} -#endif /* 0 */ - - -static unsigned long -flash_id(unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = - { - {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = - { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if(p->extval == chip) - { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if(p->extval == mfct) - { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - - -unsigned long -flash_init(void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - { - flash_info_t * const pflinfo = &flash_info[i]; - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Sandpoint flash */ - { - register unsigned char temp; - CONFIG_READ_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); - temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); - } - - for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) - { - flash_info_t * const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; -#if 0 - volatile FLASH_WORD_SIZE * addr2; -#endif -#if 0 - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; -#else - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; -#endif - __asm__ __volatile__("sync"); - -#if 0 - pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); -#else - pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]); -#endif - - switch(pflinfo->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for(j = 0; j < 8; j++) - { - pflinfo->start[j] = base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for(j = 1; j < 16; j++) - { - pflinfo->start[j+3] = base_address + 0x00010000 * j; - } -#if 0 - /* check for protected sectors */ - for (j = 0; j < pflinfo->sector_count; j++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]); - if (pflinfo->flash_id & FLASH_MAN_SST) - pflinfo->protect[j] = 0; - else - pflinfo->protect[j] = addr2[2] & 1; - } -#endif - break; - } - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -#if 0 -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void -flash_print_info(flash_info_t *info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if(info->flash_id != FLASH_UNKNOWN) - { - switch(info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: mfct = "AMD"; break; - case FLASH_MAN_FUJ: mfct = "FUJITSU"; break; - case FLASH_MAN_STM: mfct = "STM"; break; - case FLASH_MAN_SST: mfct = "SST"; break; - case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break; - case FLASH_MAN_INTEL: mfct = "Intel"; break; - } - - switch(info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; - case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; - case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; - case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; - case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; - case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; - case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; - case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; - case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break; - case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break; - case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break; - } - } - - printf( - "\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, - type, - info->size >> 10, - info->sector_count - ); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) - { - unsigned long size; - unsigned int erased; - unsigned long * flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ) - erased = *flash == ~0x0UL; - - printf( - "%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", - info->protect[i] ? "RO" : " " - ); - } - - puts("\n"); - return; -} - -#if 0 - -/* - * The following code cannot be run from FLASH! - */ -ulong -flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - printf("flash_get_size: \n"); - /* Write auto select command: read Manufacturer ID */ - eieio(); - addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x55; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x90; - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - printf("recognised manufacturer"); - - value = addr2[ADDR3]; /* device ID */ - debug ("\ndev_code=%x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size); - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if (info->flash_id & FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -#endif - - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[sect] - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST) - { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[l_sect] - info->start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c deleted file mode 100644 index 16237bd..0000000 --- a/board/sandpoint/sandpoint.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <pci.h> -#include <netdev.h> - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Sandpoint " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " Unity ##Test not implemented yet##\n"); - return 0; -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds deleted file mode 100644 index cd9f07c..0000000 --- a/board/sandpoint/u-boot.lds +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2001-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text.v*printf) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/utx8245/Kconfig b/board/utx8245/Kconfig deleted file mode 100644 index aec0eb9..0000000 --- a/board/utx8245/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_UTX8245 - -config SYS_BOARD - default "utx8245" - -config SYS_CONFIG_NAME - default "utx8245" - -endif diff --git a/board/utx8245/MAINTAINERS b/board/utx8245/MAINTAINERS deleted file mode 100644 index bed69c8..0000000 --- a/board/utx8245/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -UTX8245 BOARD -M: Greg Allen <gallen@arlut.utexas.edu> -S: Maintained -F: board/utx8245/ -F: include/configs/utx8245.h -F: configs/utx8245_defconfig diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile deleted file mode 100644 index f12e545..0000000 --- a/board/utx8245/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Gregory E. Allen, gallen@arlut.utexas.edu -# Matthew E. Karger, karger@arlut.utexas.edu -# Applied Research Laboratories, The University of Texas at Austin -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = utx8245.o flash.o diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c deleted file mode 100644 index 1dfcb41..0000000 --- a/board/utx8245/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ -#define MAIN_SECT_SIZE 0x10000 -#define SECT_SIZE_32KB 0x8000 -#define SECT_SIZE_8KB 0x2000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static int write_word (flash_info_t * info, ulong dest, ulong data); -#if 0 -static void write_via_fpu (vu_long * addr, ulong * data); -#endif -static __inline__ unsigned long get_msr (void); -static __inline__ void set_msr (unsigned long msr); - -/*flash command address offsets*/ -#define ADDR0 (0x555) -#define ADDR1 (0xAAA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*---------------------------------------------------------------------*/ -/*#define DEBUG_FLASH 1 */ - -/*---------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - int i; /* flash bank counter */ - int j; /* flash device sector counter */ - int k; /* flash size calculation loop counter */ - int N; /* pow(2,N) is flash size, but we don't have <math.h> */ - ulong total_size = 0, device_size = 1; - unsigned char manuf_id, device_id; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - vu_char *addr = (vu_char *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0x555] = 0xAA; /* get manuf/device info command */ - addr[0x2AA] = 0x55; /* 3-cycle command */ - addr[0x555] = 0x90; - - manuf_id = addr[0]; /* read back manuf/device info */ - device_id = addr[1]; - - addr[0x55] = 0x98; /* CFI command */ - N = addr[0x27]; /* read back device_size = pow(2,N) */ - - for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */ - device_size *= 2; - - flash_info[i].size = device_size; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - -#if defined DEBUG_FLASH - printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id); -#endif - /* find out what kind of flash we are using */ - if ((manuf_id == (uchar) (AMD_MANUFACT)) - && (device_id == AMD_ID_LV033C)) { - flash_info[i].flash_id = - ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (FLASH_AM033C & FLASH_TYPEMASK); - - /* set individual sector start addresses */ - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - } - } - - else if ((manuf_id == (uchar) (AMD_MANUFACT)) && - (device_id == AMD_ID_LV116DT)) { - flash_info[i].flash_id = - ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (FLASH_AM160T & FLASH_TYPEMASK); - - /* set individual sector start addresses */ - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - - if (j < (CONFIG_SYS_MAX_FLASH_SECT - 3)) { - flash_info[i].start[j] = - (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - } else if (j == (CONFIG_SYS_MAX_FLASH_SECT - 3)) { - flash_info[i].start[j] = - (flash_info[i].start[j - 1] + SECT_SIZE_32KB); - - } else { - flash_info[i].start[j] = - (flash_info[i].start[j - 1] + SECT_SIZE_8KB); - } - } - } - - else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFF; - goto Done; - } - -#if defined DEBUG_FLASH - printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id); -#endif - - addr[0] = 0xFF; - - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - total_size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - Done: - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: - type = "AM29LV033C (32 Mbit, uniform sector size)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> - start[sect] - - info-> - start[0]) << - sh8b)); - - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else { - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ -#if 0 -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} -#endif - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c deleted file mode 100644 index 69d19e3..0000000 --- a/board/utx8245/utx8245.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <pci.h> -#include <netdev.h> - -#define SAVE_SZ 32 - - -int checkboard(void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - - -phys_size_t initdram(int board_type) -{ - long size; - long new_bank0_end; - long new_bank1_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size/2 - 1; - new_bank1_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - - mear1 = (mear1 & 0xFFFF0000) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8); - emear1 = (emear1 & 0xFFFF0000) | - ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8); - - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - - -/* - * Initialize PCI Devices, report devices found. - */ - -static struct pci_config_table pci_utx8245_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, - PCI_FIREWIRE_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, -#endif /*CONFIG_PCI_PNP*/ - { } -}; - - -static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - if (PCI_DEV(dev) == 11) - /* assign serial interrupt line 9 (int25) to FireWire */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25); - - else if (PCI_DEV(dev) == 12) - /* assign serial interrupt line 8 (int24) to Ethernet */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); - - else if (PCI_DEV(dev) == 14) - /* assign serial interrupt line 0 (int16) to PMC slot 0 */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); - - else if (PCI_DEV(dev) == 15) - /* assign serial interrupt line 1 (int17) to PMC slot 1 */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); -} - -static struct pci_controller utx8245_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_utx8245_config_table, - fixup_irq: pci_utx8245_fixup_irq, - write_byte: pci_hose_write_config_byte -#endif /*CONFIG_PCI_PNP*/ -}; - -void pci_init_board (void) -{ - pci_mpc824x_init(&utx8245_hose); - - icache_enable(); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index ddc24be..682d18f 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -331,11 +331,8 @@ int check_ide_device (int slot) ide_devices_found |= (1 << slot); -#if CONFIG_CPC45 -#else /* set I/O area in config reg -> only valid for ARGOSY D5!!! */ *((uchar *)(addr + config_base)) = 1; -#endif #if 0 printf("\n## Config_base = %04x ###\n", config_base); printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base); diff --git a/configs/A3000_defconfig b/configs/A3000_defconfig deleted file mode 100644 index e1923de..0000000 --- a/configs/A3000_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_A3000=y diff --git a/configs/CPC45_ROMBOOT_defconfig b/configs/CPC45_ROMBOOT_defconfig deleted file mode 100644 index 4aae7f6..0000000 --- a/configs/CPC45_ROMBOOT_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM" -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_CPC45=y diff --git a/configs/CPC45_defconfig b/configs/CPC45_defconfig deleted file mode 100644 index 77ae66c..0000000 --- a/configs/CPC45_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_CPC45=y diff --git a/configs/CU824_defconfig b/configs/CU824_defconfig deleted file mode 100644 index 0f22188..0000000 --- a/configs/CU824_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_CU824=y diff --git a/configs/MUSENKI_defconfig b/configs/MUSENKI_defconfig deleted file mode 100644 index 586364c..0000000 --- a/configs/MUSENKI_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_MUSENKI=y diff --git a/configs/MVBLUE_defconfig b/configs/MVBLUE_defconfig deleted file mode 100644 index f979983..0000000 --- a/configs/MVBLUE_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_MVBLUE=y diff --git a/configs/Sandpoint8240_defconfig b/configs/Sandpoint8240_defconfig deleted file mode 100644 index 332e4c0..0000000 --- a/configs/Sandpoint8240_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_SANDPOINT8240=y diff --git a/configs/Sandpoint8245_defconfig b/configs/Sandpoint8245_defconfig deleted file mode 100644 index b36757c..0000000 --- a/configs/Sandpoint8245_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_SANDPOINT8245=y diff --git a/configs/eXalion_defconfig b/configs/eXalion_defconfig deleted file mode 100644 index 9d7e090..0000000 --- a/configs/eXalion_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_EXALION=y diff --git a/configs/utx8245_defconfig b/configs/utx8245_defconfig deleted file mode 100644 index c2107cc..0000000 --- a/configs/utx8245_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC824X=y -CONFIG_TARGET_UTX8245=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 5df0664..5d2875c 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,15 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +A3000 powerpc mpc824x - - +CPC45 powerpc mpc824x - - Josef Wagner <Wagner@Microsys.de> +CU824 powerpc mpc824x - - Wolfgang Denk <wd@denx.de> +eXalion powerpc mpc824x - - Torsten Demke <torsten.demke@fci.com> +MVBLUE powerpc mpc824x - - +MUSENKI powerpc mpc824x - - Jim Thompson <jim@musenki.com> +Sandpoint8240 powerpc mpc824x - - Wolfgang Denk <wd@denx.de> +Sandpoint8245 powerpc mpc824x - - Jim Thompson <jim@musenki.com> +utx8245 powerpc mpc824x - - Greg Allen <gallen@arlut.utexas.edu> atc powerpc mpc8260 - - Wolfgang Denk <wd@denx.de> CPU86 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de> CPU87 powerpc mpc8260 - - diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 91821f4..c506f79 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_I82365) += i82365.o obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o obj-y += tqm8xx_pcmcia.o diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c deleted file mode 100644 index 84a3d2e..0000000 --- a/drivers/pcmcia/i82365.c +++ /dev/null @@ -1,989 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - ******************************************************************** - * - * Lots of code copied from: - * - * i82365.c 1.352 - Linux driver for Intel 82365 and compatible - * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. - * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net> - */ - -#include <common.h> - -#include <command.h> -#include <pci.h> -#include <pcmcia.h> -#include <asm/io.h> - -#include <pcmcia/ss.h> -#include <pcmcia/i82365.h> -#include <pcmcia/yenta.h> -#ifdef CONFIG_CPC45 -#include <pcmcia/cirrus.h> -#else -#include <pcmcia/ti113x.h> -#endif - -static struct pci_device_id supported[] = { -#ifdef CONFIG_CPC45 - {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, -#else - {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510}, -#endif - {0, 0} -}; - -#define CYCLE_TIME 120 - -#ifdef CONFIG_CPC45 -extern int SPD67290Init (void); -#endif - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev); -#endif - -typedef struct socket_info_t { - pci_dev_t dev; - u_short bcr; - u_char pci_lat, cb_lat, sub_bus, cache; - u_int cb_phys; - - socket_cap_t cap; - u_short type; - u_int flags; -#ifdef CONFIG_CPC45 - cirrus_state_t c_state; -#else - ti113x_state_t state; -#endif -} socket_info_t; - -#ifdef CONFIG_CPC45 -/* These definitions must match the pcic table! */ -typedef enum pcic_id { - IS_PD6710, IS_PD672X, IS_VT83C469 -} pcic_id; - -typedef struct pcic_t { - char *name; -} pcic_t; - -static pcic_t pcic[] = { - {" Cirrus PD6710: "}, - {" Cirrus PD672x: "}, - {" VIA VT83C469: "}, -}; -#endif - -static socket_info_t socket; -static socket_state_t state; -static struct pccard_mem_map mem; -static struct pccard_io_map io; - -/*====================================================================*/ - -/* Some PCI shortcuts */ - -static int pci_readb (socket_info_t * s, int r, u_char * v) -{ - return pci_read_config_byte (s->dev, r, v); -} -static int pci_writeb (socket_info_t * s, int r, u_char v) -{ - return pci_write_config_byte (s->dev, r, v); -} -static int pci_readw (socket_info_t * s, int r, u_short * v) -{ - return pci_read_config_word (s->dev, r, v); -} -static int pci_writew (socket_info_t * s, int r, u_short v) -{ - return pci_write_config_word (s->dev, r, v); -} -#ifndef CONFIG_CPC45 -static int pci_readl (socket_info_t * s, int r, u_int * v) -{ - return pci_read_config_dword (s->dev, r, v); -} -static int pci_writel (socket_info_t * s, int r, u_int v) -{ - return pci_write_config_dword (s->dev, r, v); -} -#endif /* !CONFIG_CPC45 */ - -/*====================================================================*/ - -#ifdef CONFIG_CPC45 - -#define cb_readb(s) readb((s)->cb_phys + 1) -#define cb_writeb(s, v) writeb(v, (s)->cb_phys) -#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - u_char val; -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - val = cb_readb (s); - - debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); - return val; -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ -#ifdef CONFIG_PCMCIA_SLOT_A - int slot = 0; -#else - int slot = 1; -#endif - u_char val; - - val = I365_REG (slot, reg); - - cb_writeb (s, val); - cb_writeb2 (s, data); - - debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); -} - -#else /* ! CONFIG_CPC45 */ - -#define cb_readb(s, r) readb((s)->cb_phys + (r)) -#define cb_readl(s, r) readl((s)->cb_phys + (r)) -#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r)) -#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) - -static u_char i365_get (socket_info_t * s, u_short reg) -{ - return cb_readb (s, 0x0800 + reg); -} - -static void i365_set (socket_info_t * s, u_short reg, u_char data) -{ - cb_writeb (s, 0x0800 + reg, data); -} -#endif /* CONFIG_CPC45 */ - -static void i365_bset (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) | mask); -} - -static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) -{ - i365_set (s, reg, i365_get (s, reg) & ~mask); -} - -#if 0 /* not used */ -static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) -{ - u_char d = i365_get (s, reg); - - i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); -} - -static u_short i365_get_pair (socket_info_t * s, u_short reg) -{ - return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); -} -#endif /* not used */ - -static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) -{ - i365_set (s, reg, data & 0xff); - i365_set (s, reg + 1, data >> 8); -} - -#ifdef CONFIG_CPC45 -/*====================================================================== - - Code to save and restore global state information for Cirrus - PD67xx controllers, and to set and report global configuration - options. - -======================================================================*/ - -#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) - -static void cirrus_get_state (socket_info_t * s) -{ - int i; - cirrus_state_t *p = &s->c_state; - - p->misc1 = i365_get (s, PD67_MISC_CTL_1); - p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - p->misc2 = i365_get (s, PD67_MISC_CTL_2); - for (i = 0; i < 6; i++) - p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); - -} - -static void cirrus_set_state (socket_info_t * s) -{ - int i; - u_char misc; - cirrus_state_t *p = &s->c_state; - - misc = i365_get (s, PD67_MISC_CTL_2); - i365_set (s, PD67_MISC_CTL_2, p->misc2); - if (misc & PD67_MC2_SUSPEND) - udelay (50000); - misc = i365_get (s, PD67_MISC_CTL_1); - misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); - i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); - for (i = 0; i < 6; i++) - i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); -} - -static u_int cirrus_set_opts (socket_info_t * s) -{ - cirrus_state_t *p = &s->c_state; - u_int mask = 0xffff; - char buf[200] = {0}; - - if (has_ring == -1) - has_ring = 1; - flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); - flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); -#if DEBUG - if (p->misc2 & PD67_MC2_IRQ15_RI) - strcat (buf, " [ring]"); - if (p->misc2 & PD67_MC2_DYNAMIC_MODE) - strcat (buf, " [dyn mode]"); - if (p->misc1 & PD67_MC1_INPACK_ENA) - strcat (buf, " [inpack]"); -#endif - - if (p->misc2 & PD67_MC2_IRQ15_RI) - mask &= ~0x8000; - if (has_led > 0) { -#if DEBUG - strcat (buf, " [led]"); -#endif - mask &= ~0x1000; - } - if (has_dma > 0) { -#if DEBUG - strcat (buf, " [dma]"); -#endif - mask &= ~0x0600; - flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); -#if DEBUG - if (p->misc2 & PD67_MC2_FREQ_BYPASS) - strcat (buf, " [freq bypass]"); -#endif - } - - if (setup_time >= 0) - p->timer[0] = p->timer[3] = setup_time; - if (cmd_time > 0) { - p->timer[1] = cmd_time; - p->timer[4] = cmd_time * 2 + 4; - } - if (p->timer[1] == 0) { - p->timer[1] = 6; - p->timer[4] = 16; - if (p->timer[0] == 0) - p->timer[0] = p->timer[3] = 1; - } - if (recov_time >= 0) - p->timer[2] = p->timer[5] = recov_time; - - debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", - buf, - p->timer[0], p->timer[1], p->timer[2], - p->timer[3], p->timer[4], p->timer[5]); - - return mask; -} - -#else /* !CONFIG_CPC45 */ - -/*====================================================================== - - Code to save and restore global state information for TI 1130 and - TI 1131 controllers, and to set and report global configuration - options. - -======================================================================*/ - -static void ti113x_get_state (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - - pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl); - pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl); - pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl); - pci_readb (s, TI1250_DIAGNOSTIC, &p->diag); - pci_readl (s, TI12XX_IRQMUX, &p->irqmux); -} - -static void ti113x_set_state (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - - pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl); - pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl); - pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl); - pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0); - pci_writeb (s, TI1250_DIAGNOSTIC, p->diag); - pci_writel (s, TI12XX_IRQMUX, p->irqmux); - i365_set_pair (s, TI113X_IO_OFFSET (0), 0); - i365_set_pair (s, TI113X_IO_OFFSET (1), 0); -} - -static u_int ti113x_set_opts (socket_info_t * s) -{ - ti113x_state_t *p = &s->state; - u_int mask = 0xffff; - - p->cardctl &= ~TI113X_CCR_ZVENABLE; - p->cardctl |= TI113X_CCR_SPKROUTEN; - - return mask; -} -#endif /* CONFIG_CPC45 */ - -/*====================================================================== - - Routines to handle common CardBus options - -======================================================================*/ - -/* Default settings for PCI command configuration register */ -#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ - PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) - -static void cb_get_state (socket_info_t * s) -{ - pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); - pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); - pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); - pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); - pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); - pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); -} - -static void cb_set_state (socket_info_t * s) -{ -#ifndef CONFIG_CPC45 - pci_writel (s, CB_LEGACY_MODE_BASE, 0); - pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys); -#endif - pci_writew (s, PCI_COMMAND, CMD_DFLT); - pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); - pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); - pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); - pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); - pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); - pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); -} - -static void cb_set_opts (socket_info_t * s) -{ -#ifndef CONFIG_CPC45 - if (s->cache == 0) - s->cache = 8; - if (s->pci_lat == 0) - s->pci_lat = 0xa8; - if (s->cb_lat == 0) - s->cb_lat = 0xb0; -#endif -} - -/*====================================================================== - - Power control for Cardbus controllers: used both for 16-bit and - Cardbus cards. - -======================================================================*/ - -static int cb_set_power (socket_info_t * s, socket_state_t * state) -{ - u_int reg = 0; - -#ifdef CONFIG_CPC45 - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - if (state->Vpp != 0) { - if (state->Vpp == 120) { - reg |= I365_VPP1_12V; - puts (" 12V card found: "); - } else if (state->Vpp == state->Vcc) { - reg |= I365_VPP1_5V; - } else { - puts (" power not found: "); - return -1; - } - } - if (state->Vcc != 0) { - reg |= I365_VCC_5V; - if (state->Vcc == 33) { - puts (" 3.3V card found: "); - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else if (state->Vcc == 50) { - puts (" 5V card found: "); - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - puts (" power not found: "); - return -1; - } - } - - if (reg != i365_get (s, I365_POWER)) { - reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); - i365_set (s, I365_POWER, reg); - } - -#else /* ! CONFIG_CPC45 */ - - /* restart card voltage detection if it seems appropriate */ - if ((state->Vcc == 0) && (state->Vpp == 0) && - !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE)) - cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST); - switch (state->Vcc) { - case 0: - reg = 0; - break; - case 33: - reg = CB_SC_VCC_3V; - break; - case 50: - reg = CB_SC_VCC_5V; - break; - default: - return -1; - } - switch (state->Vpp) { - case 0: - break; - case 33: - reg |= CB_SC_VPP_3V; - break; - case 50: - reg |= CB_SC_VPP_5V; - break; - case 120: - reg |= CB_SC_VPP_12V; - break; - default: - return -1; - } - if (reg != cb_readl (s, CB_SOCKET_CONTROL)) - cb_writel (s, CB_SOCKET_CONTROL, reg); -#endif /* CONFIG_CPC45 */ - return 0; -} - -/*====================================================================== - - Generic routines to get and set controller options - -======================================================================*/ - -static void get_bridge_state (socket_info_t * s) -{ -#ifdef CONFIG_CPC45 - cirrus_get_state (s); -#else - ti113x_get_state (s); -#endif - cb_get_state (s); -} - -static void set_bridge_state (socket_info_t * s) -{ - cb_set_state (s); - i365_set (s, I365_GBLCTL, 0x00); - i365_set (s, I365_GENCTL, 0x00); -#ifdef CONFIG_CPC45 - cirrus_set_state (s); -#else - ti113x_set_state (s); -#endif -} - -static void set_bridge_opts (socket_info_t * s) -{ -#ifdef CONFIG_CPC45 - cirrus_set_opts (s); -#else - ti113x_set_opts (s); -#endif - cb_set_opts (s); -} - -/*====================================================================*/ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ -#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) - -#define pd67_ext_get(s, r) \ - (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) - -static int i365_get_status (socket_info_t * s, u_int * value) -{ - u_int status; -#ifdef CONFIG_CPC45 - u_char val; - u_char power, vcc, vpp; - u_int powerstate; -#endif - - status = i365_get (s, I365_IDENT); - status = i365_get (s, I365_STATUS); - *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; - if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { - *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; - } else { - *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; - *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; - } - *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; - *value |= (status & I365_CS_READY) ? SS_READY : 0; - *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; - -#ifdef CONFIG_CPC45 - /* Check for Cirrus CL-PD67xx chips */ - i365_set (s, PD67_CHIP_INFO, 0); - val = i365_get (s, PD67_CHIP_INFO); - s->type = -1; - if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { - val = i365_get (s, PD67_CHIP_INFO); - if ((val & PD67_INFO_CHIP_ID) == 0) { - s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; - i365_set (s, PD67_EXT_INDEX, 0xe5); - if (i365_get (s, PD67_EXT_INDEX) != 0xe5) - s->type = IS_VT83C469; - } - } else { - printf ("no Cirrus Chip found\n"); - *value = 0; - return -1; - } - - power = i365_get (s, I365_POWER); - state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; - state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; - vcc = power & I365_VCC_MASK; - vpp = power & I365_VPP1_MASK; - state.Vcc = state.Vpp = 0; - if((vcc== 0) || (vpp == 0)) { - /* - * On the Cirrus we get the info which card voltage - * we have in EXTERN DATA and write it to MISC_CTL1 - */ - powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); - if (powerstate & PD67_EXD_VS1(0)) { - /* 5V Card */ - i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } else { - /* 3.3V Card */ - i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); - } - i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); - power = i365_get (s, I365_POWER); - } - if (power & I365_VCC_5V) { - state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; - } - - if (power == I365_VPP1_12V) - state.Vpp = 120; - - /* IO card, RESET flags, IO interrupt */ - power = i365_get (s, I365_INTCTL); - state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; - if (power & I365_PC_IOCARD) - state.flags |= SS_IOCARD; - state.io_irq = power & I365_IRQ_MASK; - - /* Card status change mask */ - power = i365_get (s, I365_CSCINT); - state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; - if (state.flags & SS_IOCARD) - state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; - else { - state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; - state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; - state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; - } - debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " - "io_irq %d, csc_mask %#2.2x\n", state.flags, - state.Vcc, state.Vpp, state.io_irq, state.csc_mask); - -#else /* !CONFIG_CPC45 */ - - status = cb_readl (s, CB_SOCKET_STATE); - *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0; - *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0; - *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0; - *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING; - /* For now, ignore cards with unsupported voltage keys */ - if (*value & SS_XVCARD) - *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD); -#endif /* CONFIG_CPC45 */ - return 0; -} /* i365_get_status */ - -static int i365_set_socket (socket_info_t * s, socket_state_t * state) -{ - u_char reg; - - set_bridge_state (s); - - /* IO card, RESET flag */ - reg = 0; - reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; - reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; - i365_set (s, I365_INTCTL, reg); - -#ifdef CONFIG_CPC45 - cb_set_power (s, state); - -#if 0 - /* Card status change interrupt mask */ - reg = s->cs_irq << 4; - if (state->csc_mask & SS_DETECT) - reg |= I365_CSC_DETECT; - if (state->flags & SS_IOCARD) { - if (state->csc_mask & SS_STSCHG) - reg |= I365_CSC_STSCHG; - } else { - if (state->csc_mask & SS_BATDEAD) - reg |= I365_CSC_BVD1; - if (state->csc_mask & SS_BATWARN) - reg |= I365_CSC_BVD2; - if (state->csc_mask & SS_READY) - reg |= I365_CSC_READY; - } - i365_set (s, I365_CSCINT, reg); - i365_get (s, I365_CSC); -#endif /* 0 */ - -#else /* !CONFIG_CPC45 */ - - reg = I365_PWR_NORESET; - if (state->flags & SS_PWR_AUTO) - reg |= I365_PWR_AUTO; - if (state->flags & SS_OUTPUT_ENA) - reg |= I365_PWR_OUT; - - cb_set_power (s, state); - reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK); - - if (reg != i365_get (s, I365_POWER)) - i365_set (s, I365_POWER, reg); -#endif /* CONFIG_CPC45 */ - - return 0; -} /* i365_set_socket */ - -/*====================================================================*/ - -static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) -{ - u_short base, i; - u_char map; - - debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", - mem->map, mem->flags, mem->speed, - mem->sys_start, mem->sys_stop, mem->card_start); - - map = mem->map; - if ((map > 4) || - (mem->card_start > 0x3ffffff) || - (mem->sys_start > mem->sys_stop) || - (mem->speed > 1000)) { - return -1; - } - - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); - - /* Take care of high byte, for PCI controllers */ - i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); - - base = I365_MEM (map); - i = (mem->sys_start >> 12) & 0x0fff; - if (mem->flags & MAP_16BIT) - i |= I365_MEM_16BIT; - if (mem->flags & MAP_0WS) - i |= I365_MEM_0WS; - i365_set_pair (s, base + I365_W_START, i); - - i = (mem->sys_stop >> 12) & 0x0fff; - switch (mem->speed / CYCLE_TIME) { - case 0: - break; - case 1: - i |= I365_MEM_WS0; - break; - case 2: - i |= I365_MEM_WS1; - break; - default: - i |= I365_MEM_WS1 | I365_MEM_WS0; - break; - } - i365_set_pair (s, base + I365_W_STOP, i); - -#ifdef CONFIG_CPC45 - i = 0; -#else - i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff; -#endif - if (mem->flags & MAP_WRPROT) - i |= I365_MEM_WRPROT; - if (mem->flags & MAP_ATTRIB) - i |= I365_MEM_REG; - i365_set_pair (s, base + I365_W_OFF, i); - -#ifdef CONFIG_CPC45 - /* set System Memory map Upper Adress */ - i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); - i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); -#endif - - /* Turn on the window if necessary */ - if (mem->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); - return 0; -} /* i365_set_mem_map */ - -static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) -{ - u_char map, ioctl; - - map = io->map; - /* comment out: comparison is always false due to limited range of data type */ - if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ - (io->stop < io->start)) - return -1; - /* Turn off the window before changing anything */ - if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) - i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); - i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); - i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); - ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); - if (io->speed) - ioctl |= I365_IOCTL_WAIT (map); - if (io->flags & MAP_0WS) - ioctl |= I365_IOCTL_0WS (map); - if (io->flags & MAP_16BIT) - ioctl |= I365_IOCTL_16BIT (map); - if (io->flags & MAP_AUTOSZ) - ioctl |= I365_IOCTL_IOCS16 (map); - i365_set (s, I365_IOCTL, ioctl); - /* Turn on the window if necessary */ - if (io->flags & MAP_ACTIVE) - i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); - return 0; -} /* i365_set_io_map */ - -/*====================================================================*/ - -int i82365_init (void) -{ - u_int val; - int i; - -#ifdef CONFIG_CPC45 - if (SPD67290Init () != 0) - return 1; -#endif - if ((socket.dev = pci_find_devices (supported, 0)) < 0) { - /* Controller not found */ - return 1; - } - debug ("i82365 Device Found!\n"); - - pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys); - socket.cb_phys &= ~0xf; - -#ifdef CONFIG_CPC45 - /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */ - socket.cb_phys += 0xfe000000; -#endif - - get_bridge_state (&socket); - set_bridge_opts (&socket); - - i = i365_get_status (&socket, &val); - -#ifdef CONFIG_CPC45 - if (i > -1) { - puts (pcic[socket.type].name); - } else { - printf ("i82365: Controller not found.\n"); - return 1; - } - if((val & SS_DETECT) != SS_DETECT){ - puts ("No card\n"); - return 1; - } -#else /* !CONFIG_CPC45 */ - if (val & SS_DETECT) { - if (val & SS_3VCARD) { - state.Vcc = state.Vpp = 33; - puts (" 3.3V card found: "); - } else if (!(val & SS_XVCARD)) { - state.Vcc = state.Vpp = 50; - puts (" 5.0V card found: "); - } else { - puts ("i82365: unsupported voltage key\n"); - state.Vcc = state.Vpp = 0; - } - } else { - /* No card inserted */ - puts ("No card\n"); - return 1; - } -#endif /* CONFIG_CPC45 */ - -#ifdef CONFIG_CPC45 - state.flags |= SS_OUTPUT_ENA; -#else - state.flags = SS_IOCARD | SS_OUTPUT_ENA; - state.csc_mask = 0; - state.io_irq = 0; -#endif - - i365_set_socket (&socket, &state); - - for (i = 500; i; i--) { - if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) - break; - udelay (1000); - } - - if (i == 0) { - /* PC Card not ready for data transfer */ - puts ("i82365 PC Card not ready for data transfer\n"); - return 1; - } - debug (" PC Card ready for data transfer: "); - - mem.map = 0; - mem.flags = MAP_ATTRIB | MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - -#ifdef CONFIG_CPC45 - mem.map = 1; - mem.flags = MAP_ACTIVE; - mem.speed = 300; - mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE; - mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1; - mem.card_start = 0; - i365_set_mem_map (&socket, &mem); - -#else /* !CONFIG_CPC45 */ - - io.map = 0; - io.flags = MAP_AUTOSZ | MAP_ACTIVE; - io.speed = 0; - io.start = 0x0100; - io.stop = 0x010F; - i365_set_io_map (&socket, &io); - -#endif /* CONFIG_CPC45 */ - -#ifdef DEBUG - i82365_dump_regions (socket.dev); -#endif - - return 0; -} - -void i82365_exit (void) -{ - io.map = 0; - io.flags = 0; - io.speed = 0; - io.start = 0; - io.stop = 0x1; - - i365_set_io_map (&socket, &io); - - mem.map = 0; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); - -#ifdef CONFIG_CPC45 - mem.map = 1; - mem.flags = 0; - mem.speed = 0; - mem.sys_start = 0; - mem.sys_stop = 0x1000; - mem.card_start = 0; - - i365_set_mem_map (&socket, &mem); -#else /* !CONFIG_CPC45 */ - socket.state.sysctl &= 0xFFFF00FF; -#endif - state.Vcc = state.Vpp = 0; - - i365_set_socket (&socket, &state); -} - -/*====================================================================== - - Debug stuff - -======================================================================*/ - -#ifdef DEBUG -static void i82365_dump_regions (pci_dev_t dev) -{ - u_int tmp[2]; - u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); - - pci_read_config_dword (dev, 0x00, tmp + 0); - pci_read_config_dword (dev, 0x80, tmp + 1); - - printf ("PCI CONF: %08X ... %08X\n", - tmp[0], tmp[1]); - printf ("PCI MEM: ... %08X ... %08X\n", - mem[0x8 / 4], mem[0x800 / 4]); - printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", - cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], - cis[0x40], cis[0x42], cis[0x44], cis[0x48]); - printf ("CIS CONF: %02X %02X %02X ...\n", - cis[0x200], cis[0x202], cis[0x204]); - printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", - ide[0], ide[1], ide[2], ide[3], - ide[4], ide[5], ide[6], ide[7]); -} -#endif /* DEBUG */ diff --git a/include/configs/A3000.h b/include/configs/A3000.h deleted file mode 100644 index 35e3e6f..0000000 --- a/include/configs/A3000.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * (C) Copyright 2001, 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ -/* - * Configuration settings for the A-3000 board (Artis Microsystems Inc.). - * http://artismicro.com - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_A3000 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - - -/* #define CONFIG_TULIP */ -/* #define CONFIG_EEPRO100 */ -#define CONFIG_NATSEMI - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET2_MEMADDR 0x82000000 -#define PCI_ENET3_IOADDR 0x83000000 -#define PCI_ENET3_MEMADDR 0x83000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM -#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM } - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h deleted file mode 100644 index a75c52f..0000000 --- a/include/configs/CPC45.h +++ /dev/null @@ -1,489 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the CPC45 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_CPC45 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#define CONFIG_BOOTDELAY 5 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#else -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) -#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 - - -/* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 8 - -#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ -#define CONFIG_SYS_BANK1_ROW 0 -#define CONFIG_SYS_BANK2_ROW 0 -#define CONFIG_SYS_BANK3_ROW 0 -#define CONFIG_SYS_BANK4_ROW 0 -#define CONFIG_SYS_BANK5_ROW 0 -#define CONFIG_SYS_BANK6_ROW 0 -#define CONFIG_SYS_BANK7_ROW 0 - -/* Bit-field values for MCCR2. - */ - -#define CONFIG_SYS_REFINT 0x2ec - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 160 - -/* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */ - -/* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 0 -#define CONFIG_SYS_REGDIMM 0 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ -#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warining: environment is not EMBEDDED in the ppcboot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000) -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------*/ -/* CPC45 Memory Map */ -/*----------------------------------------------------------------------*/ -#define SRAM_BASE 0x80000000 /* SRAM base address */ -#define SRAM_END 0x801FFFFF -#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ -#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ -#define BCSR_BASE 0x80600000 /* board control / status registers */ -#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ -#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ -#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ - -#define CONFIG_SYS_SRAM_BASE SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1) - -/*---------------------------------------------------------------------*/ -/* CPC45 Control/Status Registers */ -/*---------------------------------------------------------------------*/ -#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) -#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) -#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) -#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) -#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) -#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) -#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) -#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) -#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) -#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) - -/* IRQ_ENA_1 bit definitions */ -#define I_ENA_1_IERA 0x80 /* INTA enable */ -#define I_ENA_1_IERB 0x40 /* INTB enable */ -#define I_ENA_1_IERC 0x20 /* INTC enable */ -#define I_ENA_1_IERD 0x10 /* INTD enable */ - -/* IRQ_STAT_1 bit definitions */ -#define I_STAT_1_INTA 0x80 /* INTA status */ -#define I_STAT_1_INTB 0x40 /* INTB status */ -#define I_STAT_1_INTC 0x20 /* INTC status */ -#define I_STAT_1_INTD 0x10 /* INTD status */ - -/* IRQ_ENA_2 bit definitions */ -#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ -#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ -#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ -#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ -#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ -#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ -#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ -#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ - -/* IRQ_STAT_2 bit definitions */ -#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ -#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ -#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ -#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ -#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ -#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ -#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ -#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ - -/* BOARD_CTRL bit definitions */ -#define USER_LEDS 2 /* 2 user LEDs */ - -#if (USER_LEDS == 4) -#define B_CTRL_WRSE 0x80 -#define B_CTRL_KRSE 0x40 -#define B_CTRL_FWRE 0x20 /* Flash write enable */ -#define B_CTRL_FWPT 0x10 /* Flash write protect */ -#define B_CTRL_LED3 0x08 /* LED 3 control */ -#define B_CTRL_LED2 0x04 /* LED 2 control */ -#define B_CTRL_LED1 0x02 /* LED 1 control */ -#define B_CTRL_LED0 0x01 /* LED 0 control */ -#else -#define B_CTRL_WRSE 0x80 -#define B_CTRL_KRSE 0x40 -#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ -#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ -#define B_CTRL_LED1 0x08 /* LED 1 control */ -#define B_CTRL_LED0 0x04 /* LED 0 control */ -#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ -#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ -#endif - -/* BOARD_STAT bit definitions */ -#define B_STAT_WDGE 0x80 -#define B_STAT_WDGS 0x40 -#define B_STAT_WRST 0x20 -#define B_STAT_KRST 0x10 -#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ -#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ -#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ -#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ -#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ -#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ -#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ - -#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ -#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ - -#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ -#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ -#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ -#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ -#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ -#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ -#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ -#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_EARLY_PCI_INIT -#undef CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x82000000 -#define PCI_ENET0_MEMADDR 0x82000000 -#define PCI_PLX9030_IOADDR 0x82100000 -#define PCI_PLX9030_MEMADDR 0x82100000 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_I82365 - -#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 - -#define CONFIG_PCMCIA_SLOT_A - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for IDE not supported */ -#define CONFIG_IDE_LED /* LED for IDE is supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400) - -#define CONFIG_DOS_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/CU824.h b/include/configs/CU824.h deleted file mode 100644 index dc98a56..0000000 --- a/include/configs/CU824.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the CU824 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8240 1 -#define CONFIG_CU824 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 4 - -#define CONFIG_SYS_NS16550_CLK (14745600 / 2) - -#define CONFIG_SYS_NS16550_COM1 0xFE800080 -#define CONFIG_SYS_NS16550_COM2 0xFE8000C0 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 7 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_REFINT 430 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 192 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 2 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if 0 -#define CONFIG_ENV_ADDR 0xFF008000 -#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ -#else -#define CONFIG_ENV_ADDR 0xFFFC0000 -#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP -#define CONFIG_TULIP_USE_IO - -#define CONFIG_SYS_ETH_DEV_FN 0x7800 -#define CONFIG_SYS_ETH_IOBASE 0x00104000 - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define PCI_ENET0_IOADDR 0x00104000 -#define PCI_ENET0_MEMADDR 0x80000000 -#endif /* __CONFIG_H */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h deleted file mode 100644 index c5c9290..0000000 --- a/include/configs/MUSENKI.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the MUSENKI board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_MUSENKI 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFF0000 -#define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h deleted file mode 100644 index aa2d9c0..0000000 --- a/include/configs/MVBLUE.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define MV_VERSION "v0.2.0" - -/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ -#define ERR_NONE 0 -#define ERR_ENV 1 -#define ERR_BOOTM_BADMAGIC 2 -#define ERR_BOOTM_BADCRC 3 -#define ERR_BOOTM_GUNZIP 4 -#define ERR_BOOTP_TIMEOUT 5 -#define ERR_DHCP 6 -#define ERR_TFTP 7 -#define ERR_NOLAN 8 -#define ERR_LANDRV 9 - -#define CONFIG_BOARD_TYPES 1 -#define MVBLUE_BOARD_BOX 1 -#define MVBLUE_BOARD_LYNX 2 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds" - -#if 0 -#define ERR_LED(code) do { if (code) \ - *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ - else \ - *(volatile char *)(0xff000003) = ( 1 ); \ -} while(0) -#else -#define ERR_LED(code) -#endif - -#define CONFIG_MPC8245 1 -#define CONFIG_MVBLUE 1 - -#define CONFIG_CLOCKS_IN_MHZ 1 - -#define CONFIG_BOARD_TYPES 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOT_RETRY_TIME -1 - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds (stop with 's')...\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 60 - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_RUN - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -#define CONFIG_BOOTCOMMAND "run nfsboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" - -#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "dhcp_client_id=mvBOX-XP\0" \ - "dhcp_vendor-class-identifier=mvBOX\0" \ - "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \ - "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \ - "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \ - "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \ - "mv_version=" MV_VERSION "\0" \ - "bootretry=30\0" - -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_TULIP -#define CONFIG_TULIP_FIX_DAVICOM 1 -#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 - -#define CONFIG_HW_WATCHDOG - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_LEN 0x00100000 -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ - -/* Maximum amount of RAM. */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_ISA_IO 0xFE000000 - -/* - * serial configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 - -/* Bit-field values for MCCR1. */ -#define CONFIG_SYS_ROMNAL 7 -#define CONFIG_SYS_ROMFAL 11 - -/* Bit-field values for MCCR2. */ -#define CONFIG_SYS_TSWAIT 0x5 -#define CONFIG_SYS_REFINT 430 - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CONFIG_SYS_BSTOPRE 121 - -/* Bit-field values for MCCR3. */ -#define CONFIG_SYS_REFREC 8 - -/* Bit-field values for MCCR4. */ -#define CONFIG_SYS_PRETOACT 3 -#define CONFIG_SYS_ACTTOPRE 5 -#define CONFIG_SYS_ACTORW 3 -#define CONFIG_SYS_SDMODE_CAS_LAT 3 -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 -#define CONFIG_SYS_DBUS_SIZE2 1 -#define CONFIG_SYS_SDMODE_WRAP 0 - -#define CONFIG_SYS_PGMAX 0x32 -#define CONFIG_SYS_SDRAM_DSCD 0x20 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - - -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_OFFSET 0x00010000 -#define CONFIG_ENV_SIZE 0x00010000 -#define CONFIG_ENV_SECT_SIZE 0x00010000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h deleted file mode 100644 index 2c0cb89..0000000 --- a/include/configs/Sandpoint8240.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8240 1 -#define CONFIG_SANDPOINT 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "net_self=tftp ${kernel_addr} ${bootfile};" \ - "tftp ${ramdisk_addr} ${ramdisk};" \ - "run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp ${kernel_addr} ${bootfile};" \ - "run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/SP8240/uImage\0" \ - "ramdisk=/tftpboot/SP8240/uRamdisk\0" \ - "kernel_addr=200000\0" \ - "ramdisk_addr=400000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if 0 -#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SPEED 400000 - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ - - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ -#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CONFIG_SYS_NS87308_BADDR_10 1 - -#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ - CONFIG_SYS_NS87308_UART2 | \ - CONFIG_SYS_NS87308_POWRMAN | \ - CONFIG_SYS_NS87308_RTC_APC ) - -#undef CONFIG_SYS_NS87308_PS2MOD - -#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 -#define CONFIG_SYS_NS87308_CS0_CONF 0x30 -#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 -#define CONFIG_SYS_NS87308_CS1_CONF 0x30 -#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 -#define CONFIG_SYS_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 1843200 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 - -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h deleted file mode 100644 index 2664d5b..0000000 --- a/include/configs/Sandpoint8245.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_SANDPOINT 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NATSEMI -#define CONFIG_NS8382X - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE 0x00090000 -#define CONFIG_SYS_RAMBOOT 1 -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if 0 -#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_ISA_MEM 0xFD000000 -#define CONFIG_SYS_ISA_IO 0xFE000000 - -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -#ifdef CONFIG_SYS_I2C_SOFT -#error "Soft I2C is not configured properly. Please review!" -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SYS_I2C_SOFT */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ -#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CONFIG_SYS_NS87308_BADDR_10 1 - -#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ - CONFIG_SYS_NS87308_UART2 | \ - CONFIG_SYS_NS87308_POWRMAN | \ - CONFIG_SYS_NS87308_RTC_APC ) - -#undef CONFIG_SYS_NS87308_PS2MOD - -#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 -#define CONFIG_SYS_NS87308_CS0_CONF 0x30 -#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 -#define CONFIG_SYS_NS87308_CS1_CONF 0x30 -#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 -#define CONFIG_SYS_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX > 2) -#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CONFIG_SYS_NS16550_CLK 1843200 -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 1 -#define CONFIG_SYS_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h deleted file mode 100644 index 940be1f..0000000 --- a/include/configs/eXalion.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define CONFIG_MPC8240 1 */ -#define CONFIG_MPC8245 1 -#define CONFIG_EXALION 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#if defined (CONFIG_MPC8240) - /* #warning ---------- eXalion with MPC8240 --------------- */ -#elif defined (CONFIG_MPC8245) - /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ -#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) -#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) -#else -#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -/* older kernels need clock in MHz newer in Hz */ - /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_BOOTDELAY 10 - - - /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_PCI - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CONFIG_MISC_INIT_R 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ - /* return real value. */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_DATA_SIZE 128 - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 -#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ -#elif defined (CONFIG_MPC8245) -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for environment */ -#define CONFIG_ENV_ADDR 0xFFFC0000 -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -/* #define CONFIG_SYS_ISA_MEM 0xFD000000 */ -#define CONFIG_SYS_ISA_IO 0xFE000000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE -#define FLASH_BASE1_PRELIM 0 - - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI 1 /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_EEPRO100 1 - -#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ -#define PCI_ENET3_IOADDR 0x83000000 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1) -#define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */ -#else -#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ - - /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ - -#if defined (CONFIG_MPC8245) -/* Bit-field values for PMCR2. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ -#define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ -#endif - -/* Bit-field values for MIOCR1. */ -#if !defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ -#endif -/* Bit-field values for MIOCR2. */ -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ - /* - note bottom 3 bits MUST be 0 */ -#endif - -/* Bit-field values for MCCR1. */ -#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ - -/* Bit-field values for MCCR2. */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */ -#else /* refresh cycles */ -#define CONFIG_SYS_REFINT 750 -#endif - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_BSTOPRE 1023 -#else -#define CONFIG_SYS_BSTOPRE 250 -#endif - -/* Bit-field values for MCCR3. */ -/* the following are for SDRAM only */ - -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */ -#else -#define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */ -#endif -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_RDLAT 2 /* data latency from read command */ -#endif - -/* Bit-field values for MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 5 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#else -#if 0 -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#endif -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#endif -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CONFIG_SYS_REGDIMM 0 -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0 -#elif defined (CONFIG_MPC8245) -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 0 -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - -/*----------------------------------------------------------------------- - memory bank settings - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 - -/*----------------------------------------------------------------------- - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#if defined (CONFIG_MPC8240) -#define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#elif defined (CONFIG_MPC8245) -#if defined (CONFIG_133MHZ_DRAM) -#define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */ -#else -#define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */ -#endif -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/*----------------------------------------------------------------------- - * Block Address Translation (BAT) register settings. - */ -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* values according to the manual */ -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#define CONFIG_ATAPI - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide supported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ - -/*----------------------------------------------------------------------- - * DISK Partition support - */ -#define CONFIG_DOS_PARTITION - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h deleted file mode 100644 index 5be62ec..0000000 --- a/include/configs/utx8245.h +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * Configuration settings for the utx8245 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8245 1 -#define CONFIG_UTX8245 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define DEBUG 1 - -#define CONFIG_IDENT_STRING " [UTX5] " - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 57600 - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ -#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ -#define CONFIG_SERVERIP 10.8.17.105 /* Spree */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=FFA00000\0" \ - "ramdisk_addr=FF800000\0" \ - "u-boot_startaddr=FFB00000\0" \ - "u-boot_endaddr=FFB2FFFF\0" \ - "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \ -nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \ - "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \ - "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \ - "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \ - "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \ - "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \ -${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \ -${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\ -protect on ${u-boot_startaddr} ${u-boot_endaddr}" - -#define CONFIG_ENV_OVERWRITE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_PCI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_IMI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - - -/*----------------------------------------------------------------------- - * PCI configuration - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#define PCI_ENET0_IOADDR 0xF0000000 -#define PCI_ENET0_MEMADDR 0xF0000000 - -#define PCI_FIREWIRE_IOADDR 0xF1000000 -#define PCI_FIREWIRE_MEMADDR 0xF1000000 -/* -#define PCI_ENET0_IOADDR 0xFE000000 -#define PCI_ENET0_MEMADDR 0x80000000 - -#define PCI_FIREWIRE_IOADDR 0x81000000 -#define PCI_FIREWIRE_MEMADDR 0x81000000 -*/ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */ -/*#define CONFIG_SYS_VERY_BIG_RAM 1 */ - -/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector - * is actually located at FFF00100. Therefore, U-Boot is - * physically located at 0xFFB0_0000, but is also mirrored at - * 0xFFF0_0000. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*#define CONFIG_SYS_DRAM_TEST 1 */ -#define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ -#define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ - /* vectors and U-Boot */ - - -/*-------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - *------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ - /* initial data */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/*-------------------------------------------------------------------- - * NS16550 Configuration - *------------------------------------------------------------------*/ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) -# define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#else -# define CONFIG_SYS_NS16550_CLK 33000000 -#endif - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) -#define CONFIG_SYS_NS16550_COM3 0xFF000000 -#define CONFIG_SYS_NS16550_COM4 0xFF000008 - -/*-------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - *------------------------------------------------------------------*/ - -#define CONFIG_SYS_CLK_FREQ 33000000 - -/*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */ -/*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */ - -/*-------------------------------------------------------------------- - * I2C Configuration - *------------------------------------------------------------------*/ -#if 1 -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#endif - -#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ - /* Philips PCF8563 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ - -/*-------------------------------------------------------------------- - * Memory Control Configuration Register values - * - see sec. 4.12 of MPC8245 UM - *------------------------------------------------------------------*/ - -/**** MCCR1 ****/ -#define CONFIG_SYS_ROMNAL 0 -#define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, - mem_freq = 100MHz */ - -#define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ -#define CONFIG_SYS_BANK6_ROW 0 /* bit count */ -#define CONFIG_SYS_BANK5_ROW 0 -#define CONFIG_SYS_BANK4_ROW 0 -#define CONFIG_SYS_BANK3_ROW 0 -#define CONFIG_SYS_BANK2_ROW 0 -#define CONFIG_SYS_BANK1_ROW 2 -#define CONFIG_SYS_BANK0_ROW 2 - -/**** MCCR2, refresh interval clock cycles ****/ -#define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */ - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */ - /* sets open page interval */ - -/**** MCCR3 ****/ -#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */ - -/**** MCCR4 ****/ -#define CONFIG_SYS_PRETOACT 2 /* trp */ -#define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ -#define CONFIG_SYS_ACTORW 2 /* trcd min */ -#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 -#define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */ -#define CONFIG_SYS_REGDIMM 0 - -/* calculate according to formula in sec. 6-22 of 8245 UM */ -#define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */ - /* currently accessed page in memory */ - /* was 45 */ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ - /* bits 7,6, and 3-0 MUST be 0 */ - -#if 0 -#define CONFIG_SYS_DLL_MAX_DELAY 0x04 -#else -#define CONFIG_SYS_DLL_MAX_DELAY 0 -#endif -#if 0 /* need for 33MHz SDRAM */ -#define CONFIG_SYS_DLL_EXTEND 0x80 -#else -#define CONFIG_SYS_DLL_EXTEND 0 -#endif -#define CONFIG_SYS_PCI_HOLD_DEL 0x20 - - -/* Memory bank settings. - * Only bits 20-29 are actually used from these values to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8245 user manual. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2 -#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK1_ENABLE 1 -#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */ -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -/*--------------------------------------------------------------------*/ -/* 4.4 - Output Driver Control Register */ -/*--------------------------------------------------------------------*/ -#define CONFIG_SYS_ODCR 0xe5 - -/*--------------------------------------------------------------------*/ -/* 4.8 - Error Handling Registers */ -/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/ -#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ - -/* SDRAM 0-256 MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -/*#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */ -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in dcache */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - - -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) - -/* PCI memory */ -/*#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */ -/*#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */ - -/*Flash, config addrs, etc. */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ - -/* NOTE: environment is not EMBEDDED in the u-boot code. - It's stored in flash in its own separate sector. */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#if 1 /* AMD AM29LV033C */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ -#define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ -#define CONFIG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ -#else /* AMD AM29LV116D */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ -#define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ -#define CONFIG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ -#endif /* #if */ - -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/mpc824x.h b/include/mpc824x.h deleted file mode 100644 index 31d6f69..0000000 --- a/include/mpc824x.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000. - * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MPC824X_H__ -#define __MPC824X_H__ - -#include <config.h> - -/* CPU Types */ -#define CPU_TYPE_601 0x01 /* PPC 601 CPU */ -#define CPU_TYPE_602 0x02 /* PPC 602 CPU */ -#define CPU_TYPE_603 0x03 /* PPC 603 CPU */ -#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */ -#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */ -#define CPU_TYPE_604 0x04 /* PPC 604 CPU */ -#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */ -#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */ -#define CPU_TYPE_750 0x08 /* PPC 750 CPU */ -#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */ -#define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */ -#define _CACHE_ALIGN_SIZE 32 /* cache line size */ - -/* spr976 - DMISS data tlb miss address register - * spr977 - DCMP data tlb miss compare register - * spr978 - HASH1 PTEG1 address register - * spr980 - HASH2 PTEG2 address register - * IMISS - instruction tlb miss address register - * ICMP - instruction TLB mis compare register - * RPA - real page address register - * HID0 - hardware implemntation register - * HID2 - instruction address breakpoint register - */ - -/* Kahlua/MPC8240 defines */ -#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */ -#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */ -#define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */ -#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */ -#define CHRP_ISA_MEM_PHYS 0xfd000000 -#define CHRP_ISA_MEM_BUS 0x00000000 -#define CHRP_ISA_MEM_SIZE 0x01000000 -#define CHRP_ISA_IO_PHYS 0xfe000000 -#define CHRP_ISA_IO_BUS 0x00000000 -#define CHRP_ISA_IO_SIZE 0x00800000 -#define CHRP_PCI_IO_PHYS 0xfe800000 -#define CHRP_PCI_IO_BUS 0x00800000 -#define CHRP_PCI_IO_SIZE 0x00400000 -#define CHRP_PCI_MEM_PHYS 0x80000000 -#define CHRP_PCI_MEM_BUS 0x80000000 -#define CHRP_PCI_MEM_SIZE 0x7d000000 -#define CHRP_PCI_MEMORY_PHYS 0x00000000 -#define CHRP_PCI_MEMORY_BUS 0x00000000 -#define CHRP_PCI_MEMORY_SIZE 0x40000000 -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -#define PREP_ISA_IO_PHYS 0x80000000 -#define PREP_ISA_IO_BUS 0x00000000 -#define PREP_ISA_IO_SIZE 0x00800000 -#define PREP_PCI_IO_PHYS 0x81000000 -#define PREP_PCI_IO_BUS 0x01000000 -#define PREP_PCI_IO_SIZE 0x3e800000 -#define PREP_PCI_MEM_PHYS 0xc0000000 -#define PREP_PCI_MEM_BUS 0x00000000 -#define PREP_PCI_MEM_SIZE 0x3f000000 -#define PREP_PCI_MEMORY_PHYS 0x00000000 -#define PREP_PCI_MEMORY_BUS 0x80000000 -#define PREP_PCI_MEMORY_SIZE 0x80000000 -#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ -#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ -#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ -#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ -#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ -#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */ -#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */ -#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */ -#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ -#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ -#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ -#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ -#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ -#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ -#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ -#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ -#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/ -#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */ -#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */ -#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */ - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_RESERVED0 0x0000 /* Reserved */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */ -#define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */ -#define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */ -#define EXC_OFF_EXTERNAL 0x0500 /* External */ -#define EXC_OFF_ALIGN 0x0600 /* Alignment */ -#define EXC_OFF_PROGRAM 0x0700 /* Program */ -#define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */ -#define EXC_OFF_DECR 0x0900 /* Decrementer */ -#define EXC_OFF_RESERVED1 0x0A00 /* Reserved */ -#define EXC_OFF_RESERVED2 0x0B00 /* Reserved */ -#define EXC_OFF_SYS_CALL 0x0C00 /* System Call */ -#define EXC_OFF_TRACE 0x0D00 /* Trace */ -#define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */ - - /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */ - /* these found in DINK code - may not apply to 8240*/ -#define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */ -#define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */ - - /* 0x1000 - 0x2FFF are implementation specific */ - /* these found in DINK code - may not apply to 8240 */ -#define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */ -#define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */ -#define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */ -#define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */ -#define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */ -#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ -#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ - -#define _START_OFFSET EXC_OFF_SYS_RESET - -#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ -#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ -#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ -#define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */ -#define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */ -#define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */ -#define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */ -#define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */ - - -#if defined(CONFIG_SYS_ADDR_MAP_A) -#define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ -#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ -#define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ -#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ -#else /* Assume Map B, default */ -#define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ -#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ -#define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ -#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ -#endif - -#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW) - -#define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW) - -/* Macros to write to config registers. addr should be a constant in all cases */ - -#define CONFIG_WRITE_BYTE( addr, data ) \ - __asm__ __volatile__( \ - " stwbrx %1, 0, %0\n \ - sync\n \ - stb %3, %4(%2)\n \ - sync " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ - "b" (CONFIG_DATA), "r" (data), \ - "n" ((addr) & 3)); - -#define CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__( \ - " stwbrx %1, 0, %0\n \ - sync\n \ - sthbrx %3, %4, %2\n \ - sync " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ - "r" (CONFIG_DATA), "r" (data), \ - "b" ((addr) & 3)); - -/* this assumes it's writeing on word boundaries*/ -#define CONFIG_WRITE_WORD( addr, data ) \ - __asm__ __volatile__( \ - " stwbrx %1, 0, %0\n \ - sync\n \ - stwbrx %3, 0, %2\n \ - sync " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (addr), \ - "r" (CONFIG_DATA), "r" (data)); - -/* Configuration register reads*/ - -#define CONFIG_READ_BYTE( addr, reg ) \ - __asm__ ( \ - " stwbrx %1, 0, %2\n \ - sync\n \ - lbz %0, %4(%3)\n \ - sync " \ - : "=r" (reg) \ - : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ - "b" (CONFIG_DATA), "n" ((addr) & 3)); - - -#define CONFIG_READ_HALFWORD( addr, reg ) \ - __asm__ ( \ - " stwbrx %1, 0, %2\n \ - sync\n \ - lhbrx %0, %4, %3\n \ - sync " \ - : "=r" (reg) \ - : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ - "r" (CONFIG_DATA), \ - "b" ((addr) & 3)); - -/* this assumes it's reading on word boundaries*/ -#define CONFIG_READ_WORD( addr, reg ) \ - __asm__ ( \ - " stwbrx %1, 0, %2\n \ - sync\n \ - lwbrx %0, 0, %3\n \ - sync " \ - : "=r" (reg) \ - : "r" (addr), "r" (CONFIG_ADDR),\ - "r" (CONFIG_DATA)); - -/* - * configuration register 'addresses'. - * These are described in chaper 5 of the 8240 users manual. - * Where the register has an abreviation in the manual, this has - * been usaed here, otherwise a name in keeping with the norm has - * been invented. - * Note that some of these registers aren't documented in the manual. - */ - -#define PCICR 0x80000004 /* PCI Command Register */ -#define PCISR 0x80000006 /* PCI Status Register */ -#define REVID 0x80000008 /* CPU revision id */ -#define PIR 0x80000009 /* PCI Programming Interface Register */ -#define PBCCR 0x8000000b /* PCI Base Class Code Register */ -#define PCLSR 0x8000000c /* Processor Cache Line Size Register */ -#define PLTR 0x8000000d /* PCI Latancy Timer Register */ -#define PHTR 0x8000000e /* PCI Header Type Register */ -#define BISTCTRL 0x8000000f /* BIST Control */ -#define LMBAR 0x80000010 /* Local Base Address Register */ -#define PCSRBAR 0x80000014 /* PCSR Base Address Register */ -#define ILR 0x8000003c /* PCI Interrupt Line Register */ -#define IPR 0x8000003d /* Interrupt Pin Register */ -#define MINGNT 0x8000003e /* MIN GNI */ -#define MAXLAT 0x8000003f /* MAX LAT */ -#define PCIACR 0x80000046 /* PCI Arbiter Control Register */ -#define PMCR1 0x80000070 /* Power management config. 1 */ -#define PMCR2 0x80000072 /* Power management config. 2 */ -#define ODCR 0x80000073 /* Output Driver Control Register */ -#define CLKDCR 0x80000074 /* CLK Driver Control Register */ -#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ -#endif -#define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */ -#define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */ -#define EUMBSIZE 0x00100000 /* Size of EUMB region */ - -#define MSAR1 0x80000080 /* Memory Starting Address Register 1 */ -#define MSAR2 0x80000084 /* Memory Starting Address Register 2 */ -#define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/ -#define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/ -#define MEAR1 0x80000090 /* Memory Ending Address Register 1 */ -#define MEAR2 0x80000094 /* Memory Ending Address Register 2 */ -#define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */ -#define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */ -#define MBER 0x800000a0 /* Memory bank Enable Register*/ -#define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */ -#define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */ -#define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */ -#define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */ -#define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */ -#define ERRENR1 0x800000c0 /* Error Enableing Register 1 */ -#define ERRENR2 0x800000c4 /* Error Enableing Register 2 */ -#define ERRDR1 0x800000c1 /* Error Detection Register 1 */ -#define IPBESR 0x800000c3 /* Internal Processor Error Status Register */ -#define ERRDR2 0x800000c5 /* Error Detection Register 2 */ -#define PBESR 0x800000c7 /* PCI Bus Error Status Register */ -#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */ -#define AMBOR 0x800000e0 /* Address Map B Options Register */ -#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */ -#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */ -#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */ -#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */ -#define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */ - -/* some values for some of the above */ - -#define PICR1_CF_APARK 0x00000008 -#define PICR1_LE_MODE 0x00000020 -#define PICR1_ST_GATH_EN 0x00000040 -#if defined(CONFIG_MPC8240) -#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */ -#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */ -#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */ -#define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */ -#define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */ -#define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */ -#define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */ -#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR1_SHIFT 2 -#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ -#define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ -#define MIOCR2_SHIFT 3 -#define ODCR_ADR_X 0x80000070 /* Output Driver Control register */ -#define ODCR_SHIFT 3 -#define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */ -#define PMCR2_ADR_X 0x80000070 -#define PMCR2_SHIFT 3 -#define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -#define PICR1_CF_DPARK 0x00000200 -#define PICR1_MCP_EN 0x00000800 -#define PICR1_FLASH_WR_EN 0x00001000 -#ifdef CONFIG_MPC8240 -#define PICR1_ADDRESS_MAP 0x00010000 -#define PIRC1_MSK 0xff000000 -#endif -#define PICR1_PROC_TYPE_MSK 0x00060000 -#define PICR1_PROC_TYPE_603E 0x00040000 -#define PICR1_RCS0 0x00100000 - -#define PICR2_CF_SNOOP_WS_MASK 0x000c0000 -#define PICR2_CF_SNOOP_WS_0WS 0x00000000 -#define PICR2_CF_SNOOP_WS_1WS 0x00040000 -#define PICR2_CF_SNOOP_WS_2WS 0x00080000 -#define PICR2_CF_SNOOP_WS_3WS 0x000c0000 -#define PICR2_CF_APHASE_WS_MASK 0x0000000c -#define PICR2_CF_APHASE_WS_0WS 0x00000000 -#define PICR2_CF_APHASE_WS_1WS 0x00000004 -#define PICR2_CF_APHASE_WS_2WS 0x00000008 -#define PICR2_CF_APHASE_WS_3WS 0x0000000c - -#define MCCR1_ROMNAL_SHIFT 28 -#define MCCR1_ROMNAL_MSK 0xf0000000 -#define MCCR1_ROMFAL_SHIFT 23 -#define MCCR1_ROMFAL_MSK 0x0f800000 -#define MCCR1_DBUS_SIZE0 0x00400000 -#define MCCR1_BURST 0x00100000 -#define MCCR1_MEMGO 0x00080000 -#define MCCR1_SREN 0x00040000 -#if defined(CONFIG_MPC8240) -#define MCCR1_RAM_TYPE 0x00020000 -#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define MCCR1_SDRAM_EN 0x00020000 -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -#define MCCR1_PCKEN 0x00010000 -#define MCCR1_BANK1ROW_SHIFT 2 -#define MCCR1_BANK2ROW_SHIFT 4 -#define MCCR1_BANK3ROW_SHIFT 6 -#define MCCR1_BANK4ROW_SHIFT 8 -#define MCCR1_BANK5ROW_SHIFT 10 -#define MCCR1_BANK6ROW_SHIFT 12 -#define MCCR1_BANK7ROW_SHIFT 14 - -#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000 -#define MCCR2_TS_WAIT_TIMER_SHIFT 29 -#define MCCR2_ASRISE_MSK 0x1e000000 -#define MCCR2_ASRISE_SHIFT 25 -#define MCCR2_ASFALL_MSK 0x01e00000 -#define MCCR2_ASFALL_SHIFT 21 - -#define MCCR2_INLINE_PAR_NOT_ECC 0x00100000 -#define MCCR2_WRITE_PARITY_CHK 0x00080000 -#define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000 -#ifdef CONFIG_MPC8240 -#define MCCR2_ECC_EN 0x00020000 -#define MCCR2_EDO 0x00010000 -#endif -#define MCCR2_REFINT_MSK 0x0000fffc -#define MCCR2_REFINT_SHIFT 2 -#define MCCR2_RSV_PG 0x00000002 -#define MCCR2_PMW_PAR 0x00000001 - -#define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/ -#define MCCR3_BSTOPRE2TO5_SHIFT 28 -#define MCCR3_REFREC_MSK 0x0f000000 -#define MCCR3_REFREC_SHIFT 24 -#ifdef CONFIG_MPC8240 -#define MCCR3_RDLAT_MSK 0x00f00000 -#define MCCR3_RDLAT_SHIFT 20 -#define MCCR3_CPX 0x00010000 -#define MCCR3_RAS6P_MSK 0x00078000 -#define MCCR3_RAS6P_SHIFT 15 -#define MCCR3_CAS5_MSK 0x00007000 -#define MCCR3_CAS5_SHIFT 12 -#define MCCR3_CP4_MSK 0x00000e00 -#define MCCR3_CP4_SHIFT 9 -#define MCCR3_CAS3_MSK 0x000001c0 -#define MCCR3_CAS3_SHIFT 6 -#define MCCR3_RCD2_MSK 0x00000038 -#define MCCR3_RCD2_SHIFT 3 -#define MCCR3_RP1_MSK 0x00000007 -#define MCCR3_RP1_SHIFT 0 -#endif - -#define MCCR4_PRETOACT_MSK 0xf0000000 -#define MCCR4_PRETOACT_SHIFT 28 -#define MCCR4_ACTTOPRE_MSK 0x0f000000 -#define MCCR4_ACTTOPRE_SHIFT 24 -#define MCCR4_WMODE 0x00800000 -#define MCCR4_INLINE 0x00400000 -#if defined(CONFIG_MPC8240) -#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/ -#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) -#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -#define MCCR4_REGISTERED 0x00100000 -#define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/ -#define MCCR4_BSTOPRE0TO1_SHIFT 18 -#define MCCR4_REGDIMM 0x00008000 -#define MCCR4_SDMODE_MSK 0x00007f00 -#define MCCR4_SDMODE_SHIFT 8 -#define MCCR4_ACTTORW_MSK 0x000000f0 -#define MCCR4_ACTTORW_SHIFT 4 -#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/ -#define MCCR4_BSTOPRE6TO9_SHIFT 0 -#define MCCR4_DBUS_SIZE2_SHIFT 17 - -#define MICR_ADDR_MASK 0x0ff00000 -#define MICR_ADDR_SHIFT 20 -#define MICR_EADDR_MASK 0x30000000 -#define MICR_EADDR_SHIFT 28 - -/*eumb and epic config*/ - -#define EPIC_FPR 0x00041000 -#define EPIC_GCR 0x00041020 -#define EPIC_EICR 0x00041030 -#define EPIC_EVI 0x00041080 -#define EPIC_PI 0x00041090 -#define EPIC_SVR 0x000410E0 -#define EPIC_TFRR 0x000410F0 - -/* - * Note the information for these is rather mangled in the 8240 manual. - * These are guesses. - */ - -#define EPIC_GTCCR0 0x00041100 -#define EPIC_GTCCR1 0x00041140 -#define EPIC_GTCCR2 0x00041180 -#define EPIC_GTCCR3 0x000411C0 -#define EPIC_GTBCR0 0x00041110 -#define EPIC_GTBCR1 0x00041150 -#define EPIC_GTBCR2 0x00041190 -#define EPIC_GTBCR3 0x000411D0 -#define EPIC_GTVPR0 0x00041120 -#define EPIC_GTVPR1 0x00041160 -#define EPIC_GTVPR2 0x000411a0 -#define EPIC_GTVPR3 0x000411e0 -#define EPIC_GTDR0 0x00041130 -#define EPIC_GTDR1 0x00041170 -#define EPIC_GTDR2 0x000411b0 -#define EPIC_GTDR3 0x000411f0 - -#define EPIC_IVPR0 0x00050200 -#define EPIC_IVPR1 0x00050220 -#define EPIC_IVPR2 0x00050240 -#define EPIC_IVPR3 0x00050260 -#define EPIC_IVPR4 0x00050280 - -#define EPIC_SVPR0 0x00050200 -#define EPIC_SVPR1 0x00050220 -#define EPIC_SVPR2 0x00050240 -#define EPIC_SVPR3 0x00050260 -#define EPIC_SVPR4 0x00050280 -#define EPIC_SVPR5 0x000502A0 -#define EPIC_SVPR6 0x000502C0 -#define EPIC_SVPR7 0x000502E0 -#define EPIC_SVPR8 0x00050300 -#define EPIC_SVPR9 0x00050320 -#define EPIC_SVPRa 0x00050340 -#define EPIC_SVPRb 0x00050360 -#define EPIC_SVPRc 0x00050380 -#define EPIC_SVPRd 0x000503A0 -#define EPIC_SVPRe 0x000503C0 -#define EPIC_SVPRf 0x000503E0 - -/* MPC8240 Byte Swap/PCI Support Macros */ -#define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) ) -#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) -#define PCISWAP(x) LONGSWAP(x) - -#ifndef __ASSEMBLY__ - -/* - * MPC107 Support - * - */ -unsigned int mpc824x_mpc107_getreg(unsigned int regNum); -void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal); -void mpc824x_mpc107_write8(unsigned int address, unsigned char data); -void mpc824x_mpc107_write16(unsigned int address, unsigned short data); -void mpc824x_mpc107_write32(unsigned int address, unsigned int data); -unsigned char mpc824x_mpc107_read8(unsigned int address); -unsigned short mpc824x_mpc107_read16(unsigned int address); -unsigned int mpc824x_mpc107_read32(unsigned int address); -unsigned int mpc824x_eummbar_read(unsigned int regNum); -void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal); - -#ifdef CONFIG_PCI -struct pci_controller; -void pci_cpm824x_init(struct pci_controller* hose); -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __MPC824X_H__ */ diff --git a/include/pci.h b/include/pci.h index 216f448..7f67ca6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -670,10 +670,6 @@ extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, const char * pci_class_str(u8 class); int pci_last_busno(void); -#ifdef CONFIG_MPC824X -extern void pci_mpc824x_init (struct pci_controller *hose); -#endif - #ifdef CONFIG_MPC85xx extern void pci_mpc85xx_init (struct pci_controller *hose); #endif diff --git a/include/pcmcia/cirrus.h b/include/pcmcia/cirrus.h deleted file mode 100644 index cd34dd8..0000000 --- a/include/pcmcia/cirrus.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * cirrus.h 1.4 1999/10/25 20:03:34 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in which - * case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_CIRRUS_H -#define _LINUX_CIRRUS_H - -#ifndef PCI_VENDOR_ID_CIRRUS -#define PCI_VENDOR_ID_CIRRUS 0x1013 -#endif -#ifndef PCI_DEVICE_ID_CIRRUS_6729 -#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 -#endif -#ifndef PCI_DEVICE_ID_CIRRUS_6832 -#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 -#endif - -#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ -#define PD67_FIFO_CTL 0x17 /* FIFO control */ -#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ -#define PD67_CHIP_INFO 0x1f /* Chip information */ -#define PD67_ATA_CTL 0x026 /* 6730: ATA control */ -#define PD67_EXT_INDEX 0x2e /* Extension index */ -#define PD67_EXT_DATA 0x2f /* Extension data */ - -/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ -#define PD67_DATA_MASK0 0x01 /* Data mask 0 */ -#define PD67_DATA_MASK1 0x02 /* Data mask 1 */ -#define PD67_DMA_CTL 0x03 /* DMA control */ - -/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ -#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ -#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ -#define PD67_EXTERN_DATA 0x0a -#define PD67_MISC_CTL_3 0x25 -#define PD67_SMB_PWR_CTL 0x26 - -/* I/O window address offset */ -#define PD67_IO_OFF(w) (0x36+((w)<<1)) - -/* Timing register sets */ -#define PD67_TIME_SETUP(n) (0x3a + 3*(n)) -#define PD67_TIME_CMD(n) (0x3b + 3*(n)) -#define PD67_TIME_RECOV(n) (0x3c + 3*(n)) - -/* Flags for PD67_MISC_CTL_1 */ -#define PD67_MC1_5V_DET 0x01 /* 5v detect */ -#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ -#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ -#define PD67_MC1_PULSE_MGMT 0x04 -#define PD67_MC1_PULSE_IRQ 0x08 -#define PD67_MC1_SPKR_ENA 0x10 -#define PD67_MC1_INPACK_ENA 0x80 - -/* Flags for PD67_FIFO_CTL */ -#define PD67_FIFO_EMPTY 0x80 - -/* Flags for PD67_MISC_CTL_2 */ -#define PD67_MC2_FREQ_BYPASS 0x01 -#define PD67_MC2_DYNAMIC_MODE 0x02 -#define PD67_MC2_SUSPEND 0x04 -#define PD67_MC2_5V_CORE 0x08 -#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ -#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ -#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ -#define PD67_MC2_DMA_MODE 0x40 -#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ - -/* Flags for PD67_CHIP_INFO */ -#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ -#define PD67_INFO_CHIP_ID 0xc0 -#define PD67_INFO_REV 0x1c - -/* Fields in PD67_TIME_* registers */ -#define PD67_TIME_SCALE 0xc0 -#define PD67_TIME_SCALE_1 0x00 -#define PD67_TIME_SCALE_16 0x40 -#define PD67_TIME_SCALE_256 0x80 -#define PD67_TIME_SCALE_4096 0xc0 -#define PD67_TIME_MULT 0x3f - -/* Fields in PD67_DMA_CTL */ -#define PD67_DMA_MODE 0xc0 -#define PD67_DMA_OFF 0x00 -#define PD67_DMA_DREQ_INPACK 0x40 -#define PD67_DMA_DREQ_WP 0x80 -#define PD67_DMA_DREQ_BVD2 0xc0 -#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ - -/* Fields in PD67_EXT_CTL_1 */ -#define PD67_EC1_VCC_PWR_LOCK 0x01 -#define PD67_EC1_AUTO_PWR_CLEAR 0x02 -#define PD67_EC1_LED_ENA 0x04 -#define PD67_EC1_INV_CARD_IRQ 0x08 -#define PD67_EC1_INV_MGMT_IRQ 0x10 -#define PD67_EC1_PULLUP_CTL 0x20 - -/* Fields in PD67_MISC_CTL_3 */ -#define PD67_MC3_IRQ_MASK 0x03 -#define PD67_MC3_IRQ_PCPCI 0x00 -#define PD67_MC3_IRQ_EXTERN 0x01 -#define PD67_MC3_IRQ_PCIWAY 0x02 -#define PD67_MC3_IRQ_PCI 0x03 -#define PD67_MC3_PWR_MASK 0x0c -#define PD67_MC3_PWR_SERIAL 0x00 -#define PD67_MC3_PWR_TI2202 0x08 -#define PD67_MC3_PWR_SMB 0x0c - -/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ - -/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ -#define PD68_EXT_CTL_2 0x0b -#define PD68_PCI_SPACE 0x22 -#define PD68_PCCARD_SPACE 0x23 -#define PD68_WINDOW_TYPE 0x24 -#define PD68_EXT_CSC 0x2e -#define PD68_MISC_CTL_4 0x2f -#define PD68_MISC_CTL_5 0x30 -#define PD68_MISC_CTL_6 0x31 - -/* Extra flags in PD67_MISC_CTL_3 */ -#define PD68_MC3_HW_SUSP 0x10 -#define PD68_MC3_MM_EXPAND 0x40 -#define PD68_MC3_MM_ARM 0x80 - -/* Bridge Control Register */ -#define PD6832_BCR_MGMT_IRQ_ENA 0x0800 - -/* Socket Number Register */ -#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ - - -typedef struct cirrus_state_t { - u_char misc1, misc2; - u_char timer[6]; -} cirrus_state_t; - -/* Cirrus options */ -static int has_dma = -1; -static int has_led = -1; -static int has_ring = -1; -static int dynamic_mode = 0; -static int freq_bypass = -1; -#ifdef CONFIG_CPC45 -static int setup_time = 2; -static int cmd_time = 6; -static int recov_time = 1; -#else -static int setup_time = -1; -static int cmd_time = -1; -static int recov_time = -1; -#endif - - -#endif /* _LINUX_CIRRUS_H */ diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h deleted file mode 100644 index 0b432a8..0000000 --- a/include/pcmcia/i82365.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * i82365.h 1.21 2001/08/24 12:15:33 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in - * which case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_I82365_H -#define _LINUX_I82365_H - -/* register definitions for the Intel 82365SL PCMCIA controller */ - -/* Offsets for PCIC registers */ -#define I365_IDENT 0x00 /* Identification and revision */ -#define I365_STATUS 0x01 /* Interface status */ -#define I365_POWER 0x02 /* Power and RESETDRV control */ -#define I365_INTCTL 0x03 /* Interrupt and general control */ -#define I365_CSC 0x04 /* Card status change */ -#define I365_CSCINT 0x05 /* Card status change interrupt control */ -#define I365_ADDRWIN 0x06 /* Address window enable */ -#define I365_IOCTL 0x07 /* I/O control */ -#define I365_GENCTL 0x16 /* Card detect and general control */ -#define I365_GBLCTL 0x1E /* Global control register */ - -/* Offsets for I/O and memory window registers */ -#define I365_IO(map) (0x08+((map)<<2)) -#define I365_MEM(map) (0x10+((map)<<3)) -#define I365_W_START 0 -#define I365_W_STOP 2 -#define I365_W_OFF 4 - -/* Flags for I365_STATUS */ -#define I365_CS_BVD1 0x01 -#define I365_CS_STSCHG 0x01 -#define I365_CS_BVD2 0x02 -#define I365_CS_SPKR 0x02 -#define I365_CS_DETECT 0x0C -#define I365_CS_WRPROT 0x10 -#define I365_CS_READY 0x20 /* Inverted */ -#define I365_CS_POWERON 0x40 -#define I365_CS_GPI 0x80 - -/* Flags for I365_POWER */ -#define I365_PWR_OFF 0x00 /* Turn off the socket */ -#define I365_PWR_OUT 0x80 /* Output enable */ -#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */ -#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */ -#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */ -/* There are different layouts for B-step and DF-step chips: the B - step has independent Vpp1/Vpp2 control, and the DF step has only - Vpp1 control, plus 3V control */ -#define I365_VCC_5V 0x10 /* Vcc = 5.0v */ -#define I365_VCC_3V 0x18 /* Vcc = 3.3v */ -#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */ -#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */ -#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */ -#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */ -#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */ -#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */ - -/* Flags for I365_INTCTL */ -#define I365_RING_ENA 0x80 -#define I365_PC_RESET 0x40 -#define I365_PC_IOCARD 0x20 -#define I365_INTR_ENA 0x10 -#define I365_IRQ_MASK 0x0F - -/* Flags for I365_CSC and I365_CSCINT*/ -#define I365_CSC_BVD1 0x01 -#define I365_CSC_STSCHG 0x01 -#define I365_CSC_BVD2 0x02 -#define I365_CSC_READY 0x04 -#define I365_CSC_DETECT 0x08 -#define I365_CSC_ANY 0x0F -#define I365_CSC_GPI 0x10 - -/* Flags for I365_ADDRWIN */ -#define I365_ADDR_MEMCS16 0x20 -#define I365_ENA_IO(map) (0x40 << (map)) -#define I365_ENA_MEM(map) (0x01 << (map)) - -/* Flags for I365_IOCTL */ -#define I365_IOCTL_MASK(map) (0x0F << (map<<2)) -#define I365_IOCTL_WAIT(map) (0x08 << (map<<2)) -#define I365_IOCTL_0WS(map) (0x04 << (map<<2)) -#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2)) -#define I365_IOCTL_16BIT(map) (0x01 << (map<<2)) - -/* Flags for I365_GENCTL */ -#define I365_CTL_16DELAY 0x01 -#define I365_CTL_RESET 0x02 -#define I365_CTL_GPI_ENA 0x04 -#define I365_CTL_GPI_CTL 0x08 -#define I365_CTL_RESUME 0x10 -#define I365_CTL_SW_IRQ 0x20 - -/* Flags for I365_GBLCTL */ -#define I365_GBL_PWRDOWN 0x01 -#define I365_GBL_CSC_LEV 0x02 -#define I365_GBL_WRBACK 0x04 -#define I365_GBL_IRQ_0_LEV 0x08 -#define I365_GBL_IRQ_1_LEV 0x10 - -/* Flags for memory window registers */ -#define I365_MEM_16BIT 0x8000 /* In memory start high byte */ -#define I365_MEM_0WS 0x4000 -#define I365_MEM_WS1 0x8000 /* In memory stop high byte */ -#define I365_MEM_WS0 0x4000 -#define I365_MEM_WRPROT 0x8000 /* In offset high byte */ -#define I365_MEM_REG 0x4000 - -#define I365_REG(slot, reg) (((slot) << 6) | (reg)) - -/* Default ISA interrupt mask */ -#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */ - -/* Device ID's for PCI-to-PCMCIA bridges */ - -#ifndef PCI_VENDOR_ID_INTEL -#define PCI_VENDOR_ID_INTEL 0x8086 -#endif -#ifndef PCI_DEVICE_ID_INTEL_82092AA_0 -#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 -#endif -#ifndef PCI_VENDOR_ID_OMEGA -#define PCI_VENDOR_ID_OMEGA 0x119b -#endif -#ifndef PCI_DEVICE_ID_OMEGA_82C092G -#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 -#endif - -#endif /* _LINUX_I82365_H */ diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h deleted file mode 100644 index aafae8a..0000000 --- a/include/pcmcia/ss.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * ss.h 1.31 2001/08/24 12:16:13 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in - * which case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_SS_H -#define _LINUX_SS_H - -/* For RegisterCallback */ -typedef struct ss_callback_t { - void (*handler)(void *info, u_int events); - void *info; -} ss_callback_t; - -/* Definitions for card status flags for GetStatus */ -#define SS_WRPROT 0x0001 -#define SS_CARDLOCK 0x0002 -#define SS_EJECTION 0x0004 -#define SS_INSERTION 0x0008 -#define SS_BATDEAD 0x0010 -#define SS_BATWARN 0x0020 -#define SS_READY 0x0040 -#define SS_DETECT 0x0080 -#define SS_POWERON 0x0100 -#define SS_GPI 0x0200 -#define SS_STSCHG 0x0400 -#define SS_CARDBUS 0x0800 -#define SS_3VCARD 0x1000 -#define SS_XVCARD 0x2000 -#define SS_PENDING 0x4000 - -/* for InquireSocket */ -typedef struct socket_cap_t { - u_int features; - u_int irq_mask; - u_int map_size; - u_char pci_irq; - u_char cardbus; - struct pci_bus *cb_bus; - struct bus_operations *bus; -} socket_cap_t; - -/* InquireSocket capabilities */ -#define SS_CAP_PAGE_REGS 0x0001 -#define SS_CAP_VIRTUAL_BUS 0x0002 -#define SS_CAP_MEM_ALIGN 0x0004 -#define SS_CAP_STATIC_MAP 0x0008 -#define SS_CAP_PCCARD 0x4000 -#define SS_CAP_CARDBUS 0x8000 - -/* for GetSocket, SetSocket */ -typedef struct socket_state_t { - u_int flags; - u_int csc_mask; - u_char Vcc, Vpp; - u_char io_irq; -} socket_state_t; - -/* Socket configuration flags */ -#define SS_PWR_AUTO 0x0010 -#define SS_IOCARD 0x0020 -#define SS_RESET 0x0040 -#define SS_DMA_MODE 0x0080 -#define SS_SPKR_ENA 0x0100 -#define SS_OUTPUT_ENA 0x0200 -#define SS_ZVCARD 0x0400 - -/* Flags for I/O port and memory windows */ -#define MAP_ACTIVE 0x01 -#define MAP_16BIT 0x02 -#define MAP_AUTOSZ 0x04 -#define MAP_0WS 0x08 -#define MAP_WRPROT 0x10 -#define MAP_ATTRIB 0x20 -#define MAP_USE_WAIT 0x40 -#define MAP_PREFETCH 0x80 - -/* Use this just for bridge windows */ -#define MAP_IOSPACE 0x20 - -typedef struct pccard_io_map { - u_char map; - u_char flags; - u_short speed; - u_short start, stop; -} pccard_io_map; - -typedef struct pccard_mem_map { - u_char map; - u_char flags; - u_short speed; - u_long sys_start, sys_stop; - u_int card_start; -} pccard_mem_map; - -typedef struct cb_bridge_map { - u_char map; - u_char flags; - u_int start, stop; -} cb_bridge_map; - -enum ss_service { - SS_RegisterCallback, SS_InquireSocket, - SS_GetStatus, SS_GetSocket, SS_SetSocket, - SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap, - SS_GetBridge, SS_SetBridge, SS_ProcSetup -}; - -#endif /* _LINUX_SS_H */ diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h deleted file mode 100644 index 5453588..0000000 --- a/include/pcmcia/ti113x.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * ti113x.h 1.31 2002/05/12 18:19:47 - * - * The contents of this file are subject to the Mozilla Public License - * Version 1.1 (the "License"); you may not use this file except in - * compliance with the License. You may obtain a copy of the License - * at http://www.mozilla.org/MPL/ - * - * Software distributed under the License is distributed on an "AS IS" - * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See - * the License for the specific language governing rights and - * limitations under the License. - * - * The initial developer of the original code is David A. Hinds - * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds - * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. - * - * Alternatively, the contents of this file may be used under the - * terms of the GNU General Public License version 2 (the "GPL"), in - * which case the provisions of the GPL are applicable instead of the - * above. If you wish to allow the use of your version of this file - * only under the terms of the GPL and not to allow others to use - * your version of this file under the MPL, indicate your decision by - * deleting the provisions above and replace them with the notice and - * other provisions required by the GPL. If you do not delete the - * provisions above, a recipient may use your version of this file - * under either the MPL or the GPL. - */ - -#ifndef _LINUX_TI113X_H -#define _LINUX_TI113X_H - -#ifndef PCI_VENDOR_ID_TI -#define PCI_VENDOR_ID_TI 0x104c -#endif - -#ifndef PCI_DEVICE_ID_TI_1130 -#define PCI_DEVICE_ID_TI_1130 0xac12 -#endif -#ifndef PCI_DEVICE_ID_TI_1031 -#define PCI_DEVICE_ID_TI_1031 0xac13 -#endif -#ifndef PCI_DEVICE_ID_TI_1131 -#define PCI_DEVICE_ID_TI_1131 0xac15 -#endif -#ifndef PCI_DEVICE_ID_TI_1210 -#define PCI_DEVICE_ID_TI_1210 0xac1a -#endif -#ifndef PCI_DEVICE_ID_TI_1211 -#define PCI_DEVICE_ID_TI_1211 0xac1e -#endif -#ifndef PCI_DEVICE_ID_TI_1220 -#define PCI_DEVICE_ID_TI_1220 0xac17 -#endif -#ifndef PCI_DEVICE_ID_TI_1221 -#define PCI_DEVICE_ID_TI_1221 0xac19 -#endif -#ifndef PCI_DEVICE_ID_TI_1250A -#define PCI_DEVICE_ID_TI_1250A 0xac16 -#endif -#ifndef PCI_DEVICE_ID_TI_1225 -#define PCI_DEVICE_ID_TI_1225 0xac1c -#endif -#ifndef PCI_DEVICE_ID_TI_1251A -#define PCI_DEVICE_ID_TI_1251A 0xac1d -#endif -#ifndef PCI_DEVICE_ID_TI_1251B -#define PCI_DEVICE_ID_TI_1251B 0xac1f -#endif -#ifndef PCI_DEVICE_ID_TI_1410 -#define PCI_DEVICE_ID_TI_1410 0xac50 -#endif -#ifndef PCI_DEVICE_ID_TI_1420 -#define PCI_DEVICE_ID_TI_1420 0xac51 -#endif -#ifndef PCI_DEVICE_ID_TI_1450 -#define PCI_DEVICE_ID_TI_1450 0xac1b -#endif -#ifndef PCI_DEVICE_ID_TI_1451 -#define PCI_DEVICE_ID_TI_1451 0xac52 -#endif -#ifndef PCI_DEVICE_ID_TI_1510 -#define PCI_DEVICE_ID_TI_1510 0xac56 -#endif -#ifndef PCI_DEVICE_ID_TI_4410 -#define PCI_DEVICE_ID_TI_4410 0xac41 -#endif -#ifndef PCI_DEVICE_ID_TI_4450 -#define PCI_DEVICE_ID_TI_4450 0xac40 -#endif -#ifndef PCI_DEVICE_ID_TI_4451 -#define PCI_DEVICE_ID_TI_4451 0xac42 -#endif - -/* Register definitions for TI 113X PCI-to-CardBus bridges */ - -/* System Control Register */ -#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */ -#define TI113X_SCR_SMIROUTE 0x04000000 -#define TI113X_SCR_SMISTATUS 0x02000000 -#define TI113X_SCR_SMIENB 0x01000000 -#define TI113X_SCR_VCCPROT 0x00200000 -#define TI113X_SCR_REDUCEZV 0x00100000 -#define TI113X_SCR_CDREQEN 0x00080000 -#define TI113X_SCR_CDMACHAN 0x00070000 -#define TI113X_SCR_SOCACTIVE 0x00002000 -#define TI113X_SCR_PWRSTREAM 0x00000800 -#define TI113X_SCR_DELAYUP 0x00000400 -#define TI113X_SCR_DELAYDOWN 0x00000200 -#define TI113X_SCR_INTERROGATE 0x00000100 -#define TI113X_SCR_CLKRUN_SEL 0x00000080 -#define TI113X_SCR_PWRSAVINGS 0x00000040 -#define TI113X_SCR_SUBSYSRW 0x00000020 -#define TI113X_SCR_CB_DPAR 0x00000010 -#define TI113X_SCR_CDMA_EN 0x00000008 -#define TI113X_SCR_ASYNC_IRQ 0x00000004 -#define TI113X_SCR_KEEPCLK 0x00000002 -#define TI113X_SCR_CLKRUN_ENA 0x00000001 - -#define TI122X_SCR_SER_STEP 0xc0000000 -#define TI122X_SCR_INTRTIE 0x20000000 -#define TI122X_SCR_P2CCLK 0x08000000 -#define TI122X_SCR_CBRSVD 0x00400000 -#define TI122X_SCR_MRBURSTDN 0x00008000 -#define TI122X_SCR_MRBURSTUP 0x00004000 -#define TI122X_SCR_RIMUX 0x00000001 - -/* Multimedia Control Register */ -#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */ -#define TI1250_MMC_ZVOUTEN 0x80 -#define TI1250_MMC_PORTSEL 0x40 -#define TI1250_MMC_ZVEN1 0x02 -#define TI1250_MMC_ZVEN0 0x01 - -#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */ -#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */ -#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */ -#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */ -#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */ -#define TI12XX_IRQMUX 0x8c /* 32 bit */ - -/* Retry Status Register */ -#define TI113X_RETRY_STATUS 0x90 /* 8 bit */ -#define TI113X_RSR_PCIRETRY 0x80 -#define TI113X_RSR_CBRETRY 0x40 -#define TI113X_RSR_TEXP_CBB 0x20 -#define TI113X_RSR_MEXP_CBB 0x10 -#define TI113X_RSR_TEXP_CBA 0x08 -#define TI113X_RSR_MEXP_CBA 0x04 -#define TI113X_RSR_TEXP_PCI 0x02 -#define TI113X_RSR_MEXP_PCI 0x01 - -/* Card Control Register */ -#define TI113X_CARD_CONTROL 0x91 /* 8 bit */ -#define TI113X_CCR_RIENB 0x80 -#define TI113X_CCR_ZVENABLE 0x40 -#define TI113X_CCR_PCI_IRQ_ENA 0x20 -#define TI113X_CCR_PCI_IREQ 0x10 -#define TI113X_CCR_PCI_CSC 0x08 -#define TI113X_CCR_SPKROUTEN 0x02 -#define TI113X_CCR_IFG 0x01 - -#define TI1220_CCR_PORT_SEL 0x20 -#define TI122X_CCR_AUD2MUX 0x04 - -/* Device Control Register */ -#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */ -#define TI113X_DCR_5V_FORCE 0x40 -#define TI113X_DCR_3V_FORCE 0x20 -#define TI113X_DCR_IMODE_MASK 0x06 -#define TI113X_DCR_IMODE_ISA 0x02 -#define TI113X_DCR_IMODE_SERIAL 0x04 - -#define TI12XX_DCR_IMODE_PCI_ONLY 0x00 -#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06 - -/* Buffer Control Register */ -#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */ -#define TI113X_BCR_CB_READ_DEPTH 0x08 -#define TI113X_BCR_CB_WRITE_DEPTH 0x04 -#define TI113X_BCR_PCI_READ_DEPTH 0x02 -#define TI113X_BCR_PCI_WRITE_DEPTH 0x01 - -/* Diagnostic Register */ -#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */ -#define TI1250_DIAG_TRUE_VALUE 0x80 -#define TI1250_DIAG_PCI_IREQ 0x40 -#define TI1250_DIAG_PCI_CSC 0x20 -#define TI1250_DIAG_ASYNC_CSC 0x01 - -/* DMA Registers */ -#define TI113X_DMA_0 0x94 /* 32 bit */ -#define TI113X_DMA_1 0x98 /* 32 bit */ - -/* ExCA IO offset registers */ -#define TI113X_IO_OFFSET(map) (0x36+((map)<<1)) - -/* Data structure for tracking vendor-specific state */ -typedef struct ti113x_state_t { - u32 sysctl; /* TI113X_SYSTEM_CONTROL */ - u8 cardctl; /* TI113X_CARD_CONTROL */ - u8 devctl; /* TI113X_DEVICE_CONTROL */ - u8 diag; /* TI1250_DIAGNOSTIC */ - u32 irqmux; /* TI12XX_IRQMUX */ -} ti113x_state_t; - -#define TI_PCIC_ID \ - IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \ - IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \ - IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \ - IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451 - -#define TI_PCIC_INFO \ - { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \ - { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \ - { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \ - { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \ - { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \ - { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \ - { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \ - { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \ - { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \ - { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \ - { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \ - { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \ - { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \ - { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \ - { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \ - { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \ - { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \ - { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \ - { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) } - -#endif /* _LINUX_TI113X_H */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 5fcef9c..36d5975 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -80,7 +80,7 @@ #define r31 31 -#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X) +#if defined(CONFIG_8xx) /* Some special registers */ @@ -92,7 +92,7 @@ #define LCTRL2 157 /* Load/Store Support (37-41) */ #define ICTRL 158 -#endif /* CONFIG_8xx, CONFIG_MPC824X */ +#endif /* CONFIG_8xx */ #if defined(CONFIG_5xx) diff --git a/post/drivers/memory.c b/post/drivers/memory.c index d94a437..d512fa5 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -170,7 +170,7 @@ DECLARE_GLOBAL_DATA_PTR; */ static void move64(const unsigned long long *src, unsigned long long *dest) { -#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) +#if defined(CONFIG_MPC8260) asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ "stfd 0, 0(4)" /* *dest = fpr0 */ : : : "fr0" ); /* Clobbers fr0 */ |