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| author | TsiChungLiew <Tsi-Chung.Liew@freescale.com> | 2008-01-30 15:04:42 -0600 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2008-02-20 13:33:45 -0700 |
| commit | c54f9263e4e11e34b1e70c160bc467ef1d8ec59d (patch) | |
| tree | 0c39d1011a1fd15ba6716da506796647fc7f973b | |
| parent | b6f29c84c208a091f95a10cbc9852d729659ba20 (diff) | |
| download | u-boot-imx-c54f9263e4e11e34b1e70c160bc467ef1d8ec59d.zip u-boot-imx-c54f9263e4e11e34b1e70c160bc467ef1d8ec59d.tar.gz u-boot-imx-c54f9263e4e11e34b1e70c160bc467ef1d8ec59d.tar.bz2 | |
ColdFire: Fix 5282 and 5271 interrupt mask bit
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| -rw-r--r-- | cpu/mcf52x2/interrupts.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 2ccbde5..9167cec 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -77,7 +77,7 @@ void dtimer_intr_setup(void) volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; - intp->imrl0 &= ~0xFFFFFFFE; + intp->imrl0 &= 0xFFFFFFFE; intp->imrl0 &= ~CFG_TMRINTR_MASK; } #endif /* CONFIG_MCFTMR */ |