Merge branch 'master' of git://git.denx.de/u-boot-arm

149 files changed, 17596 insertions, 6851 deletions

diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk
deleted file mode 100644
index b87ce24..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 72c69b9..2c5cd63 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -112,24 +112,38 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
 		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
 		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 	},
+
+	/*
+	 * T124: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+	},
 };
 
-void adjust_pllp_out_freqs(void)
+static inline void pllx_set_iddq(void)
 {
+#if defined(CONFIG_TEGRA124)
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
 	u32 reg;
 
-	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-	reg = readl(&pll->pll_out[0]);	/* OUTA, contains OUT2 / OUT1 */
-	reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
-		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
-	writel(reg, &pll->pll_out[0]);
-
-	reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
-	reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
-		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
-	writel(reg, &pll->pll_out[1]);
+	/* Disable IDDQ */
+	reg = readl(&clkrst->crc_pllx_misc3);
+	reg &= ~PLLX_IDDQ_MASK;
+	writel(reg, &clkrst->crc_pllx_misc3);
+	udelay(2);
+	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+	      readl(&clkrst->crc_pllx_misc3));
+#endif
 }
 
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
@@ -146,6 +160,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 
 	debug(" pllx_set_rate entry\n");
 
+	pllx_set_iddq();
+
 	/* Set BYPASS, m, n and p to PLLX_BASE */
 	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
 	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
@@ -162,18 +178,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 		reg |= (1 << PLL_DCCON_SHIFT);
 	writel(reg, &pll->pll_misc);
 
-	/* Enable PLLX */
-	reg = readl(&pll->pll_base);
-	reg |= PLL_ENABLE_MASK;
-
 	/* Disable BYPASS */
+	reg = readl(&pll->pll_base);
 	reg &= ~PLL_BYPASS_MASK;
 	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base = 0x%08X\n", reg);
 
 	/* Set lock_enable to PLLX_MISC */
 	reg = readl(&pll->pll_misc);
 	reg |= PLL_LOCK_ENABLE_MASK;
 	writel(reg, &pll->pll_misc);
+	debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+	/* Enable PLLX last, once it's all configured */
+	reg = readl(&pll->pll_base);
+	reg |= PLL_ENABLE_MASK;
+	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base final = 0x%08X\n", reg);
 
 	return 0;
 }
@@ -207,12 +228,6 @@ void init_pllx(void)
 	/* set pllx */
 	sel = &tegra_pll_x_table[chip_sku][osc];
 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
-	/* adjust PLLP_out1-4 on T3x/T114 */
-	if (soc_type >= CHIPID_TEGRA30) {
-		debug("  init_pllx: adjusting PLLP out freqs\n");
-		adjust_pllp_out_freqs();
-	}
 }
 
 void enable_cpu_clock(int enable)
@@ -334,7 +349,6 @@ void reset_A9_cpu(int reset)
 void clock_enable_coresight(int enable)
 {
 	u32 rst, src = 2;
-	int soc_type;
 
 	debug("clock_enable_coresight entry\n");
 	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
@@ -343,20 +357,11 @@ void clock_enable_coresight(int enable)
 	if (enable) {
 		/*
 		 * Put CoreSight on PLLP_OUT0 and divide it down as per
-		 * PLLP base frequency based on SoC type (T20/T30/T114).
+		 * PLLP base frequency based on SoC type (T20/T30+).
 		 * Clock divider request would setup CSITE clock as 144MHz
 		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 		 */
-
-		soc_type = tegra_get_chip();
-		if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
-		else if (soc_type == CHIPID_TEGRA20)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-		else
-			printf("%s: Unknown SoC type %X!\n",
-				 __func__, soc_type);
-
+		src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
 		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
 
 		/* Unlock the CPU CoreSight interfaces */
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 60412c7..b4ca44f 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2014
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,9 +11,12 @@
 #define IO_STABILIZATION_DELAY	(1000)
 
 #if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ	(216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ	(408000)
+#define NVBL_PLLP_KHZ	216000
+#define CSITE_KHZ	144000
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+	defined(CONFIG_TEGRA124)
+#define NVBL_PLLP_KHZ	408000
+#define CSITE_KHZ	204000
 #else
 #error "Unknown Tegra chip!"
 #endif
@@ -68,3 +71,4 @@ int tegra_get_chip(void);
 int tegra_get_sku_info(void);
 int tegra_get_chip_sku(void);
 void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 51ecff7..d10b96a 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
 	/* Wait for PLL-X to lock */
 	do {
 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-	} while ((reg & (1 << 27)) == 0);
+	} while ((reg & PLL_LOCK_MASK) == 0);
 
 	/* Wait until all clocks are stable */
 	udelay(PLL_STABILIZATION_DELAY);
@@ -126,18 +126,6 @@ void t114_init_clocks(void)
 	/* Set active CPU cluster to G */
 	clrbits_le32(&flow->cluster_control, 1);
 
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
 	debug("Setting up PLLX\n");
@@ -204,45 +192,43 @@ void t114_init_clocks(void)
 	debug("t114_init_clocks exit\n");
 }
 
-static int is_partition_powered(u32 mask)
+static bool is_partition_powered(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
 	/* Get power gate status */
 	reg = readl(&pmc->pmc_pwrgate_status);
-	return (reg & mask) == mask;
+	return !!(reg & (1 << partid));
 }
 
-static int is_clamp_enabled(u32 mask)
+static bool is_clamp_enabled(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
-	/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-	reg = readl(&pmc->pmc_pwrgate_timer_on);
-	return (reg & mask) == mask;
+	/* Get clamp status. */
+	reg = readl(&pmc->pmc_clamp_status);
+	return !!(reg & (1 << partid));
 }
 
-static void power_partition(u32 status, u32 partid)
+static void power_partition(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
-	debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+	debug("%s: part ID = %08X\n", __func__, partid);
 	/* Is the partition already on? */
-	if (!is_partition_powered(status)) {
+	if (!is_partition_powered(partid)) {
 		/* No, toggle the partition power state (OFF -> ON) */
 		debug("power_partition, toggling state\n");
-		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
 
 		/* Wait for the power to come up */
-		while (!is_partition_powered(status))
+		while (!is_partition_powered(partid))
 			;
 
 		/* Wait for the clamp status to be cleared */
-		while (is_clamp_enabled(status))
+		while (is_clamp_enabled(partid))
 			;
 
 		/* Give I/O signals time to stabilize */
@@ -257,13 +243,13 @@ void powerup_cpus(void)
 	/* We boot to the fast cluster */
 	debug("powerup_cpus entry: G cluster\n");
 	/* Power up the fast cluster rail partition */
-	power_partition(CRAIL, CRAILID);
+	power_partition(CRAIL);
 
 	/* Power up the fast cluster non-CPU partition */
-	power_partition(C0NC, C0NCID);
+	power_partition(C0NC);
 
 	/* Power up the fast cluster CPU0 partition */
-	power_partition(CE0, CE0ID);
+	power_partition(CE0);
 }
 
 void start_cpu(u32 reset_vector)
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
new file mode 100644
index 0000000..61abf45
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/config.mk b/arch/arm/cpu/arm720t/tegra124/config.mk
new file mode 100644
index 0000000..5e10701
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/config.mk
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2010-2013
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#/
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
new file mode 100644
index 0000000..c03aaf1
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+	pmic_enable_cpu_vdd();
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+	 */
+	writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+		debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+	} while ((reg & PLL_LOCK_MASK) == 0);
+
+	debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	debug("%s: Enabling clock to all CPUs\n", __func__);
+	/* Enable the clock to all CPUs */
+	reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+		CLR_CPU0_CLK_STP;
+	writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+	debug("%s: Enabling main CPU complex clocks\n", __func__);
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+
+	debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+
+	/* Take the slow and fast partitions out of reset */
+	reg = CLR_NONCPURESET;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+		CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+		CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	debug("tegra124_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	/* Change the oscillator drive strength */
+	val = readl(&clkrst->crc_osc_ctrl);
+	val &= ~OSC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+	writel(val, &clkrst->crc_osc_ctrl);
+
+	/* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+	val = readl(&pmc->pmc_osc_edpd_over);
+	val &= ~PMC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+	writel(val, &pmc->pmc_osc_edpd_over);
+
+	/* Set HOLD_CKE_LOW_EN to 1 */
+	setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/*
+	 * Set MSELECT clock source as PLLP (00), and ask for a clock
+	 * divider that would set the MSELECT clock at 102MHz for a
+	 * PLLP base of 408MHz.
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+				    CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
+
+	debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: part ID = %08X\n", __func__, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(partid)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(partid))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+
+	/* Power up the fast cluster rail partition */
+	debug("powerup_cpus: CRAIL\n");
+	power_partition(CRAIL);
+
+	/* Power up the fast cluster non-CPU partition */
+	debug("powerup_cpus: C0NC\n");
+	power_partition(C0NC);
+
+	/* Power up the fast cluster CPU0 partition */
+	debug("powerup_cpus: CE0\n");
+	power_partition(CE0);
+
+	debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	tegra124_init_clocks();
+
+	/* Set power-gating timer multiplier */
+	clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
+	setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+
+	enable_cpu_power_rail();
+	enable_cpu_clocks();
+	clock_enable_coresight(1);
+	remove_cpu_resets();
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+	powerup_cpus();
+	debug("start_cpu exit, should continue @ reset_vector\n");
+}
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index e162357..a806483 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
 	/* Set active CPU cluster to G */
 	clrbits_le32(flow->cluster_control, 1 << 0);
 
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
 	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 5bde9d1..1fea4d6 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,7 +26,7 @@ struct clk_bit_info {
 };
 
 /* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+static struct clk_bit_info clk_bit_info[] = {
 	{0,	0,	-1},
 	{4,	4,	-1},
 	{8,	8,	-1},
@@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos4_clock *clk =
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos4x12: set the mmc clock */
@@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos4x12_clock *clk =
 		(struct exynos4x12_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */
@@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */
@@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos5420_clock *clk =
 		(struct exynos5420_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val, shift;
+	unsigned int shift;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
 	addr = (unsigned int)&clk->div_fsys1;
 	shift = dev_index * 10;
 
-	val = readl(addr);
-	val &= ~(0x3ff << shift);
-	val |= (div & 0x3ff) << shift;
-	writel(val, addr);
+	clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
 }
 
 /* get_lcd_clk: return lcd clock frequency */
@@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK
@@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0
@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
 
 	/*
 	 * CLK_GATE_IP_LCD0
@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0
@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x1;
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
 }
 
 void exynos5_set_lcd_clk(void)
 {
 	struct exynos5_clock *clk =
 	    (struct exynos5_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK
@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0
@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_disp1_0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_disp1_0);
+	clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
 
 	/*
 	 * CLK_GATE_IP_LCD0
@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_disp1);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_disp1);
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0
@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x0;
-	writel(cfg, &clk->div_disp1_0);
+	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_SRC_LCD0
@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set mipi0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf << 12);
-	cfg |= (0x6 << 12);
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
 
 	/*
 	 * CLK_SRC_MASK_LCD0
@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_MASK		[12]
 	 * set src mask mipi0 0x1: Unmask
 	 */
-	cfg = readl(&clk->src_mask_lcd0);
-	cfg |= (0x1 << 12);
-	writel(cfg, &clk->src_mask_lcd0);
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
 	/*
 	 * CLK_GATE_IP_LCD0
@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for MIPI0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 3;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 
 	/*
 	 * CLK_DIV_LCD0
@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set mipi ratio
 	 */
-	cfg &= ~(0xf << 16);
-	cfg |= (0x1 << 16);
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 904177a..645c497 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -751,12 +751,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
 	if (err)
 		return PERIPH_ID_NONE;
 
-	/* check for invalid peripheral id */
-	if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
-		return cell[1];
-
-	debug(" invalid peripheral id\n");
-	return PERIPH_ID_NONE;
+	return cell[1];
 }
 
 int pinmux_decode_periph_id(const void *blob, int node)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index dfa3760..8e7411d 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -418,55 +418,6 @@ static void setup_dplls(void)
 #endif
 }
 
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-static void setup_non_essential_dplls(void)
-{
-	u32 abe_ref_clk;
-	const struct dpll_params *params;
-
-	/* IVA */
-	clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
-		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
-
-	params = get_iva_dpll_params(*dplls_data);
-	do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
-
-	/* Configure ABE dpll */
-	params = get_abe_dpll_params(*dplls_data);
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
-
-	if (omap_revision() == DRA752_ES1_0)
-		/* Select the sys clk for dpll_abe */
-		clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
-				CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
-				CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
-#else
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
-	/*
-	 * We need to enable some additional options to achieve
-	 * 196.608MHz from 32768 Hz
-	 */
-	setbits_le32((*prcm)->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
-			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
-			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
-			CM_CLKMODE_DPLL_REGM4XEN_MASK);
-	/* Spend 4 REFCLK cycles at each stage */
-	clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
-			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
-#endif
-
-	/* Select the right reference clk */
-	clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
-			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
-			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
-	/* Lock the dpll */
-	do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
-}
-#endif
-
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
 {
 	u32 offset_code;
@@ -760,10 +711,6 @@ void prcm_init(void)
 		timer_init();
 		scale_vcores(*omap_vcores);
 		setup_dplls();
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-		setup_non_essential_dplls();
-		enable_non_essential_clocks();
-#endif
 		setup_warmreset_time();
 		break;
 	default:
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index cd6289b..429c4be 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -179,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-	if ((omap_revision() >= OMAP5430_ES1_0) ||
-				(omap_revision() == DRA752_ES1_0)) {
+	if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 			&emif->emif_l3_config);
 	} else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -309,7 +308,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	 * The same sequence should work on OMAP5432 as well. But strange that
 	 * it is not working
 	 */
-	if (omap_revision() == DRA752_ES1_0) {
+	if (is_dra7xx()) {
 		do_ext_phy_settings(base, regs);
 		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 		writel(regs->sdram_config_init, &emif->emif_sdram_config);
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 85d3754..bf29510 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -43,16 +43,10 @@ static void set_mux_conf_regs(void)
 		set_muxconf_regs_essential();
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
-#ifdef CONFIG_SYS_ENABLE_PADS_ALL
-		set_muxconf_regs_non_essential();
-#endif
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
 		set_muxconf_regs_essential();
-#ifdef CONFIG_SYS_ENABLE_PADS_ALL
-		set_muxconf_regs_non_essential();
-#endif
 		break;
 	}
 }
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 1b2f439..4dec73e 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -399,91 +399,6 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-	u32 const clk_domains_non_essential[] = {
-		(*prcm)->cm_mpu_m3_clkstctrl,
-		(*prcm)->cm_ivahd_clkstctrl,
-		(*prcm)->cm_dsp_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sgx_clkstctrl,
-		(*prcm)->cm1_abe_clkstctrl,
-		(*prcm)->cm_c2c_clkstctrl,
-		(*prcm)->cm_cam_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 const clk_modules_hw_auto_non_essential[] = {
-		(*prcm)->cm_l3instr_l3_3_clkctrl,
-		(*prcm)->cm_l3instr_l3_instr_clkctrl,
-		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-		(*prcm)->cm_l3init_hsi_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_non_essential[] = {
-		(*prcm)->cm1_abe_aess_clkctrl,
-		(*prcm)->cm1_abe_pdm_clkctrl,
-		(*prcm)->cm1_abe_dmic_clkctrl,
-		(*prcm)->cm1_abe_mcasp_clkctrl,
-		(*prcm)->cm1_abe_mcbsp1_clkctrl,
-		(*prcm)->cm1_abe_mcbsp2_clkctrl,
-		(*prcm)->cm1_abe_mcbsp3_clkctrl,
-		(*prcm)->cm1_abe_slimbus_clkctrl,
-		(*prcm)->cm1_abe_timer5_clkctrl,
-		(*prcm)->cm1_abe_timer6_clkctrl,
-		(*prcm)->cm1_abe_timer7_clkctrl,
-		(*prcm)->cm1_abe_timer8_clkctrl,
-		(*prcm)->cm1_abe_wdt3_clkctrl,
-		(*prcm)->cm_l4per_gptimer9_clkctrl,
-		(*prcm)->cm_l4per_gptimer10_clkctrl,
-		(*prcm)->cm_l4per_gptimer11_clkctrl,
-		(*prcm)->cm_l4per_gptimer3_clkctrl,
-		(*prcm)->cm_l4per_gptimer4_clkctrl,
-		(*prcm)->cm_l4per_hdq1w_clkctrl,
-		(*prcm)->cm_l4per_mcbsp4_clkctrl,
-		(*prcm)->cm_l4per_mcspi2_clkctrl,
-		(*prcm)->cm_l4per_mcspi3_clkctrl,
-		(*prcm)->cm_l4per_mcspi4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd3_clkctrl,
-		(*prcm)->cm_l4per_mmcsd4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd5_clkctrl,
-		(*prcm)->cm_l4per_uart1_clkctrl,
-		(*prcm)->cm_l4per_uart2_clkctrl,
-		(*prcm)->cm_l4per_uart4_clkctrl,
-		(*prcm)->cm_wkup_keyboard_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_cam_iss_clkctrl,
-		(*prcm)->cm_cam_fdif_clkctrl,
-		(*prcm)->cm_dss_dss_clkctrl,
-		(*prcm)->cm_sgx_sgx_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-	do_enable_clocks(clk_domains_non_essential,
-			 clk_modules_hw_auto_non_essential,
-			 clk_modules_explicit_en_non_essential,
-			 0);
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 void hw_data_init(void)
 {
 	u32 omap_rev = omap_revision();
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
index 31b6795..3bf8897 100644
--- a/arch/arm/cpu/armv7/omap5/abb.c
+++ b/arch/arm/cpu/armv7/omap5/abb.c
@@ -28,18 +28,25 @@
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
 {
 	u32 vset;
+	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
+	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
 
+	if (!is_omap54xx()) {
+		/* DRA7 */
+		fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
+		fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
+	}
 	/*
 	 * ABB parameters must be properly fused
 	 * otherwise ABB should be disabled
 	 */
 	vset = readl(fuse);
-	if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+	if (!(vset & fuse_enable_mask))
 		return -1;
 
 	/* prepare VSET value for LDOVBB mux register */
-	vset &= OMAP5_ABB_FUSE_VSET_MASK;
-	vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+	vset &= fuse_vset_mask;
+	vset >>= ffs(fuse_vset_mask) - 1;
 	vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
 	vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
 
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5268a1f..ad97132 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -486,94 +486,6 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-	u32 const clk_domains_non_essential[] = {
-		(*prcm)->cm_mpu_m3_clkstctrl,
-		(*prcm)->cm_ivahd_clkstctrl,
-		(*prcm)->cm_dsp_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sgx_clkstctrl,
-		(*prcm)->cm1_abe_clkstctrl,
-		(*prcm)->cm_c2c_clkstctrl,
-		(*prcm)->cm_cam_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 const clk_modules_hw_auto_non_essential[] = {
-		(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
-		(*prcm)->cm_ivahd_ivahd_clkctrl,
-		(*prcm)->cm_ivahd_sl2_clkctrl,
-		(*prcm)->cm_dsp_dsp_clkctrl,
-		(*prcm)->cm_l3instr_l3_3_clkctrl,
-		(*prcm)->cm_l3instr_l3_instr_clkctrl,
-		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-		(*prcm)->cm_l3init_hsi_clkctrl,
-		(*prcm)->cm_l4per_hdq1w_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_non_essential[] = {
-		(*prcm)->cm1_abe_aess_clkctrl,
-		(*prcm)->cm1_abe_pdm_clkctrl,
-		(*prcm)->cm1_abe_dmic_clkctrl,
-		(*prcm)->cm1_abe_mcasp_clkctrl,
-		(*prcm)->cm1_abe_mcbsp1_clkctrl,
-		(*prcm)->cm1_abe_mcbsp2_clkctrl,
-		(*prcm)->cm1_abe_mcbsp3_clkctrl,
-		(*prcm)->cm1_abe_slimbus_clkctrl,
-		(*prcm)->cm1_abe_timer5_clkctrl,
-		(*prcm)->cm1_abe_timer6_clkctrl,
-		(*prcm)->cm1_abe_timer7_clkctrl,
-		(*prcm)->cm1_abe_timer8_clkctrl,
-		(*prcm)->cm1_abe_wdt3_clkctrl,
-		(*prcm)->cm_l4per_gptimer9_clkctrl,
-		(*prcm)->cm_l4per_gptimer10_clkctrl,
-		(*prcm)->cm_l4per_gptimer11_clkctrl,
-		(*prcm)->cm_l4per_gptimer3_clkctrl,
-		(*prcm)->cm_l4per_gptimer4_clkctrl,
-		(*prcm)->cm_l4per_mcspi2_clkctrl,
-		(*prcm)->cm_l4per_mcspi3_clkctrl,
-		(*prcm)->cm_l4per_mcspi4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd3_clkctrl,
-		(*prcm)->cm_l4per_mmcsd4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd5_clkctrl,
-		(*prcm)->cm_l4per_uart1_clkctrl,
-		(*prcm)->cm_l4per_uart2_clkctrl,
-		(*prcm)->cm_l4per_uart4_clkctrl,
-		(*prcm)->cm_wkup_keyboard_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_cam_iss_clkctrl,
-		(*prcm)->cm_cam_fdif_clkctrl,
-		(*prcm)->cm_dss_dss_clkctrl,
-		(*prcm)->cm_sgx_sgx_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-	do_enable_clocks(clk_domains_non_essential,
-			 clk_modules_hw_auto_non_essential,
-			 clk_modules_explicit_en_non_essential,
-			 0);
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 const struct ctrl_ioregs ioregs_omap5430 = {
 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
@@ -639,6 +551,7 @@ void hw_data_init(void)
 	break;
 
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
 	*omap_vcores = &dra752_volts;
@@ -666,6 +579,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_omap5432_es2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		*regs = &ioregs_dra7xx_es1;
 		break;
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 5386ae0..737d23c 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -333,6 +333,9 @@ void init_omap_revision(void)
 	case DRA752_CONTROL_ID_CODE_ES1_0:
 		*omap_si_rev = DRA752_ES1_0;
 		break;
+	case DRA752_CONTROL_ID_CODE_ES1_1:
+		*omap_si_rev = DRA752_ES1_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 77c428b..ff32807 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -432,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_srcomp_code_latch		= 0x4A002E84,
 	.control_ddr_control_ext_0		= 0x4A002E88,
 	.control_padconf_core_base		= 0x4A003400,
+	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B24,
 	.control_port_emif1_sdram_config	= 0x4AE0C110,
 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
 	.control_port_emif2_sdram_config	= 0x4AE0C118,
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
+	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
 	.control_padconf_mode			= 0x4AE0C5A0,
 	.control_xtal_oscillator		= 0x4AE0C5A4,
 	.control_i2c_2				= 0x4AE0C5A8,
@@ -807,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_dsp_clkstctrl			= 0x4a005400,
 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
 
+	/* prm irqstatus regs */
+	.prm_irqstatus_mpu_2			= 0x4ae06014,
+
 	/* cm2.ckgen */
 	.cm_clksel_usb_60mhz			= 0x4a008104,
 	.cm_clkmode_dpll_per			= 0x4a008140,
@@ -967,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
+
+	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
+	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
 };
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2e18706..16a91f9 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -245,6 +245,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		switch (emif_nr) {
 		case 1:
 			*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
@@ -273,6 +274,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 	default:
 		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 	}
@@ -460,6 +462,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		if (emif_nr == 1) {
 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 			*size =
@@ -626,6 +629,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 			     sizeof(omap5_bug_00339_regs[0]);
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);
diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644
index 0000000..7f127b1
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/Makefile
@@ -0,0 +1,6 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
diff --git a/arch/arm/cpu/armv7/tegra124/config.mk b/arch/arm/cpu/armv7/tegra124/config.mk
new file mode 100644
index 0000000..2f1c645
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/config.mk
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+CONFIG_ARCH_DEVICE_TREE := tegra124
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds
new file mode 100644
index 0000000..a68b050
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	/*
+	 * Zynq needs to discard more sections because the user
+	 * is expected to pass this image on to tools for boot.bin
+	 * generation that require them to be dropped.
+	 */
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss*) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 60d71a6..91d70da 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -1,5 +1,5 @@
 /*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
 * NVIDIA Corporation <www.nvidia.com>
 *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -27,7 +27,7 @@ int tegra_get_chip(void)
 	/*
 	 * This is undocumented, Chip ID is bits 15:8 of the register
 	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-	 * Tegra30, and 0x35 for T114.
+	 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
 	 */
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
 	debug("%s: CHIPID is 0x%02X\n", __func__, rev);
@@ -72,6 +72,7 @@ int tegra_get_chip_sku(void)
 		case SKU_ID_T33:
 		case SKU_ID_T30:
 		case SKU_ID_TM30MQS_P_A3:
+		default:
 			return TEGRA_SOC_T30;
 		}
 		break;
@@ -79,10 +80,19 @@ int tegra_get_chip_sku(void)
 		switch (sku_id) {
 		case SKU_ID_T114_ENG:
 		case SKU_ID_T114_1:
+		default:
 			return TEGRA_SOC_T114;
 		}
 		break;
+	case CHIPID_TEGRA124:
+		switch (sku_id) {
+		case SKU_ID_T124_ENG:
+		default:
+			return TEGRA_SOC_T124;
+		}
+		break;
 	}
+
 	/* unknown chip/sku id */
 	printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
 		__func__, chip_id, sku_id);
@@ -117,8 +127,8 @@ static u32 get_odmdata(void)
 	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
 	 * The BCT start and size are stored in the BIT in IRAM.
 	 * Read the data @ bct_start + (bct_size - 12). This works
-	 * on T20 and T30 BCTs, which are locked down. If this changes
-	 * in new chips (T114, etc.), we can revisit this algorithm.
+	 * on BCTs for currently supported SoCs, which are locked down.
+	 * If this changes in new chips, we can revisit this algorithm.
 	 */
 
 	u32 bct_start, odmdata;
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index d9cbda8..6a6faf4 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -109,12 +109,18 @@ static int uart_configs[] = {
 	-1,
 	-1,
 	-1,
-#else	/* Tegra114 */
+#elif defined(CONFIG_TEGRA114)
 	-1,
 	-1,
 	-1,
 	FUNCMUX_UART4_GMI,	/* UARTD */
 	-1,
+#else	/* Tegra124 */
+	FUNCMUX_UART1_KBC,	/* UARTA */
+	-1,
+	-1,
+	FUNCMUX_UART4_GPIO,	/* UARTD */
+	-1,
 #endif
 };
 
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c
index 48e9319..94f5bce 100644
--- a/arch/arm/cpu/tegra-common/cache.c
+++ b/arch/arm/cpu/tegra-common/cache.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -23,8 +23,6 @@
 
 void config_cache(void)
 {
-	struct apb_misc_gp_ctlr *gp =
-		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	u32 reg = 0;
 
 	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
@@ -33,10 +31,10 @@ void config_cache(void)
 		"orr r0, r0, #0x41\n"
 		"mcr p15, 0, r0, c1, c0, 1\n");
 
-	/* Currently, only T114 needs this L2 cache change to boot Linux */
-	reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
-	if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+	/* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
+	if (tegra_get_chip() < CHIPID_TEGRA114)
 		return;
+
 	/*
 	 * Systems with an architectural L2 cache must not use the PL310.
 	 * Config L2CTLR here for a data RAM latency of 3 cycles.
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 268fb91..11c7435 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
 
 	value = readl(reg);
 
-	value &= ~OUT_CLK_SOURCE_MASK;
-	value |= source << OUT_CLK_SOURCE_SHIFT;
+	value &= ~OUT_CLK_SOURCE_31_30_MASK;
+	value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
 
 	value &= ~OUT_CLK_DIVISOR_MASK;
 	value |= divisor << OUT_CLK_DIVISOR_SHIFT;
@@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
 {
 	u32 *reg = get_periph_source_reg(periph_id);
 
-	clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-			source << OUT_CLK_SOURCE_SHIFT);
+	clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+			source << OUT_CLK_SOURCE_31_30_SHIFT);
 }
 
 /**
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
 	/* work out the source clock and set it */
 	if (source < 0)
 		return -1;
-	if (mux_bits == 4) {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
-			source << OUT_CLK_SOURCE4_SHIFT);
-	} else {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-			source << OUT_CLK_SOURCE_SHIFT);
+
+	switch (mux_bits) {
+	case MASK_BITS_31_30:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+				source << OUT_CLK_SOURCE_31_30_SHIFT);
+		break;
+
+	case MASK_BITS_31_29:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+				source << OUT_CLK_SOURCE_31_29_SHIFT);
+		break;
+
+	case MASK_BITS_31_28:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+				source << OUT_CLK_SOURCE_31_28_SHIFT);
+		break;
+
+	default:
+		return -1;
 	}
+
 	udelay(2);
 	return 0;
 }
@@ -561,3 +575,95 @@ void clock_init(void)
 	/* Do any special system timer/TSC setup */
 	arch_timer_init();
 }
+
+static void set_avp_clock_source(u32 src)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+	writel(val, &clkrst->crc_sclk_brst_pol);
+	udelay(3);
+}
+
+/*
+ * This function is useful on Tegra30, and any later SoCs that have compatible
+ * PLLP configuration registers.
+ */
+void tegra30_set_up_pllp(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	/*
+	 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
+	 * run up to 275MHz. On power on, the default sytem clock source is set
+	 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+	 * 408MHz which is beyond system clock's upper limit.
+	 *
+	 * The fix is to set the system clock to CLK_M before initializing PLLP,
+	 * and then switch back to PLLP_OUT4, which has an appropriate divider
+	 * configured, after PLLP has been configured
+	 */
+	set_avp_clock_source(SCLK_SOURCE_CLKM);
+
+	/*
+	 * PLLP output frequency set to 408Mhz
+	 * PLLC output frequency set to 228Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+
+	/* OUT1, 2 */
+	/* Assert RSTN before enable */
+	reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+	/* Set divisor and reenable */
+	reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
+		| PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
+		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+		| PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+	/* OUT3, 4 */
+	/* Assert RSTN before enable */
+	reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+	/* Set divisor and reenable */
+	reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+		| PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+		| PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+	set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
+}
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 5c4305a..d5194e1 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -61,12 +61,6 @@ enum {
 	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
 };
 
-enum {
-	MASK_BITS_31_30	= 2,	/* num of bits used to specify clock source */
-	MASK_BITS_31_29,
-	MASK_BITS_29_28,
-};
-
 /*
  * Clock source mux for each clock type. This just converts our enum into
  * a list of mux sources for use by the code.
@@ -109,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
 		MASK_BITS_31_29},
 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
-		MASK_BITS_29_28}
+		MASK_BITS_31_28}
 };
 
 /*
@@ -610,26 +604,24 @@ void clock_early_init(void)
 	struct clk_rst_ctlr *clkrst =
 		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
+	tegra30_set_up_pllp();
+
 	/*
-	 * PLLP output frequency set to 408Mhz
 	 * PLLC output frequency set to 600Mhz
 	 * PLLD output frequency set to 925Mhz
 	 */
 	switch (clock_get_osc_freq()) {
 	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
 		break;
 
 	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
 		break;
 
 	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
 		break;
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
new file mode 100644
index 0000000..ff77992
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= clock.o
+obj-y	+= funcmux.o
+obj-y	+= pinmux.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
new file mode 100644
index 0000000..7394363
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/clock.c
@@ -0,0 +1,826 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_PC2CC3M,
+	CLOCK_TYPE_PC2CC3S_T,
+	CLOCK_TYPE_PC2CC3M_T,
+	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
+	CLOCK_TYPE_MC2CC3P_A,
+	CLOCK_TYPE_M,
+	CLOCK_TYPE_MCPTM2C2C3,
+	CLOCK_TYPE_PC2CC3T_S,
+	CLOCK_TYPE_AC2CC3P_TS2,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
+		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
+		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_28},
+
+	/* Additional clock types on Tegra114+ */
+	/* CLOCK_TYPE_PC2CC3M */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3S_T */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(SFROM32KHZ), CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3M_T */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_MC2CC3P_A */
+	{ CLK(MEMORY),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(PERIPH),	CLK(NONE),	CLK(AUDIO),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_M */
+	{ CLK(MEMORY),		CLK(NONE),	CLK(NONE),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	/* CLOCK_TYPE_MCPTM2C2C3 */
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(MEMORY2),	CLK(CGENERAL2),	CLK(CGENERAL3),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3T_S */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(OSC),	CLK(NONE),	CLK(SFROM32KHZ), CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_AC2CC3P_TS2 */
+	{ CLK(AUDIO),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(PERIPH),	CLK(NONE),	CLK(OSC),	CLK(SRC2),
+		MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PC2CC3M),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_05h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x08 */
+	TYPE(PERIPHC_08h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_0bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_0ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_10h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_11h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_13h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_16h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_17h,	CLOCK_TYPE_NONE),
+
+	/* 0x18 */
+	TYPE(PERIPHC_18h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_1Bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_1Ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_HSI,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_21h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_22h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_24h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_25h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPTM2C2C3),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_29h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_SENSOR,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_2bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_2ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_I2S0,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_DTV,	CLOCK_TYPE_NONE),
+
+	/* 0x38 */
+	TYPE(PERIPHC_38h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_39h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_3ah,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_3bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_MSENC,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_TSEC,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_3eh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_OSC,	CLOCK_TYPE_NONE),
+
+	/* 0x40 */
+	TYPE(PERIPHC_40h,	CLOCK_TYPE_NONE),	/* start with 0x3b0 */
+	TYPE(PERIPHC_MSELECT,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_TSENSOR,	CLOCK_TYPE_PC2CC3T_S),
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x48 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_49h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_52h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_55h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_56h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_57h,	CLOCK_TYPE_NONE),
+
+	/* 0x58 */
+	TYPE(PERIPHC_58h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_59h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_5ah,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_5bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_5fh,	CLOCK_TYPE_NONE),
+
+	/* 0x60 */
+	TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_FS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_SS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILAB,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILCD,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILE,	CLOCK_TYPE_NONE),
+
+	/* 0x68 */
+	TYPE(PERIPHC_DSIA_LP,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DSIB_LP,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ENTROPY,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DVFS_REF,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DVFS_SOC,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ADX0,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_AMX0,	CLOCK_TYPE_NONE),
+
+	/* 0x70 */
+	TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SOC_THERM,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_72h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_73h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_74h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_75h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C6,	CLOCK_TYPE_PC2CC3M_T16),
+
+	/* 0x78 */
+	TYPE(PERIPHC_78h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_EMC_DLL,	CLOCK_TYPE_MCPTM2C2C3),
+	TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CLK72MHZ,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ADX1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_AMX1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_VIC,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_7Fh,	CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(ISPB),
+	NONE(RESERVED4),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	NONE(RESERVED13),
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(TCW),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	NONE(RESERVED19),
+	PERIPHC_VI,
+	NONE(RESERVED21),
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(FUSE),
+
+	/* 40 */
+	NONE(KFUSE),
+	PERIPHC_SBC1,		/* SBCx = SPIx */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(XIO),
+	PERIPHC_SBC3,
+	PERIPHC_I2C5,
+
+	/* 48 */
+	NONE(DSI),
+	NONE(RESERVED49),
+	PERIPHC_HSI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	NONE(RESERVED53),
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(MIPI_CAL),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	NONE(RESERVED60),
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	NONE(RESERVED64),
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(LA),
+	NONE(TRACECLKIN),
+	NONE(SOC_THERM),
+	NONE(DTV),
+
+	/* 80 */
+	NONE(RESERVED80),
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	PERIPHC_TSEC,
+	NONE(RESERVED84),
+	NONE(RESERVED85),
+	NONE(RESERVED86),
+	NONE(EMUCIF),
+
+	/* 88 */
+	NONE(RESERVED88),
+	NONE(XUSB_HOST),
+	NONE(RESERVED90),
+	PERIPHC_MSENC,
+	NONE(RESERVED92),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(XUSB_DEV),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	NONE(V_RESERVED2),
+	PERIPHC_MSELECT,
+	NONE(V_RESERVED4),
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 104 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 112 */
+	NONE(ATOMICS),
+	NONE(V_RESERVED17),
+	NONE(V_RESERVED18),
+	NONE(V_RESERVED19),
+	NONE(V_RESERVED20),
+	NONE(V_RESERVED21),
+	NONE(V_RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 120 */
+	NONE(EXTPERIPH1),
+	NONE(EXTPERIPH2),
+	NONE(EXTPERIPH3),
+	NONE(OOB),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(TZRAM),
+	NONE(SE),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(SATACOLD),
+	NONE(W_RESERVED2),
+	NONE(W_RESERVED3),
+	NONE(W_RESERVED4),
+	NONE(W_RESERVED5),
+	NONE(W_RESERVED6),
+	NONE(W_RESERVED7),
+
+	/* 136 */
+	NONE(CEC),
+	NONE(W_RESERVED9),
+	NONE(W_RESERVED10),
+	NONE(W_RESERVED11),
+	NONE(W_RESERVED12),
+	NONE(W_RESERVED13),
+	NONE(XUSB_PADCTL),
+	NONE(W_RESERVED15),
+
+	/* 144 */
+	NONE(W_RESERVED16),
+	NONE(W_RESERVED17),
+	NONE(W_RESERVED18),
+	NONE(W_RESERVED19),
+	NONE(W_RESERVED20),
+	NONE(ENTROPY),
+	NONE(DDS),
+	NONE(W_RESERVED23),
+
+	/* 152 */
+	NONE(DP2),
+	NONE(AMX0),
+	NONE(ADX0),
+	NONE(DVFS),
+	NONE(XUSB_SS),
+	NONE(W_RESERVED29),
+	NONE(W_RESERVED30),
+	NONE(W_RESERVED31),
+
+	/* X word: 31:0 */
+	NONE(SPARE),
+	NONE(X_RESERVED1),
+	NONE(X_RESERVED2),
+	NONE(X_RESERVED3),
+	NONE(CAM_MCLK),
+	NONE(CAM_MCLK2),
+	PERIPHC_I2C6,
+	NONE(X_RESERVED7),
+
+	/* 168 */
+	NONE(X_RESERVED8),
+	NONE(X_RESERVED9),
+	NONE(X_RESERVED10),
+	NONE(VIM2_CLK),
+	NONE(X_RESERVED12),
+	NONE(X_RESERVED13),
+	NONE(EMC_DLL),
+	NONE(X_RESERVED15),
+
+	/* 176 */
+	NONE(HDMI_AUDIO),
+	NONE(CLK72MHZ),
+	NONE(VIC),
+	NONE(X_RESERVED19),
+	NONE(ADX1),
+	NONE(DPAUX),
+	NONE(SOR0),
+	NONE(X_RESERVED23),
+
+	/* 184 */
+	NONE(GPU),
+	NONE(AMX1),
+	NONE(X_RESERVED26),
+	NONE(X_RESERVED27),
+	NONE(X_RESERVED28),
+	NONE(X_RESERVED29),
+	NONE(X_RESERVED30),
+	NONE(X_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)				/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else {
+		return &clkrst->crc_clk_src[internal_id];
+	}
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PC2CC3M_T16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+	       parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra124 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED4:
+	case PERIPH_ID_RESERVED25:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED36:
+	case PERIPH_ID_RESERVED38:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED49:
+	case PERIPH_ID_RESERVED53:
+	case PERIPH_ID_RESERVED64:
+	case PERIPH_ID_RESERVED84:
+	case PERIPH_ID_RESERVED85:
+	case PERIPH_ID_RESERVED86:
+	case PERIPH_ID_RESERVED88:
+	case PERIPH_ID_RESERVED90:
+	case PERIPH_ID_RESERVED92:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_V_RESERVED2:
+	case PERIPH_ID_V_RESERVED4:
+	case PERIPH_ID_V_RESERVED17:
+	case PERIPH_ID_V_RESERVED18:
+	case PERIPH_ID_V_RESERVED19:
+	case PERIPH_ID_V_RESERVED20:
+	case PERIPH_ID_V_RESERVED21:
+	case PERIPH_ID_V_RESERVED22:
+	case PERIPH_ID_W_RESERVED2:
+	case PERIPH_ID_W_RESERVED3:
+	case PERIPH_ID_W_RESERVED4:
+	case PERIPH_ID_W_RESERVED5:
+	case PERIPH_ID_W_RESERVED6:
+	case PERIPH_ID_W_RESERVED7:
+	case PERIPH_ID_W_RESERVED9:
+	case PERIPH_ID_W_RESERVED10:
+	case PERIPH_ID_W_RESERVED11:
+	case PERIPH_ID_W_RESERVED12:
+	case PERIPH_ID_W_RESERVED13:
+	case PERIPH_ID_W_RESERVED15:
+	case PERIPH_ID_W_RESERVED16:
+	case PERIPH_ID_W_RESERVED17:
+	case PERIPH_ID_W_RESERVED18:
+	case PERIPH_ID_W_RESERVED19:
+	case PERIPH_ID_W_RESERVED20:
+	case PERIPH_ID_W_RESERVED23:
+	case PERIPH_ID_W_RESERVED29:
+	case PERIPH_ID_W_RESERVED30:
+	case PERIPH_ID_W_RESERVED31:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	tegra30_set_up_pllp();
+
+	/*
+	 * PLLC output frequency set to 600Mhz
+	 * PLLD output frequency set to 925Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+	/* PLLC_MISC: Set LOCK_ENABLE */
+	writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+	udelay(2);
+
+	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+	udelay(2);
+}
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only Tegra114+ has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
new file mode 100644
index 0000000..d19fda0
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/funcmux.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART4:
+		switch (config) {
+		case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+			pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+
+			pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
+			pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
+			pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+
+			pinmux_tristate_disable(PINGRP_GPIO_PJ7);
+			pinmux_tristate_disable(PINGRP_GPIO_PB0);
+			pinmux_tristate_disable(PINGRP_GPIO_PB1);
+			pinmux_tristate_disable(PINGRP_GPIO_PK7);
+			break;
+		}
+		break;
+
+	case PERIPH_ID_UART1:
+		switch (config) {
+		case FUNCMUX_UART1_KBC:
+			pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+
+			pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+
+			pinmux_tristate_disable(PINGRP_KB_ROW9);
+			pinmux_tristate_disable(PINGRP_KB_ROW10);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
new file mode 100644
index 0000000..a4ab4ea
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -0,0 +1,730 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+	const char *name;
+	enum pmux_func funcs[4];
+	enum pmux_func func_safe;
+	enum pmux_vddio vddio;
+	enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT	0
+#define PMUX_PULL_SHIFT		2
+#define PMUX_TRISTATE_SHIFT	4
+#define PMUX_TRISTATE_MASK	(1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT		5
+#define PMUX_OD_SHIFT		6
+#define PMUX_LOCK_SHIFT		7
+#define PMUX_IO_RESET_SHIFT	8
+#define PMUX_RCV_SEL_SHIFT	9
+
+#define PGRP_HSM_SHIFT		2
+#define PGRP_SCHMT_SHIFT	3
+#define PGRP_LPMD_SHIFT		4
+#define PGRP_LPMD_MASK		(3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT	12
+#define PGRP_DRVDN_MASK		(0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT	20
+#define PGRP_DRVUP_MASK		(0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT		28
+#define PGRP_SLWR_MASK		(3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT		30
+#define PGRP_SLWF_MASK		(3 << PGRP_SLWF_SHIFT)
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
+	{						\
+		.vddio = PMUX_VDDIO_ ## vdd,		\
+		.funcs = {				\
+			PMUX_FUNC_ ## f0,		\
+			PMUX_FUNC_ ## f1,		\
+			PMUX_FUNC_ ## f2,		\
+			PMUX_FUNC_ ## f3,		\
+		},					\
+		.func_safe = PMUX_FUNC_RSVD1,		\
+		.io = PMUX_PIN_ ## iod,			\
+	}
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+	PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+	/*	NAME	  VDD	   f0		f1	   f2	    f3  */
+	PINI(ULPI_DATA0,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA1,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA2,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA3,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA4,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_CLK,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_DIR,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_NXT,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_STP,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(DAP3_FS,     BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_DIN,    BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_DOUT,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_SCLK,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(GPIO_PV0,    BB,      USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PV1,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,     CLK12,      RSVD3,   RSVD4),
+	PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+	PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+	PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
+	PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
+	PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
+	PIN_RESERVED,	/* Reserved: 0x3060 - 0x3064 */
+	PIN_RESERVED,
+	PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x3070 - 0x310c */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x311c - 0x3160 */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+	PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+	PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+	PINI(UART2_CTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+	PINI(UART3_TXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+	PINI(UART3_RXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+	PINI(UART3_CTS_N, UART,    UARTC,      SDMMC1,     DTV,     SPI4),
+	PINI(UART3_RTS_N, UART,    UARTC,      PWM0,       DTV,     DISPA),
+	PINI(GPIO_PU0,    UART,    OWR,        UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU1,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU2,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU3,    UART,    PWM0,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU4,    UART,    PWM1,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU5,    UART,    PWM2,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU6,    UART,    PWM3,       UARTA,      USB,     DISPB),
+	PINI(GEN1_I2C_SDA, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GEN1_I2C_SCL, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP4_FS,     UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+	PINI(DAP4_DIN,    UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP4_DOUT,   UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+	PINI(DAP4_SCLK,   UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK3_OUT,    UART,    EXTPERIPH3, RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK3_REQ,    UART,    DEV3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GMI_WP_N,    GMI,     RSVD1,      NAND,       GMI,     GMI_ALT),
+	PINI(GMI_IORDY,   GMI,     SDMMC2,     RSVD2,      GMI,     TRACE),
+	PINI(GMI_WAIT,    GMI,     SPI4,       NAND,       GMI,     DTV),
+	PINI(GMI_ADV_N,   GMI,     RSVD1,      NAND,       GMI,     TRACE),
+	PINI(GMI_CLK,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_CS0_N,   GMI,     RSVD1,      NAND,       GMI,     USB),
+	PINI(GMI_CS1_N,   GMI,     RSVD1,      NAND,       GMI,     SOC),
+	PINI(GMI_CS2_N,   GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_CS3_N,   GMI,     SDMMC2,     NAND,       GMI,     GMI_ALT),
+	PINI(GMI_CS4_N,   GMI,     USB,        NAND,       GMI,     TRACE),
+	PINI(GMI_CS6_N,   GMI,     NAND,       NAND_ALT,   GMI,     SPI4),
+	PINI(GMI_CS7_N,   GMI,     NAND,       NAND_ALT,   GMI,     SDMMC2),
+	PINI(GMI_AD0,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD1,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD2,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD3,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD4,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD5,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD6,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD7,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD8,     GMI,     PWM0,       NAND,       GMI,     DTV),
+	PINI(GMI_AD9,     GMI,     PWM1,       NAND,       GMI,     CLDVFS),
+	PINI(GMI_AD10,    GMI,     PWM2,       NAND,       GMI,     CLDVFS),
+	PINI(GMI_AD11,    GMI,     PWM3,       NAND,       GMI,     USB),
+	PINI(GMI_AD12,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+	PINI(GMI_AD13,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+	PINI(GMI_AD14,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+	PINI(GMI_AD15,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+	PINI(GMI_A16,     GMI,     UARTD,      TRACE,      GMI,     GMI_ALT),
+	PINI(GMI_A17,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+	PINI(GMI_A18,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+	PINI(GMI_A19,     GMI,     UARTD,      SPI4,       GMI,     TRACE),
+	PINI(GMI_WR_N,    GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_OE_N,    GMI,     RSVD1,      NAND,       GMI,     SOC),
+	PINI(GMI_DQS,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_RST_N,   GMI,     NAND,       NAND_ALT,   GMI,     RSVD4),
+	PINI(GEN2_I2C_SCL, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+	PINI(GEN2_I2C_SDA, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_CLK,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_CMD,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_DAT0, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT1, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT2, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT3, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT4, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x3280 */
+	PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT3, RSVD4),
+	PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
+	PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
+	PINI(CAM_I2C_SDA, CAM,     VGP2,       I2C3,       RSVD3,   RSVD4),
+	PINI(GPIO_PBB3,   CAM,     VGP3,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB4,   CAM,     VGP4,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB5,   CAM,     VGP5,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB6,   CAM,     VGP6,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB7,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PCC2,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(JTAG_RTCK,   SYS,     RTCK,       RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_I2C_SCL, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_I2C_SDA, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW0,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+	PINI(KB_ROW1,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+	PINI(KB_ROW2,     SYS,     KBC,        RSVD2,      DTV,     SOC),
+	PINI(KB_ROW3,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+	PINI(KB_ROW4,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+	PINI(KB_ROW5,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+	PINI(KB_ROW6,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+	PINI(KB_ROW7,     SYS,     KBC,        RSVD2,      CLDVFS,  UARTA),
+	PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PIN_RESERVED,	/* Reserved: 0x32e8 - 0x32f8 */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
+	PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
+	PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(KB_COL3,     SYS,     KBC,        DISPA,      PWM2,    UARTA),
+	PINI(KB_COL4,     SYS,     KBC,        OWR,        SDMMC3,  UARTA),
+	PINI(KB_COL5,     SYS,     KBC,        RSVD2,      SDMMC1,  RSVD4),
+	PINI(KB_COL6,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(KB_COL7,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(CLK_32K_OUT, SYS,     BLINK,      SOC,        RSVD3,   RSVD4),
+	PINI(SYS_CLK_REQ, SYS,     SYSCLK,     RSVD2,      RSVD3,   RSVD4),
+	PINI(CORE_PWR_REQ, SYS,    PWRON,      RSVD2,      RSVD3,   RSVD4),
+	PINI(CPU_PWR_REQ, SYS,     CPU,        RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_INT_N,   SYS,     PMI,        RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK_32K_IN,  SYS,     CLK,        RSVD2,      RSVD3,   RSVD4),
+	PINI(OWR,         SYS,     OWR,        RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP1_FS,     AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_DIN,    AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_DOUT,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_SCLK,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(CLK1_REQ,    AUDIO,   DAP,        DAP1,       RSVD3,   RSVD4),
+	PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1, DAP2,       RSVD3,   RSVD4),
+	PINI(SPDIF_IN,    AUDIO,   SPDIF,      USB,        RSVD3,   RSVD4),
+	PINI(SPDIF_OUT,   AUDIO,   SPDIF,      RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP2_FS,     AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DVFS_PWM,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+	PINI(GPIO_X1_AUD, AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_X3_AUD, AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
+	PINI(DVFS_CLK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+	PINI(GPIO_X4_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
+	PINI(GPIO_X5_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+	PINI(GPIO_X6_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
+	PINI(GPIO_X7_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+	PIN_RESERVED,   /* Reserved: 0x3388 - 0x338c */
+	PIN_RESERVED,
+	PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+	PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
+	PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+	PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
+	PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
+	PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
+	PIN_RESERVED,   /* Reserved: 0x33a8 - 0x33dc */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
+	PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
+	PINI(SDMMC3_CD_N, SYS,  SDMMC3,     OWR,        RSVD3,   RSVD4),
+	PINI(GPIO_W2_AUD, AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
+	PINI(GPIO_W3_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
+	PINI(USB_VBUS_EN0, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(USB_VBUS_EN1, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+	PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x3404 */
+	PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *tri = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin */
+	assert(pmux_pingrp_isvalid(pin));
+
+	reg = readl(tri);
+	if (enable)
+		reg |= PMUX_TRISTATE_MASK;
+	else
+		reg &= ~PMUX_TRISTATE_MASK;
+	writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pull = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and pupd */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_pupd_isvalid(pupd));
+
+	reg = readl(pull);
+	reg &= ~(0x3 << PMUX_PULL_SHIFT);
+	reg |= (pupd << PMUX_PULL_SHIFT);
+	writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *muxctl = &pmt->pmt_ctl[pin];
+	int i, mux = -1;
+	u32 reg;
+
+	/* Error check on pin and func */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_func_isvalid(func));
+
+	/* Handle special values */
+	if (func == PMUX_FUNC_SAFE)
+		func = tegra_soc_pingroups[pin].func_safe;
+
+	if (func & PMUX_FUNC_RSVD1) {
+		mux = func & 0x3;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 4; i++) {
+			if (tegra_soc_pingroups[pin].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	reg = readl(muxctl);
+	reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+	reg |= (mux << PMUX_MUXCTL_SHIFT);
+	writel(reg, muxctl);
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_io = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and io */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_io_isvalid(io));
+
+	reg = readl(pin_io);
+	reg &= ~(0x1 << PMUX_IO_SHIFT);
+	reg |= (io & 0x1) << PMUX_IO_SHIFT;
+	writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_lock = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and lock */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_lock_isvalid(lock));
+
+	if (lock == PMUX_PIN_LOCK_DEFAULT)
+		return 0;
+
+	reg = readl(pin_lock);
+	reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+	if (lock == PMUX_PIN_LOCK_ENABLE) {
+		reg |= (0x1 << PMUX_LOCK_SHIFT);
+	} else {
+		/* lock == DISABLE, which isn't possible */
+		printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+		       __func__, lock);
+	}
+	writel(reg, pin_lock);
+
+	return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_od = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and od */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_od_isvalid(od));
+
+	if (od == PMUX_PIN_OD_DEFAULT)
+		return 0;
+
+	reg = readl(pin_od);
+	reg &= ~(0x1 << PMUX_OD_SHIFT);
+	if (od == PMUX_PIN_OD_ENABLE)
+		reg |= (0x1 << PMUX_OD_SHIFT);
+	writel(reg, pin_od);
+
+	return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+				enum pmux_pin_ioreset ioreset)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and ioreset */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_ioreset_isvalid(ioreset));
+
+	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+		return 0;
+
+	reg = readl(pin_ioreset);
+	reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+		reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+	writel(reg, pin_ioreset);
+
+	return 0;
+}
+
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+				enum pmux_pin_rcv_sel rcv_sel)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and rcv_sel */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+	if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+		return 0;
+
+	reg = readl(pin_rcv_sel);
+	reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+	if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+		reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+	writel(reg, pin_rcv_sel);
+
+	return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+	enum pmux_pingrp pin = config->pingroup;
+
+	pinmux_set_func(pin, config->func);
+	pinmux_set_pullupdown(pin, config->pull);
+	pinmux_set_tristate(pin, config->tristate);
+	pinmux_set_io(pin, config->io);
+	pinmux_set_lock(pin, config->lock);
+	pinmux_set_od(pin, config->od);
+	pinmux_set_ioreset(pin, config->ioreset);
+	pinmux_set_rcv_sel(pin, config->rcv_sel);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_pingroup(&config[i]);
+}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_slwf = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and slwf */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_slw_isvalid(slwf));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (slwf == PGRP_SLWF_NONE)
+		return 0;
+
+	reg = readl(pad_slwf);
+	reg &= ~PGRP_SLWF_MASK;
+	reg |= (slwf << PGRP_SLWF_SHIFT);
+	writel(reg, pad_slwf);
+
+	return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_slwr = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and slwr */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_slw_isvalid(slwr));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (slwr == PGRP_SLWR_NONE)
+		return 0;
+
+	reg = readl(pad_slwr);
+	reg &= ~PGRP_SLWR_MASK;
+	reg |= (slwr << PGRP_SLWR_SHIFT);
+	writel(reg, pad_slwr);
+
+	return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_drvup = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and drvup */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_drv_isvalid(drvup));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (drvup == PGRP_DRVUP_NONE)
+		return 0;
+
+	reg = readl(pad_drvup);
+	reg &= ~PGRP_DRVUP_MASK;
+	reg |= (drvup << PGRP_DRVUP_SHIFT);
+	writel(reg, pad_drvup);
+
+	return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_drvdn = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and drvdn */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_drv_isvalid(drvdn));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (drvdn == PGRP_DRVDN_NONE)
+		return 0;
+
+	reg = readl(pad_drvdn);
+	reg &= ~PGRP_DRVDN_MASK;
+	reg |= (drvdn << PGRP_DRVDN_SHIFT);
+	writel(reg, pad_drvdn);
+
+	return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_lpmd = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check pad and lpmd value */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_lpmd_isvalid(lpmd));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (lpmd == PGRP_LPMD_NONE)
+		return 0;
+
+	reg = readl(pad_lpmd);
+	reg &= ~PGRP_LPMD_MASK;
+	reg |= (lpmd << PGRP_LPMD_SHIFT);
+	writel(reg, pad_lpmd);
+
+	return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_schmt = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check pad */
+	assert(pmux_padgrp_isvalid(pad));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (schmt == PGRP_SCHMT_NONE)
+		return 0;
+
+	reg = readl(pad_schmt);
+	reg &= ~(1 << PGRP_SCHMT_SHIFT);
+	if (schmt == PGRP_SCHMT_ENABLE)
+		reg |= (0x1 << PGRP_SCHMT_SHIFT);
+	writel(reg, pad_schmt);
+
+	return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_hsm = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check pad */
+	assert(pmux_padgrp_isvalid(pad));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (hsm == PGRP_HSM_NONE)
+		return 0;
+
+	reg = readl(pad_hsm);
+	reg &= ~(1 << PGRP_HSM_SHIFT);
+	if (hsm == PGRP_HSM_ENABLE)
+		reg |= (0x1 << PGRP_HSM_SHIFT);
+	writel(reg, pad_hsm);
+
+	return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+	enum pdrive_pingrp pad = config->padgrp;
+
+	padgrp_set_drvup_slwf(pad, config->slwf);
+	padgrp_set_drvdn_slwr(pad, config->slwr);
+	padgrp_set_drvup(pad, config->drvup);
+	padgrp_set_drvdn(pad, config->drvdn);
+	padgrp_set_lpmd(pad, config->lpmd);
+	padgrp_set_schmt(pad, config->schmt);
+	padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		padctrl_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index 34124f9..0c4f5fb 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -412,9 +412,9 @@ int get_periph_clock_source(enum periph_id periph_id,
 	 * with its 16-bit divisor
 	 */
 	if (type == CLOCK_TYPE_PCXTS)
-		*mux_bits = 4;
+		*mux_bits = MASK_BITS_31_28;
 	else
-		*mux_bits = 2;
+		*mux_bits = MASK_BITS_31_30;
 	if (type == CLOCK_TYPE_PCMT16)
 		*divider_bits = 16;
 	else
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
index 74bd22b..80ba2d8 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -60,12 +60,6 @@ enum {
 	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
 };
 
-enum {
-	MASK_BITS_31_30 = 2,    /* num of bits used to specify clock source */
-	MASK_BITS_31_29,
-	MASK_BITS_29_28,
-};
-
 /*
  * Clock source mux for each clock type. This just converts our enum into
  * a list of mux sources for use by the code.
@@ -108,7 +102,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
 		MASK_BITS_31_29},
 	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
 		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
-		MASK_BITS_29_28}
+		MASK_BITS_31_28}
 };
 
 /*
@@ -587,34 +581,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)
 
 void clock_early_init(void)
 {
-	/*
-	 * PLLP output frequency set to 408Mhz
-	 * PLLC output frequency set to 228Mhz
-	 */
-	switch (clock_get_osc_freq()) {
-	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
-		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
-		break;
-
-	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
-		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
-		break;
-
-	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
-		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
-		break;
-	case CLOCK_OSC_FREQ_19_2:
-	default:
-		/*
-		 * These are not supported. It is too early to print a
-		 * message and the UART likely won't work anyway due to the
-		 * oscillator being wrong.
-		 */
-		break;
-	}
+	tegra30_set_up_pllp();
 }
 
 void arch_timer_init(void)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 626cc3c..f52fcf1 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -139,7 +139,7 @@
 
 	spi@7000d800 {
 		compatible = "nvidia,tegra114-spi";
-		reg = <0x7000d480 0x200>;
+		reg = <0x7000d800 0x200>;
 		interrupts = <0 83 0x04>;
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
new file mode 100644
index 0000000..18a8b24
--- /dev/null
+++ b/arch/arm/dts/tegra124.dtsi
@@ -0,0 +1,250 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra124";
+
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra124-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma@60020000 {
+		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+		reg = <0x60020000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
+		reg = <0x6000d000 0x1000>;
+		interrupts = <0 32 0x04
+			      0 33 0x04
+			      0 34 0x04
+			      0 35 0x04
+			      0 55 0x04
+			      0 87 0x04
+			      0 89 0x04
+			      0 125 0x04>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	i2c@7000c000 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>;
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>;
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>;
+		status = "disabled";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>;
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	i2c@7000d100 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000d100 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 41>;
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 44>;
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d800 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 46>;
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 68>;
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 104>;
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 105>;
+	};
+
+	sdhci@700b0000 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
+	};
+
+	sdhci@700b0200 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
+	};
+
+	sdhci@700b0400 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
+	};
+
+	sdhci@700b0600 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
+	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = < 52 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = < 53 >;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = < 129 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index c1777df..fbe599d 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -43,7 +43,7 @@
 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define MT41J128MJT125_EMIF_READ_LATENCY	0x06
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
 #define MT41J128MJT125_EMIF_TIM1		0x0888A39B
 #define MT41J128MJT125_EMIF_TIM2		0x26337FDA
 #define MT41J128MJT125_EMIF_TIM3		0x501F830F
@@ -65,7 +65,7 @@
 #define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
 
 /* Micron MT41J256M8HX-15E */
-#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x06
+#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
 #define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
 #define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
@@ -97,7 +97,7 @@
 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
-#define MT41J512M8RH125_EMIF_READ_LATENCY	0x06
+#define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
 #define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
 #define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
@@ -113,7 +113,7 @@
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
 /* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x07
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
 #define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
 #define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
 #define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 38cb42a..dded857 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -143,7 +143,7 @@ struct bcm2835_mbox_tag_get_arm_mem {
 #define BCM2835_MBOX_POWER_DEVID_SPI		7
 #define BCM2835_MBOX_POWER_DEVID_CCP2TX		8
 
-#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 1)
+#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 0)
 /* Device doesn't exist */
 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV	(1 << 1)
 
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 573f755..bccce63 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -185,9 +185,11 @@ static inline int s5p_get_cpu_rev(void)
 
 static inline void s5p_set_cpu_id(void)
 {
-	unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+	unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+	unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+	unsigned int cpu_rev = pro_id & 0x000000FF;
 
-	switch (pro_id) {
+	switch (cpu_id) {
 	case 0x200:
 		/* Exynos4210 EVT0 */
 		s5p_cpu_id = 0x4210;
@@ -196,10 +198,12 @@ static inline void s5p_set_cpu_id(void)
 	case 0x210:
 		/* Exynos4210 EVT1 */
 		s5p_cpu_id = 0x4210;
+		s5p_cpu_rev = cpu_rev;
 		break;
 	case 0x412:
 		/* Exynos4412 */
 		s5p_cpu_id = 0x4412;
+		s5p_cpu_rev = cpu_rev;
 		break;
 	case 0x520:
 		/* Exynos5250 */
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 2a19852..d6868fa 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -247,180 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 
 /* GPIO pins per bank  */
 #define GPIO_PER_BANK 8
-
-#define exynos4_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
-			       EXYNOS4_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
-				EXYNOS4_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
-
-#define exynos4x12_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
-			       EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
-				EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
-
-#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part3_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
-				EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
-	    - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
-
-#define exynos5_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
-			       EXYNOS5_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
-				EXYNOS5_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
-
-#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part3_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
-				EXYNOS5_GPIO_PART3_BASE)->bank)) \
-	    - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
-
-
-/* EXYNOS5420 */
-#define exynos5420_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
-			       EXYNOS5420_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
-				EXYNOS5420_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
-
-#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part3_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
-				EXYNOS5420_GPIO_PART3_BASE)->bank)) \
-	    - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
-
-#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part4_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
-				EXYNOS5420_GPIO_PART4_BASE)->bank)) \
-	    - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
-
-#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-static inline unsigned int s5p_gpio_base(int nr)
+#define S5P_GPIO_PART_SHIFT	(24)
+#define S5P_GPIO_PART_MASK	(0xff)
+#define S5P_GPIO_BANK_SHIFT	(8)
+#define S5P_GPIO_BANK_MASK	(0xffff)
+#define S5P_GPIO_PIN_MASK	(0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+			((x) & S5P_GPIO_PIN_MASK)
+
+#define EXYNOS4_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos4_gpio_part##part *) \
+			EXYNOS4_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS4_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
+			EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS4X12_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS5_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS5420_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define exynos4_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS4_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos4x12_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos5420_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS5420_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos5_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS5_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int gpio)
 {
-	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420()) {
-			if (nr < EXYNOS5420_GPIO_PART1_MAX)
-				return EXYNOS5420_GPIO_PART1_BASE;
-			else if (nr < EXYNOS5420_GPIO_PART2_MAX)
-				return EXYNOS5420_GPIO_PART2_BASE;
-			else if (nr < EXYNOS5420_GPIO_PART3_MAX)
-				return EXYNOS5420_GPIO_PART3_BASE;
-			else
-				return EXYNOS5420_GPIO_PART4_BASE;
-		} else {
-			if (nr < EXYNOS5_GPIO_PART1_MAX)
-				return EXYNOS5_GPIO_PART1_BASE;
-			else if (nr < EXYNOS5_GPIO_PART2_MAX)
-				return EXYNOS5_GPIO_PART2_BASE;
-			else
-				return EXYNOS5_GPIO_PART3_BASE;
-		}
-	} else if (cpu_is_exynos4()) {
-		if (nr < EXYNOS4_GPIO_PART1_MAX)
-			return EXYNOS4_GPIO_PART1_BASE;
-		else
-			return EXYNOS4_GPIO_PART2_BASE;
+	unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
+
+	switch (gpio_part) {
+	case 1:
+		return samsung_get_base_gpio_part1();
+	case 2:
+		return samsung_get_base_gpio_part2();
+	case 3:
+		return samsung_get_base_gpio_part3();
+	case 4:
+		return samsung_get_base_gpio_part4();
+	default:
+		return 0;
 	}
-
-	return 0;
-}
-
-static inline unsigned int s5p_gpio_part_max(int nr)
-{
-	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420()) {
-			if (nr < EXYNOS5420_GPIO_PART1_MAX)
-				return 0;
-			else if (nr < EXYNOS5420_GPIO_PART2_MAX)
-				return EXYNOS5420_GPIO_PART1_MAX;
-			else if (nr < EXYNOS5420_GPIO_PART3_MAX)
-				return EXYNOS5420_GPIO_PART2_MAX;
-			else if (nr < EXYNOS5420_GPIO_PART4_MAX)
-				return EXYNOS5420_GPIO_PART3_MAX;
-			else
-				return EXYNOS5420_GPIO_PART4_MAX;
-		} else {
-			if (nr < EXYNOS5_GPIO_PART1_MAX)
-				return 0;
-			else if (nr < EXYNOS5_GPIO_PART2_MAX)
-				return EXYNOS5_GPIO_PART1_MAX;
-			else
-				return EXYNOS5_GPIO_PART2_MAX;
-		}
-	} else if (cpu_is_exynos4()) {
-		if (proid_is_exynos4412()) {
-			if (nr < EXYNOS4X12_GPIO_PART1_MAX)
-				return 0;
-			else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
-				return EXYNOS4X12_GPIO_PART1_MAX;
-			else
-				return EXYNOS4X12_GPIO_PART2_MAX;
-		} else {
-			if (nr < EXYNOS4_GPIO_PART1_MAX)
-				return 0;
-			else
-				return EXYNOS4_GPIO_PART1_MAX;
-		}
-	}
-
-	return 0;
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 30c7f18..5c1c3d4 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -36,7 +36,6 @@ enum periph_id {
 	PERIPH_ID_SDMMC3,
 	PERIPH_ID_I2C8 = 87,
 	PERIPH_ID_I2C9,
-	PERIPH_ID_I2C10 = 203,
 	PERIPH_ID_I2S0 = 98,
 	PERIPH_ID_I2S1 = 99,
 
@@ -54,8 +53,8 @@ enum periph_id {
 	PERIPH_ID_PWM2,
 	PERIPH_ID_PWM3,
 	PERIPH_ID_PWM4,
+	PERIPH_ID_I2C10 = 203,
 
-	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,
 };
 
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 65a5995..194b93b 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -140,13 +140,13 @@ struct gpio {
 					 SRAM_OFFSET2)
 #define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
 
-#define OMAP3_PUBLIC_SRAM_BASE		0x40208000 /* Works for GP & EMU */
-#define OMAP3_PUBLIC_SRAM_END		0x40210000
+#define NON_SECURE_SRAM_START		0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END		0x40210000
 
 #define LOW_LEVEL_SRAM_STACK		0x4020FFFC
 
 /* scratch area - accessible on both EMU and GP */
-#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	OMAP3_PUBLIC_SRAM_BASE
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	NON_SECURE_SRAM_START
 
 #define DEBUG_LED1			149	/* gpio */
 #define DEBUG_LED2			150	/* gpio */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index ce8217f..fc94725 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -30,7 +30,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 590235b..19fdece 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -44,6 +44,7 @@
 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
@@ -204,6 +205,8 @@ struct s32ktimer {
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
 #define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
+#define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
 
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 9e70d48..43011a4 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -31,7 +31,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index 4fc5a0c..5ae5c87 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -51,10 +51,17 @@
 #include <asm/io.h>
 /* CPU detection macros */
 extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+	return s5p_cpu_rev;
+}
 
 static inline void s5p_set_cpu_id(void)
 {
 	s5p_cpu_id = readl(S5PC100_PRO_ID);
+	s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
 	s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
 }
 
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index ac60fe6..da8df74 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -125,20 +125,45 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 /* GPIO pins per bank  */
 #define GPIO_PER_BANK 8
 
-static inline unsigned int s5p_gpio_base(int nr)
-{
-	return S5PC110_GPIO_BASE;
-}
+#define S5P_GPIO_PART_SHIFT	(24)
+#define S5P_GPIO_PART_MASK	(0xff)
+#define S5P_GPIO_BANK_SHIFT	(8)
+#define S5P_GPIO_BANK_MASK	(0xffff)
+#define S5P_GPIO_PIN_MASK	(0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+			((x) & S5P_GPIO_PIN_MASK)
 
-static inline unsigned int s5p_gpio_part_max(int nr)
+#define S5PC100_SET_BANK(bank) \
+			(((unsigned)&(((struct s5pc100_gpio *) \
+			S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define S5PC110_SET_BANK(bank) \
+			((((unsigned)&(((struct s5pc110_gpio *) \
+			S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define s5pc100_gpio_get(bank, pin) \
+			(S5P_GPIO_SET_PART(0) | \
+			S5PC100_SET_BANK(bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define s5pc110_gpio_get(bank, pin) \
+			(S5P_GPIO_SET_PART(0) | \
+			S5PC110_SET_BANK(bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int nr)
 {
-	return 0;
+	return samsung_get_base_gpio();
 }
-
-#define s5pc110_gpio_get_nr(bank, pin)	  \
-	((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
-	    - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
 #endif
 
 /* Pin configurations */
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 074b3bc..7d28e16 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,7 +11,8 @@
 /* PLL registers - there are several PLLs in the clock controller */
 struct clk_pll {
 	uint pll_base;		/* the control register */
-	uint pll_out[2];	/* output control */
+	/* pll_out[0] is output A control, pll_out[1] is output B control */
+	uint pll_out[2];
 	uint pll_misc;		/* other misc things */
 };
 
@@ -21,6 +22,13 @@ struct clk_pll_simple {
 	uint pll_misc;		/* other misc things */
 };
 
+struct clk_pllm {
+	uint pllm_base;		/* the control register */
+	uint pllm_out;		/* output control */
+	uint pllm_misc1;	/* misc1 */
+	uint pllm_misc2;	/* misc2 */
+};
+
 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
 struct clk_set_clr {
 	uint set;
@@ -38,7 +46,8 @@ enum {
 	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
 	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
 	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
-	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W*/
+	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
+	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -47,7 +56,7 @@ struct clk_rst_ctlr {
 	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
 	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
 	uint crc_reserved0;		/* reserved_0,		0x1C */
-	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
+	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0, 0x20 */
 	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
 	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
 	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
@@ -75,7 +84,21 @@ struct clk_rst_ctlr {
 
 	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
 
-	uint crc_reserved20[64];	/* _reserved_20,	0x200-2fc */
+	uint crc_reserved20[32];	/* _reserved_20,	0x200-27c */
+
+	uint crc_clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,	0x280 */
+	uint crc_clk_enb_x_set;		/* _CLK_ENB_X_SET_0,	0x284 */
+	uint crc_clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,	0x288 */
+
+	uint crc_rst_devices_x;		/* _RST_DEVICES_X_0,	0x28c */
+	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
+	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
+
+	uint crc_reserved21[23];	/* _reserved_21,	0x298-2f0 */
+
+	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
+
+	uint crc_reserved22[2];		/* _reserved_22,	0x2f8-2fc */
 
 	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
 	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
@@ -105,10 +128,10 @@ struct clk_rst_ctlr {
 	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
 	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
 	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
-	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTR1L_0,    0x384 */
+	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTRL1_0,    0x384 */
 	uint crc_cpu_softrst_ctrl2;	/* _CPU_SOFTRST_CTRL2_0,    0x388 */
 	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
-	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];	/* 0x3B0-0x42C */
 	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
 	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
 	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
@@ -142,6 +165,47 @@ struct clk_rst_ctlr {
 	uint crc_audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
 	uint crc_audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
 	uint crc_audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+	uint crc_plld2_base;		/* _PLLD2_BASE_0, 0x4B8 */
+	uint crc_plld2_misc;		/* _PLLD2_MISC_0, 0x4BC */
+	uint crc_utmip_pll_cfg3;	/* _UTMIP_PLL_CFG3_0, 0x4C0 */
+	uint crc_pllrefe_base;		/* _PLLREFE_BASE_0, 0x4C4 */
+	uint crc_pllrefe_misc;		/* _PLLREFE_MISC_0, 0x4C8 */
+	uint crs_reserved_50[7];	/* _reserved_50, 0x4CC-0x4E4 */
+	uint crc_pllc2_base;		/* _PLLC2_BASE_0, 0x4E8 */
+	uint crc_pllc2_misc0;		/* _PLLC2_MISC_0_0, 0x4EC */
+	uint crc_pllc2_misc1;		/* _PLLC2_MISC_1_0, 0x4F0 */
+	uint crc_pllc2_misc2;		/* _PLLC2_MISC_2_0, 0x4F4 */
+	uint crc_pllc2_misc3;		/* _PLLC2_MISC_3_0, 0x4F8 */
+	uint crc_pllc3_base;		/* _PLLC3_BASE_0, 0x4FC */
+	uint crc_pllc3_misc0;		/* _PLLC3_MISC_0_0, 0x500 */
+	uint crc_pllc3_misc1;		/* _PLLC3_MISC_1_0, 0x504 */
+	uint crc_pllc3_misc2;		/* _PLLC3_MISC_2_0, 0x508 */
+	uint crc_pllc3_misc3;		/* _PLLC3_MISC_3_0, 0x50C */
+	uint crc_pllx_misc1;		/* _PLLX_MISC_1_0, 0x510 */
+	uint crc_pllx_misc2;		/* _PLLX_MISC_2_0, 0x514 */
+	uint crc_pllx_misc3;		/* _PLLX_MISC_3_0, 0x518 */
+	uint crc_xusbio_pll_cfg0;	/* _XUSBIO_PLL_CFG0_0, 0x51C */
+	uint crc_xusbio_pll_cfg1;	/* _XUSBIO_PLL_CFG0_1, 0x520 */
+	uint crc_plle_aux1;		/* _PLLE_AUX1_0, 0x524 */
+	uint crc_pllp_reshift;		/* _PLLP_RESHIFT_0, 0x528 */
+	uint crc_utmipll_hw_pwrdn_cfg0;	/* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+	uint crc_pllu_hw_pwrdn_cfg0;	/* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+	uint crc_xusb_pll_cfg0;		/* _XUSB_PLL_CFG0_0, 0x534 */
+	uint crc_reserved51[1];		/* _reserved_51, 0x538 */
+	uint crc_clk_cpu_misc;		/* _CLK_CPU_MISC_0, 0x53C */
+	uint crc_clk_cpug_misc;		/* _CLK_CPUG_MISC_0, 0x540 */
+	uint crc_clk_cpulp_misc;	/* _CLK_CPULP_MISC_0, 0x544 */
+	uint crc_pllx_hw_ctrl_cfg;	/* _PLLX_HW_CTRL_CFG_0, 0x548 */
+	uint crc_pllx_sw_ramp_cfg;	/* _PLLX_SW_RAMP_CFG_0, 0x54C */
+	uint crc_pllx_hw_ctrl_status;	/* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+	uint crc_reserved52[1];		/* _reserved_52, 0x554 */
+	uint crc_super_gr3d_clk_div;	/* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+	uint crc_spare_reg0;		/* _SPARE_REG0_0, 0x55C */
+
+	/* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
+	uint crc_reserved60[40];	/* _reserved_60, 0x560 - 0x5FC */
+	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -160,6 +224,9 @@ struct clk_rst_ctlr {
 
 #define PLL_BASE_OVRRIDE_MASK	(1U << 28)
 
+#define PLL_LOCK_SHIFT		27
+#define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
+
 #define PLL_DIVP_SHIFT		20
 #define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
 
@@ -209,6 +276,20 @@ enum {
 	IN_408_OUT_9_6_DIVISOR = 83,
 };
 
+#define PLLP_OUT1_RSTN_DIS	(1 << 0)
+#define PLLP_OUT1_RSTN_EN	(0 << 0)
+#define PLLP_OUT1_CLKEN		(1 << 1)
+#define PLLP_OUT2_RSTN_DIS	(1 << 16)
+#define PLLP_OUT2_RSTN_EN	(0 << 16)
+#define PLLP_OUT2_CLKEN		(1 << 17)
+
+#define PLLP_OUT3_RSTN_DIS	(1 << 0)
+#define PLLP_OUT3_RSTN_EN	(0 << 0)
+#define PLLP_OUT3_CLKEN		(1 << 1)
+#define PLLP_OUT4_RSTN_DIS	(1 << 16)
+#define PLLP_OUT4_RSTN_EN	(0 << 16)
+#define PLLP_OUT4_CLKEN		(1 << 17)
+
 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
 #define PLLU_POWERDOWN		(1 << 16)
 #define PLL_ENABLE_POWERDOWN	(1 << 14)
@@ -219,9 +300,15 @@ enum {
 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
 
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_XOBP_SHIFT		1
-#define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT			0
+#define OSC_XOE_MASK			(1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE			(1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT			1
+#define OSC_XOBP_MASK			(1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT			4
+#define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH		7
 
 /*
  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
@@ -233,11 +320,15 @@ enum {
 #define OUT_CLK_DIVISOR_SHIFT	0
 #define OUT_CLK_DIVISOR_MASK	(0xffff << OUT_CLK_DIVISOR_SHIFT)
 
-#define OUT_CLK_SOURCE_SHIFT	30
-#define OUT_CLK_SOURCE_MASK	(3U << OUT_CLK_SOURCE_SHIFT)
+#define OUT_CLK_SOURCE_31_30_SHIFT	30
+#define OUT_CLK_SOURCE_31_30_MASK	(3U << OUT_CLK_SOURCE_31_30_SHIFT)
+
+#define OUT_CLK_SOURCE_31_29_SHIFT	29
+#define OUT_CLK_SOURCE_31_29_MASK	(7U << OUT_CLK_SOURCE_31_29_SHIFT)
 
-#define OUT_CLK_SOURCE4_SHIFT	28
-#define OUT_CLK_SOURCE4_MASK	(15U << OUT_CLK_SOURCE4_SHIFT)
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT	28
+#define OUT_CLK_SOURCE_31_28_MASK	(15U << OUT_CLK_SOURCE_31_28_SHIFT)
 
 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
 #define SCLK_SYS_STATE_SHIFT    28U
@@ -290,7 +381,7 @@ enum {
 #define SUPER_SCLK_DIVISOR_SHIFT	0
 #define SUPER_SCLK_DIVISOR_MASK		(0xff << SUPER_SCLK_DIVISOR_SHIFT)
 
-/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
 #define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
 #define CLK_SYS_RATE_AHB_RATE_SHIFT     4
@@ -300,23 +391,53 @@ enum {
 #define CLK_SYS_RATE_APB_RATE_SHIFT     0
 #define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 
-/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
-#define CLR_CPURESET0   (1 << 0)
-#define CLR_CPURESET1   (1 << 1)
-#define CLR_CPURESET2   (1 << 2)
-#define CLR_CPURESET3   (1 << 3)
-#define CLR_DBGRESET0   (1 << 12)
-#define CLR_DBGRESET1   (1 << 13)
-#define CLR_DBGRESET2   (1 << 14)
-#define CLR_DBGRESET3   (1 << 15)
-#define CLR_CORERESET0  (1 << 16)
-#define CLR_CORERESET1  (1 << 17)
-#define CLR_CORERESET2  (1 << 18)
-#define CLR_CORERESET3  (1 << 19)
-#define CLR_CXRESET0    (1 << 20)
-#define CLR_CXRESET1    (1 << 21)
-#define CLR_CXRESET2    (1 << 22)
-#define CLR_CXRESET3    (1 << 23)
-#define CLR_NONCPURESET (1 << 29)
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0			(1 << 0)
+#define CLR_CPURESET1			(1 << 1)
+#define CLR_CPURESET2			(1 << 2)
+#define CLR_CPURESET3			(1 << 3)
+#define CLR_DBGRESET0			(1 << 12)
+#define CLR_DBGRESET1			(1 << 13)
+#define CLR_DBGRESET2			(1 << 14)
+#define CLR_DBGRESET3			(1 << 15)
+#define CLR_CORERESET0			(1 << 16)
+#define CLR_CORERESET1			(1 << 17)
+#define CLR_CORERESET2			(1 << 18)
+#define CLR_CORERESET3			(1 << 19)
+#define CLR_CXRESET0			(1 << 20)
+#define CLR_CXRESET1			(1 << 21)
+#define CLR_CXRESET2			(1 << 22)
+#define CLR_CXRESET3			(1 << 23)
+#define CLR_L2RESET			(1 << 24)
+#define CLR_NONCPURESET			(1 << 29)
+#define CLR_PRESETDBG			(1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP		(1 << 8)
+#define CLR_CPU1_CLK_STP		(1 << 9)
+#define CLR_CPU2_CLK_STP		(1 << 10)
+#define CLR_CPU3_CLK_STP		(1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE		(1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE	(1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE	(1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN		(1 << 12)
+#define PLL_ENABLE_POWERDOWN		(1 << 14)
+#define PLLU_POWERDOWN			(1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN	(1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN	(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN	(1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT			3
+#define PLLX_IDDQ_MASK			(1U << PLLX_IDDQ_SHIFT)
 
 #endif	/* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index e7d0fd4..9d8114c 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,6 +20,21 @@ enum clock_osc_freq {
 	CLOCK_OSC_FREQ_COUNT,
 };
 
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
+enum {
+	MASK_BITS_31_30,
+	MASK_BITS_31_29,
+	MASK_BITS_31_28,
+};
+
 #include <asm/arch/clock-tables.h>
 /* PLL stabilization delay in usec */
 #define CLOCK_PLL_STABLE_DELAY_US 300
@@ -305,4 +320,6 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
 /* SoC-specific TSC init */
 void arch_timer_init(void);
 
+void tegra30_set_up_pllp(void);
+
 #endif  /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
index c840c08..7a86acb 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -20,5 +20,6 @@
 #define CHIPID_TEGRA20			0x20
 #define CHIPID_TEGRA30			0x30
 #define CHIPID_TEGRA114			0x35
+#define CHIPID_TEGRA124			0x40
 
 #endif	/* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index ba22236..4c3264b 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010,2011,2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -21,7 +21,11 @@ struct pmc_ctlr {
 	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
 	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
 	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
 	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+	uint pmc_clamp_status;		/* _CLAMP_STATUS_0, offset 2C */
+#endif
 	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
 	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
 	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
@@ -103,6 +107,179 @@ struct pmc_ctlr {
 	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
 	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
 	uint pmc_gate;			/* _GATE_0, offset 15C */
+	/* The following fields are in Tegra124 and later only */
+	uint pmc_wake2_mask;		/* _WAKE2_MASK_0, offset 160 */
+	uint pmc_wake2_lvl;		/* _WAKE2_LVL_0,  offset 164 */
+	uint pmc_wake2_stat;		/* _WAKE2_STATUS_0, offset 168 */
+	uint pmc_sw_wake2_stat;		/* _SW_WAKE2_STATUS_0, offset 16C */
+	uint pmc_auto_wake2_lvl_mask;	/* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+	uint pmc_pg_mask2;		/* _PG_MASK_2_0, offset 174 */
+	uint pmc_pg_mask_ce1;		/* _PG_MASK_CE1_0, offset 178 */
+	uint pmc_pg_mask_ce2;		/* _PG_MASK_CE2_0, offset 17C */
+	uint pmc_pg_mask_ce3;		/* _PG_MASK_CE3_0, offset 180 */
+	uint pmc_pwrgate_timer_ce0;	/* _PWRGATE_TIMER_CE_0_0, offset 184 */
+	uint pmc_pwrgate_timer_ce1;	/* _PWRGATE_TIMER_CE_1_0, offset 188 */
+	uint pmc_pwrgate_timer_ce2;	/* _PWRGATE_TIMER_CE_2_0, offset 18C */
+	uint pmc_pwrgate_timer_ce3;	/* _PWRGATE_TIMER_CE_3_0, offset 190 */
+	uint pmc_pwrgate_timer_ce4;	/* _PWRGATE_TIMER_CE_4_0, offset 194 */
+	uint pmc_pwrgate_timer_ce5;	/* _PWRGATE_TIMER_CE_5_0, offset 198 */
+	uint pmc_pwrgate_timer_ce6;	/* _PWRGATE_TIMER_CE_6_0, offset 19C */
+	uint pmc_pcx_edpd_cntrl;	/* _PCX_EDPD_CNTRL_0, offset 1A0 */
+	uint pmc_osc_edpd_over;		/* _OSC_EDPD_OVER_0, offset 1A4 */
+	uint pmc_clk_out_cntrl;		/* _CLK_OUT_CNTRL_0, offset 1A8 */
+	uint pmc_sata_pwrgate;		/* _SATA_PWRGT_0, offset 1AC */
+	uint pmc_sensor_ctrl;		/* _SENSOR_CTRL_0, offset 1B0 */
+	uint pmc_reset_status;		/* _RTS_STATUS_0, offset 1B4 */
+	uint pmc_io_dpd_req;		/* _IO_DPD_REQ_0, offset 1B8 */
+	uint pmc_io_dpd_stat;		/* _IO_DPD_STATUS_0, offset 1BC */
+	uint pmc_io_dpd2_req;		/* _IO_DPD2_REQ_0, offset 1C0 */
+	uint pmc_io_dpd2_stat;		/* _IO_DPD2_STATUS_0, offset 1C4 */
+	uint pmc_sel_dpd_tim;		/* _SEL_DPD_TIM_0, offset 1C8 */
+	uint pmc_vddp_sel;		/* _VDDP_SEL_0, offset 1CC */
+
+	uint pmc_ddr_cfg;		/* _DDR_CFG_0, offset 1D0 */
+	uint pmc_e_no_vttgen;		/* _E_NO_VTTGEN_0, offset 1D4 */
+	uint pmc_reserved0;		/* _RESERVED, offset 1D8 */
+	uint pmc_pllm_wb0_ovrride_frq;	/* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+	uint pmc_test_pwrgate;		/* _TEST_PWRGATE_0, offset 1E0 */
+	uint pmc_pwrgate_timer_mult;	/* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+	uint pmc_dsi_sel_dpd;		/* _DSI_SEL_DPD_0, offset 1E8 */
+	uint pmc_utmip_uhsic_triggers;	/* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+	uint pmc_utmip_uhsic_saved_st;  /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+	uint pmc_utmip_pad_cfg;		/* _UTMIP_PAD_CFG_0, offset 1F4 */
+	uint pmc_utmip_term_pad_cfg;	/* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+	uint pmc_utmip_uhsic_sleep_cfg;	/* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+	uint pmc_todo_0[9];		/* offset 200-220 */
+	uint pmc_secure_scratch6;	/* _SECURE_SCRATCH6_0, offset 224 */
+	uint pmc_secure_scratch7;	/* _SECURE_SCRATCH7_0, offset 228 */
+	uint pmc_scratch43;		/* _SCRATCH43_0, offset 22C */
+	uint pmc_scratch44;		/* _SCRATCH44_0, offset 230 */
+	uint pmc_scratch45;
+	uint pmc_scratch46;
+	uint pmc_scratch47;
+	uint pmc_scratch48;
+	uint pmc_scratch49;
+	uint pmc_scratch50;
+	uint pmc_scratch51;
+	uint pmc_scratch52;
+	uint pmc_scratch53;
+	uint pmc_scratch54;
+	uint pmc_scratch55;		/* _SCRATCH55_0, offset 25C */
+	uint pmc_scratch0_eco;		/* _SCRATCH0_ECO_0, offset 260 */
+	uint pmc_por_dpd_ctrl;		/* _POR_DPD_CTRL_0, offset 264 */
+	uint pmc_scratch2_eco;		/* _SCRATCH2_ECO_0, offset 268 */
+	uint pmc_todo_1[17];		/* TODO: 26C ~ 2AC */
+	uint pmc_pllm_wb0_override2;	/* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+	uint pmc_tsc_mult;		/* _TSC_MULT_0, offset 2B4 */
+	uint pmc_cpu_vsense_override;	/* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+	uint pmc_glb_amap_cfg;		/* _GLB_AMAP_CFG_0, offset 2BC */
+	uint pmc_sticky_bits;		/* _STICKY_BITS_0, offset 2C0 */
+	uint pmc_sec_disable2;		/* _SEC_DISALBE2, offset 2C4 */
+	uint pmc_weak_bias;		/* _WEAK_BIAS_0, offset 2C8 */
+	uint pmc_todo_3[13];		/* TODO: 2CC ~ 2FC */
+	uint pmc_secure_scratch8;	/* _SECURE_SCRATCH8_0, offset 300 */
+	uint pmc_secure_scratch9;
+	uint pmc_secure_scratch10;
+	uint pmc_secure_scratch11;
+	uint pmc_secure_scratch12;
+	uint pmc_secure_scratch13;
+	uint pmc_secure_scratch14;
+	uint pmc_secure_scratch15;
+	uint pmc_secure_scratch16;
+	uint pmc_secure_scratch17;
+	uint pmc_secure_scratch18;
+	uint pmc_secure_scratch19;
+	uint pmc_secure_scratch20;
+	uint pmc_secure_scratch21;
+	uint pmc_secure_scratch22;
+	uint pmc_secure_scratch23;
+	uint pmc_secure_scratch24;	/* _SECURE_SCRATCH24_0, offset 340 */
+	uint pmc_secure_scratch25;
+	uint pmc_secure_scratch26;
+	uint pmc_secure_scratch27;
+	uint pmc_secure_scratch28;
+	uint pmc_secure_scratch29;
+	uint pmc_secure_scratch30;
+	uint pmc_secure_scratch31;
+	uint pmc_secure_scratch32;
+	uint pmc_secure_scratch33;
+	uint pmc_secure_scratch34;
+	uint pmc_secure_scratch35;	/* _SECURE_SCRATCH35_0, offset 36C */
+
+	uint pmc_reserved1[52];		/* RESERVED: 370 ~ 43C */
+	uint pmc_cntrl2;		/* _CNTRL2_0, offset 440 */
+	uint pmc_reserved2[6];		/* RESERVED: 444 ~ 458 */
+	uint pmc_io_dpd3_req;		/* _IO_DPD3_REQ_0, offset 45c */
+	uint pmc_io_dpd3_stat;		/* _IO_DPD3_STATUS_0, offset 460 */
+	uint pmc_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 464 */
+	uint pmc_reserved3[102];	/* RESERVED: 468 ~ 5FC */
+
+	uint pmc_scratch56;		/* _SCRATCH56_0, offset 600 */
+	uint pmc_scratch57;
+	uint pmc_scratch58;
+	uint pmc_scratch59;
+	uint pmc_scratch60;
+	uint pmc_scratch61;
+	uint pmc_scratch62;
+	uint pmc_scratch63;
+	uint pmc_scratch64;
+	uint pmc_scratch65;
+	uint pmc_scratch66;
+	uint pmc_scratch67;
+	uint pmc_scratch68;
+	uint pmc_scratch69;
+	uint pmc_scratch70;
+	uint pmc_scratch71;
+	uint pmc_scratch72;
+	uint pmc_scratch73;
+	uint pmc_scratch74;
+	uint pmc_scratch75;
+	uint pmc_scratch76;
+	uint pmc_scratch77;
+	uint pmc_scratch78;
+	uint pmc_scratch79;
+	uint pmc_scratch80;
+	uint pmc_scratch81;
+	uint pmc_scratch82;
+	uint pmc_scratch83;
+	uint pmc_scratch84;
+	uint pmc_scratch85;
+	uint pmc_scratch86;
+	uint pmc_scratch87;
+	uint pmc_scratch88;
+	uint pmc_scratch89;
+	uint pmc_scratch90;
+	uint pmc_scratch91;
+	uint pmc_scratch92;
+	uint pmc_scratch93;
+	uint pmc_scratch94;
+	uint pmc_scratch95;
+	uint pmc_scratch96;
+	uint pmc_scratch97;
+	uint pmc_scratch98;
+	uint pmc_scratch99;
+	uint pmc_scratch100;
+	uint pmc_scratch101;
+	uint pmc_scratch102;
+	uint pmc_scratch103;
+	uint pmc_scratch104;
+	uint pmc_scratch105;
+	uint pmc_scratch106;
+	uint pmc_scratch107;
+	uint pmc_scratch108;
+	uint pmc_scratch109;
+	uint pmc_scratch110;
+	uint pmc_scratch111;
+	uint pmc_scratch112;
+	uint pmc_scratch113;
+	uint pmc_scratch114;
+	uint pmc_scratch115;
+	uint pmc_scratch116;
+	uint pmc_scratch117;
+	uint pmc_scratch118;
+	uint pmc_scratch119;
+	uint pmc_scratch1_eco;	/* offset 700 */
 };
 
 #define CPU_PWRED	1
@@ -114,11 +291,90 @@ struct pmc_ctlr {
 #define CPUPWRREQ_OE	(1 << 16)
 #define CPUPWRREQ_POL	(1 << 15)
 
-#define CRAILID		(0)
-#define CE0ID		(14)
-#define C0NCID		(15)
-#define CRAIL		(1 << CRAILID)
-#define CE0		(1 << CE0ID)
-#define C0NC		(1 << C0NCID)
+#define CRAIL		0
+#define CE0		14
+#define C0NC		15
+
+#define PMC_XOFS_SHIFT	1
+#define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
+
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	2
+#define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
+#define MULT_1			0
+#define MULT_2			1
+#define MULT_4			2
+#define MULT_8			3
+
+#define AMAP_WRITE_SHIFT	20
+#define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON			(1 << 4)
+#define SEC_DISABLE_READ0_ON			(1 << 5)
+#define SEC_DISABLE_WRITE1_ON			(1 << 6)
+#define SEC_DISABLE_READ1_ON			(1 << 7)
+#define SEC_DISABLE_WRITE2_ON			(1 << 8)
+#define SEC_DISABLE_READ2_ON			(1 << 9)
+#define SEC_DISABLE_WRITE3_ON			(1 << 10)
+#define SEC_DISABLE_READ3_ON			(1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON		(1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL		0
+#define PWRGATE_TOGGLE_PARTID_TD		1
+#define PWRGATE_TOGGLE_PARTID_VE		2
+#define PWRGATE_TOGGLE_PARTID_PCX		3
+#define PWRGATE_TOGGLE_PARTID_VDE		4
+#define PWRGATE_TOGGLE_PARTID_L2C		5
+#define PWRGATE_TOGGLE_PARTID_MPE		6
+#define PWRGATE_TOGGLE_PARTID_HEG		7
+#define PWRGATE_TOGGLE_PARTID_SAX		8
+#define PWRGATE_TOGGLE_PARTID_CE1		9
+#define PWRGATE_TOGGLE_PARTID_CE2		10
+#define PWRGATE_TOGGLE_PARTID_CE3		11
+#define PWRGATE_TOGGLE_PARTID_CELP		12
+#define PWRGATE_TOGGLE_PARTID_CE0		14
+#define PWRGATE_TOGGLE_PARTID_C0NC		15
+#define PWRGATE_TOGGLE_PARTID_C1NC		16
+#define PWRGATE_TOGGLE_PARTID_SOR		17
+#define PWRGATE_TOGGLE_PARTID_DIS		18
+#define PWRGATE_TOGGLE_PARTID_DISB		19
+#define PWRGATE_TOGGLE_PARTID_XUSBA		20
+#define PWRGATE_TOGGLE_PARTID_XUSBB		21
+#define PWRGATE_TOGGLE_PARTID_XUSBC		22
+#define PWRGATE_TOGGLE_PARTID_VIC		23
+#define PWRGATE_TOGGLE_PARTID_IRAM		24
+#define PWRGATE_TOGGLE_START			(1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE		(1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE		(1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE		(1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE		(1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE		(1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE		(1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE		(1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE		(1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE		(1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE		(1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE		(1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE		(1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE		(1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE		(1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE		(1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE		(1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE		(1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE		(1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE		(1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE		(1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE		(1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE		(1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE		(1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE		(1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN				(1 << 12)
 
 #endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index e99f681..5fe19ae 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -68,6 +68,7 @@ enum {
 	SKU_ID_TM30MQS_P_A3	= 0xb1,
 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
 	SKU_ID_T114_1		= 0x01,
+	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
 };
 
 /*
@@ -81,6 +82,7 @@ enum {
 	TEGRA_SOC_T25,
 	TEGRA_SOC_T30,
 	TEGRA_SOC_T114,
+	TEGRA_SOC_T124,
 
 	TEGRA_SOC_CNT,
 	TEGRA_SOC_UNKNOWN	= -1,
diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h
new file mode 100644
index 0000000..4e48c43
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+	u32 reserved0;			/* 00h */
+	u32 arbitration_disable;	/* _ARBITRATION_DISABLE_0,	04h */
+	u32 arbitration_priority_ctrl;	/* _ARBITRATION_PRIORITY_CTRL_0,08h */
+	u32 arbitration_usr_protect;	/* _ARBITRATION_USR_PROTECT_0,	0ch */
+	u32 gizmo_ahb_mem;		/* _GIZMO_AHB_MEM_0,		10h */
+	u32 gizmo_apb_dma;		/* _GIZMO_APB_DMA_0,		14h */
+	u32 reserved6[2];		/* 18h, 1ch */
+	u32 gizmo_usb;			/* _GIZMO_USB_0,		20h */
+	u32 gizmo_ahb_xbar_bridge;	/* _GIZMO_AHB_XBAR_BRIDGE_0,	24h */
+	u32 gizmo_cpu_ahb_bridge;	/* _GIZMO_CPU_AHB_BRIDGE_0,	28h */
+	u32 gizmo_cop_ahb_bridge;	/* _GIZMO_COP_AHB_BRIDGE_0,	2ch */
+	u32 gizmo_xbar_apb_ctlr;	/* _GIZMO_XBAR_APB_CTLR_0,	30h */
+	u32 gizmo_vcp_ahb_bridge;	/* _GIZMO_VCP_AHB_BRIDGE_0,	34h */
+	u32 reserved13[2];		/* 38h, 3ch */
+	u32 gizmo_nand;			/* _GIZMO_NAND_0,		40h */
+	u32 reserved15;			/* 44h */
+	u32 gizmo_sdmmc4;		/* _GIZMO_SDMMC4_0,		48h */
+	u32 reserved17;			/* 4ch */
+	u32 gizmo_se;			/* _GIZMO_SE_0,			50h */
+	u32 gizmo_tzram;		/* _GIZMO_TZRAM_0,		54h */
+	u32 reserved20[3];		/* 58h, 5ch, 60h */
+	u32 gizmo_bsev;			/* _GIZMO_BSEV_0,		64h */
+	u32 reserved22[3];		/* 68h, 6ch, 70h */
+	u32 gizmo_bsea;			/* _GIZMO_BSEA_0,		74h */
+	u32 gizmo_nor;			/* _GIZMO_NOR_0,		78h */
+	u32 gizmo_usb2;			/* _GIZMO_USB2_0,		7ch */
+	u32 gizmo_usb3;			/* _GIZMO_USB3_0,		80h */
+	u32 gizmo_sdmmc1;		/* _GIZMO_SDMMC1_0,		84h */
+	u32 gizmo_sdmmc2;		/* _GIZMO_SDMMC2_0,		88h */
+	u32 gizmo_sdmmc3;		/* _GIZMO_SDMMC3_0,		8ch */
+	u32 reserved30[13];		/* 90h ~ c0h */
+	u32 ahb_wrq_empty;		/* _AHB_WRQ_EMPTY_0,		c4h */
+	u32 reserved32[5];		/* c8h ~ d8h */
+	u32 ahb_mem_prefetch_cfg_x;	/* _AHB_MEM_PREFETCH_CFG_X_0,	dch */
+	u32 arbitration_xbar_ctrl;	/* _ARBITRATION_XBAR_CTRL_0,	e0h */
+	u32 ahb_mem_prefetch_cfg3;	/* _AHB_MEM_PREFETCH_CFG3_0,	e4h */
+	u32 ahb_mem_prefetch_cfg4;	/* _AHB_MEM_PREFETCH_CFG3_0,	e8h */
+	u32 avp_ppcs_rd_coh_status;	/* _AVP_PPCS_RD_COH_STATUS_0,	ech */
+	u32 ahb_mem_prefetch_cfg1;	/* _AHB_MEM_PREFETCH_CFG1_0,	f0h */
+	u32 ahb_mem_prefetch_cfg2;	/* _AHB_MEM_PREFETCH_CFG2_0,	f4h */
+	u32 ahbslvmem_status;		/* _AHBSLVMEM_STATUS_0, f8h */
+	/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+	u32 arbitration_ahb_mem_wrque_mst_id;
+	u32 arbitration_cpu_abort_addr;	/* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+	u32 arbitration_cpu_abort_info;	/* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+	u32 arbitration_cop_abort_addr;	/* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+	u32 arbitration_cop_abort_info;	/* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+	u32 reserved46[4];		/* 110h ~ 11ch */
+	u32 avpc_mccif_fifoctrl;	/* _AVPC_MCCIF_FIFOCTRL_0,	120h */
+	u32 timeout_wcoal_avpc;		/* _TIMEOUT_WCOAL_AVPC_0,	124h */
+	u32 mpcorelp_mccif_fifoctrl;	/* _MPCORELP_MCCIF_FIFOCTRL_0,	128h */
+	u32 mpcore_mccif_fifoctrl;	/* _MPCORE_MCCIF_FIFOCTRL_0,	12ch */
+	u32 axicif_fastsync_ctrl;	/* AXICIF_FASTSYNC_CTRL_0,	130h */
+	u32 axicif_fastsync_statistics;	/* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+	/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0,	138h */
+	u32 axicif_fastsync0_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+	u32 axicif_fastsync1_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+	u32 axicif_fastsync2_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+	u32 axicif_fastsync0_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+	u32 axicif_fastsync1_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+	u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE	(1 << 2)
+
+#define GIZ_ENABLE_SPLIT	(1 << 0)
+#define GIZ_ENB_FAST_REARB	(1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
+
+#define GIZ_USB_IMMEDIATE	(1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
+
+#endif	/* _TEGRA124_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
new file mode 100644
index 0000000..daf9a2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SoC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+
+	/*
+	 * These are clock IDs that are used in table clock_source[][]
+	 * but will not be assigned as a clock source for any peripheral.
+	 */
+	CLOCK_ID_DISPLAY2,
+	CLOCK_ID_CGENERAL2,
+	CLOCK_ID_CGENERAL3,
+	CLOCK_ID_MEMORY2,
+	CLOCK_ID_SRC2,
+
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_ISPB,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_RESERVED13,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TCW,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_RESERVED19,
+	PERIPH_ID_VI,
+	PERIPH_ID_RESERVED21,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_RESERVED25,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_RESERVED36,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_RESERVED38,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_RESERVED49,
+	PERIPH_ID_HSI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_RESERVED53,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_MIPI_CAL,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_RESERVED60,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_RESERVED64,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_LA,
+	PERIPH_ID_TRACECLKIN,
+	PERIPH_ID_SOC_THERM,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_TSEC,
+	PERIPH_ID_RESERVED84,
+	PERIPH_ID_RESERVED85,
+	PERIPH_ID_RESERVED86,
+	PERIPH_ID_EMUCIF,
+
+	/* 88 */
+	PERIPH_ID_RESERVED88,
+	PERIPH_ID_XUSB_HOST,
+	PERIPH_ID_RESERVED90,
+	PERIPH_ID_MSENC,
+	PERIPH_ID_RESERVED92,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_XUSB_DEV,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_V_RESERVED2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_V_RESERVED4,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_V_RESERVED17,
+	PERIPH_ID_V_RESERVED18,
+	PERIPH_ID_V_RESERVED19,
+	PERIPH_ID_V_RESERVED20,
+	PERIPH_ID_V_RESERVED21,
+	PERIPH_ID_V_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EXTPERIPH1,
+	PERIPH_ID_EXTPERIPH2,
+	PERIPH_ID_EXTPERIPH3,
+	PERIPH_ID_OOB,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_V_RESERVED30,
+	PERIPH_ID_V_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_W_RESERVED2,
+	PERIPH_ID_W_RESERVED3,
+	PERIPH_ID_W_RESERVED4,
+	PERIPH_ID_W_RESERVED5,
+	PERIPH_ID_W_RESERVED6,
+	PERIPH_ID_W_RESERVED7,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_W_RESERVED9,
+	PERIPH_ID_W_RESERVED10,
+	PERIPH_ID_W_RESERVED11,
+	PERIPH_ID_W_RESERVED12,
+	PERIPH_ID_W_RESERVED13,
+	PERIPH_ID_XUSB_PADCTL,
+	PERIPH_ID_W_RESERVED15,
+
+	/* 144 */
+	PERIPH_ID_W_RESERVED16,
+	PERIPH_ID_W_RESERVED17,
+	PERIPH_ID_W_RESERVED18,
+	PERIPH_ID_W_RESERVED19,
+	PERIPH_ID_W_RESERVED20,
+	PERIPH_ID_ENTROPY,
+	PERIPH_ID_DDS,
+	PERIPH_ID_W_RESERVED23,
+
+	/* 152 */
+	PERIPH_ID_DP2,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_W_RESERVED29,
+	PERIPH_ID_W_RESERVED30,
+	PERIPH_ID_W_RESERVED31,
+
+	PERIPH_ID_X_FIRST,
+	/* X word: 31:0 */
+	PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+	PERIPH_ID_X_RESERVED1,
+	PERIPH_ID_X_RESERVED2,
+	PERIPH_ID_X_RESERVED3,
+	PERIPH_ID_CAM_MCLK,
+	PERIPH_ID_CAM_MCLK2,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_X_RESERVED7,
+
+	/* 168 */
+	PERIPH_ID_X_RESERVED8,
+	PERIPH_ID_X_RESERVED9,
+	PERIPH_ID_X_RESERVED10,
+	PERIPH_ID_VIM2_CLK,
+	PERIPH_ID_X_RESERVED12,
+	PERIPH_ID_X_RESERVED13,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_X_RESERVED15,
+
+	/* 176 */
+	PERIPH_ID_HDMI_AUDIO,
+	PERIPH_ID_CLK72MHZ,
+	PERIPH_ID_VIC,
+	PERIPH_ID_X_RESERVED19,
+	PERIPH_ID_ADX1,
+	PERIPH_ID_DPAUX,
+	PERIPH_ID_SOR0,
+	PERIPH_ID_X_RESERVED23,
+
+	/* 184 */
+	PERIPH_ID_GPU,
+	PERIPH_ID_AMX1,
+	PERIPH_ID_X_RESERVED26,
+	PERIPH_ID_X_RESERVED27,
+	PERIPH_ID_X_RESERVED28,
+	PERIPH_ID_X_RESERVED29,
+	PERIPH_ID_X_RESERVED30,
+	PERIPH_ID_X_RESERVED31,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_10h,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_18h,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_1Bh,
+	PERIPHC_1Ch,
+	PERIPHC_HSI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_22h,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_25h,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_DTV,
+
+	/* 0x38 */
+	PERIPHC_38h,
+	PERIPHC_39h,
+	PERIPHC_3ah,
+	PERIPHC_3bh,
+	PERIPHC_MSENC,
+	PERIPHC_TSEC,
+	PERIPHC_3eh,
+	PERIPHC_OSC,
+
+	PERIPHC_VW_FIRST,
+	/* 0x40 */
+	PERIPHC_40h = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x48 */
+	PERIPHC_AUDIO,
+	PERIPHC_49h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x50 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_52h,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_55h,
+	PERIPHC_56h,
+	PERIPHC_57h,
+
+	/* 0x58 */
+	PERIPHC_58h,
+	PERIPHC_59h,
+	PERIPHC_5ah,
+	PERIPHC_5bh,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,		/* 0x428 */
+	PERIPHC_5fh,
+
+	PERIPHC_X_FIRST,
+	/* 0x60 */
+	PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST,	/* 0x600 */
+	PERIPHC_XUSB_FALCON,
+	PERIPHC_XUSB_FS,
+	PERIPHC_XUSB_CORE_DEV,
+	PERIPHC_XUSB_SS,
+	PERIPHC_CILAB,
+	PERIPHC_CILCD,
+	PERIPHC_CILE,
+
+	/* 0x68 */
+	PERIPHC_DSIA_LP,
+	PERIPHC_DSIB_LP,
+	PERIPHC_ENTROPY,
+	PERIPHC_DVFS_REF,
+	PERIPHC_DVFS_SOC,
+	PERIPHC_TRACECLKIN,
+	PERIPHC_ADX0,
+	PERIPHC_AMX0,
+
+	/* 0x70 */
+	PERIPHC_EMC_LATENCY,
+	PERIPHC_SOC_THERM,
+	PERIPHC_72h,
+	PERIPHC_73h,
+	PERIPHC_74h,
+	PERIPHC_75h,
+	PERIPHC_VI_SENSOR2,
+	PERIPHC_I2C6,
+
+	/* 0x78 */
+	PERIPHC_78h,
+	PERIPHC_EMC_DLL,
+	PERIPHC_HDMI_AUDIO,
+	PERIPHC_CLK72MHZ,
+	PERIPHC_ADX1,
+	PERIPHC_AMX1,
+	PERIPHC_VIC,
+	PERIPHC_7fh,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA124_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
new file mode 100644
index 0000000..8e39d21
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA124_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
new file mode 100644
index 0000000..0db1881
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;	/* offset 0x00 */
+	u32 halt_cop_events;	/* offset 0x04 */
+	u32 cpu_csr;		/* offset 0x08 */
+	u32 cop_csr;		/* offset 0x0c */
+	u32 xrq_events;		/* offset 0x10 */
+	u32 halt_cpu1_events;	/* offset 0x14 */
+	u32 cpu1_csr;		/* offset 0x18 */
+	u32 halt_cpu2_events;	/* offset 0x1c */
+	u32 cpu2_csr;		/* offset 0x20 */
+	u32 halt_cpu3_events;	/* offset 0x24 */
+	u32 cpu3_csr;		/* offset 0x28 */
+	u32 cluster_control;	/* offset 0x2c */
+	u32 halt_cop1_events;	/* offset 0x30 */
+	u32 halt_cop1_csr;	/* offset 0x34 */
+	u32 cpu_pwr_csr;	/* offset 0x38 */
+	u32 mpid;		/* offset 0x3c */
+	u32 ram_repair;		/* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC		(1 << 24)
+#define EVENT_USEC		(1 << 25)
+#define EVENT_JTAG		(1 << 28)
+#define EVENT_MODE_STOP		(2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP		(1 << 0)
+
+#endif	/*  _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h
new file mode 100644
index 0000000..df94d13
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/funcmux.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_KBC = 0,
+	FUNCMUX_UART4_GPIO = 0,
+};
+#endif	/* _TEGRA124_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
new file mode 100644
index 0000000..440cbbf
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
new file mode 100644
index 0000000..1a6dcb8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+	GPIO_PA0 = 0,	/* pin 0 */
+	GPIO_PA1,
+	GPIO_PA2,
+	GPIO_PA3,
+	GPIO_PA4,
+	GPIO_PA5,
+	GPIO_PA6,
+	GPIO_PA7,
+	GPIO_PB0,	/* pin 8 */
+	GPIO_PB1,
+	GPIO_PB2,
+	GPIO_PB3,
+	GPIO_PB4,
+	GPIO_PB5,
+	GPIO_PB6,
+	GPIO_PB7,
+	GPIO_PC0,	/* pin 16 */
+	GPIO_PC1,
+	GPIO_PC2,
+	GPIO_PC3,
+	GPIO_PC4,
+	GPIO_PC5,
+	GPIO_PC6,
+	GPIO_PC7,
+	GPIO_PD0,	/* pin 24 */
+	GPIO_PD1,
+	GPIO_PD2,
+	GPIO_PD3,
+	GPIO_PD4,
+	GPIO_PD5,
+	GPIO_PD6,
+	GPIO_PD7,
+	GPIO_PE0,	/* pin 32 */
+	GPIO_PE1,
+	GPIO_PE2,
+	GPIO_PE3,
+	GPIO_PE4,
+	GPIO_PE5,
+	GPIO_PE6,
+	GPIO_PE7,
+	GPIO_PF0,	/* pin 40 */
+	GPIO_PF1,
+	GPIO_PF2,
+	GPIO_PF3,
+	GPIO_PF4,
+	GPIO_PF5,
+	GPIO_PF6,
+	GPIO_PF7,
+	GPIO_PG0,	/* pin 48 */
+	GPIO_PG1,
+	GPIO_PG2,
+	GPIO_PG3,
+	GPIO_PG4,
+	GPIO_PG5,
+	GPIO_PG6,
+	GPIO_PG7,
+	GPIO_PH0,	/* pin 56 */
+	GPIO_PH1,
+	GPIO_PH2,
+	GPIO_PH3,
+	GPIO_PH4,
+	GPIO_PH5,
+	GPIO_PH6,
+	GPIO_PH7,
+	GPIO_PI0,	/* pin 64 */
+	GPIO_PI1,
+	GPIO_PI2,
+	GPIO_PI3,
+	GPIO_PI4,
+	GPIO_PI5,
+	GPIO_PI6,
+	GPIO_PI7,
+	GPIO_PJ0,	/* pin 72 */
+	GPIO_PJ1,
+	GPIO_PJ2,
+	GPIO_PJ3,
+	GPIO_PJ4,
+	GPIO_PJ5,
+	GPIO_PJ6,
+	GPIO_PJ7,
+	GPIO_PK0,	/* pin 80 */
+	GPIO_PK1,
+	GPIO_PK2,
+	GPIO_PK3,
+	GPIO_PK4,
+	GPIO_PK5,
+	GPIO_PK6,
+	GPIO_PK7,
+	GPIO_PL0,	/* pin 88 */
+	GPIO_PL1,
+	GPIO_PL2,
+	GPIO_PL3,
+	GPIO_PL4,
+	GPIO_PL5,
+	GPIO_PL6,
+	GPIO_PL7,
+	GPIO_PM0,	/* pin 96 */
+	GPIO_PM1,
+	GPIO_PM2,
+	GPIO_PM3,
+	GPIO_PM4,
+	GPIO_PM5,
+	GPIO_PM6,
+	GPIO_PM7,
+	GPIO_PN0,	/* pin 104 */
+	GPIO_PN1,
+	GPIO_PN2,
+	GPIO_PN3,
+	GPIO_PN4,
+	GPIO_PN5,
+	GPIO_PN6,
+	GPIO_PN7,
+	GPIO_PO0,	/* pin 112 */
+	GPIO_PO1,
+	GPIO_PO2,
+	GPIO_PO3,
+	GPIO_PO4,
+	GPIO_PO5,
+	GPIO_PO6,
+	GPIO_PO7,
+	GPIO_PP0,	/* pin 120 */
+	GPIO_PP1,
+	GPIO_PP2,
+	GPIO_PP3,
+	GPIO_PP4,
+	GPIO_PP5,
+	GPIO_PP6,
+	GPIO_PP7,
+	GPIO_PQ0,	/* pin 128 */
+	GPIO_PQ1,
+	GPIO_PQ2,
+	GPIO_PQ3,
+	GPIO_PQ4,
+	GPIO_PQ5,
+	GPIO_PQ6,
+	GPIO_PQ7,
+	GPIO_PR0,	/* pin 136 */
+	GPIO_PR1,
+	GPIO_PR2,
+	GPIO_PR3,
+	GPIO_PR4,
+	GPIO_PR5,
+	GPIO_PR6,
+	GPIO_PR7,
+	GPIO_PS0,	/* pin 144 */
+	GPIO_PS1,
+	GPIO_PS2,
+	GPIO_PS3,
+	GPIO_PS4,
+	GPIO_PS5,
+	GPIO_PS6,
+	GPIO_PS7,
+	GPIO_PT0,	/* pin 152 */
+	GPIO_PT1,
+	GPIO_PT2,
+	GPIO_PT3,
+	GPIO_PT4,
+	GPIO_PT5,
+	GPIO_PT6,
+	GPIO_PT7,
+	GPIO_PU0,	/* pin 160 */
+	GPIO_PU1,
+	GPIO_PU2,
+	GPIO_PU3,
+	GPIO_PU4,
+	GPIO_PU5,
+	GPIO_PU6,
+	GPIO_PU7,
+	GPIO_PV0,	/* pin 168 */
+	GPIO_PV1,
+	GPIO_PV2,
+	GPIO_PV3,
+	GPIO_PV4,
+	GPIO_PV5,
+	GPIO_PV6,
+	GPIO_PV7,
+	GPIO_PW0,	/* pin 176 */
+	GPIO_PW1,
+	GPIO_PW2,
+	GPIO_PW3,
+	GPIO_PW4,
+	GPIO_PW5,
+	GPIO_PW6,
+	GPIO_PW7,
+	GPIO_PX0,	/* pin 184 */
+	GPIO_PX1,
+	GPIO_PX2,
+	GPIO_PX3,
+	GPIO_PX4,
+	GPIO_PX5,
+	GPIO_PX6,
+	GPIO_PX7,
+	GPIO_PY0,	/* pin 192 */
+	GPIO_PY1,
+	GPIO_PY2,
+	GPIO_PY3,
+	GPIO_PY4,
+	GPIO_PY5,
+	GPIO_PY6,
+	GPIO_PY7,
+	GPIO_PZ0,	/* pin 200 */
+	GPIO_PZ1,
+	GPIO_PZ2,
+	GPIO_PZ3,
+	GPIO_PZ4,
+	GPIO_PZ5,
+	GPIO_PZ6,
+	GPIO_PZ7,
+	GPIO_PAA0,	/* pin 208 */
+	GPIO_PAA1,
+	GPIO_PAA2,
+	GPIO_PAA3,
+	GPIO_PAA4,
+	GPIO_PAA5,
+	GPIO_PAA6,
+	GPIO_PAA7,
+	GPIO_PBB0,	/* pin 216 */
+	GPIO_PBB1,
+	GPIO_PBB2,
+	GPIO_PBB3,
+	GPIO_PBB4,
+	GPIO_PBB5,
+	GPIO_PBB6,
+	GPIO_PBB7,
+	GPIO_PCC0,	/* pin 224 */
+	GPIO_PCC1,
+	GPIO_PCC2,
+	GPIO_PCC3,
+	GPIO_PCC4,
+	GPIO_PCC5,
+	GPIO_PCC6,
+	GPIO_PCC7,
+	GPIO_PDD0,	/* pin 232 */
+	GPIO_PDD1,
+	GPIO_PDD2,
+	GPIO_PDD3,
+	GPIO_PDD4,
+	GPIO_PDD5,
+	GPIO_PDD6,
+	GPIO_PDD7,
+	GPIO_PEE0,	/* pin 240 */
+	GPIO_PEE1,
+	GPIO_PEE2,
+	GPIO_PEE3,
+	GPIO_PEE4,
+	GPIO_PEE5,
+	GPIO_PEE6,
+	GPIO_PEE7,
+	GPIO_PFF0,	/* pin 248 */
+	GPIO_PFF1,
+	GPIO_PFF2,
+	GPIO_PFF3,
+	GPIO_PFF4,
+	GPIO_PFF5,
+	GPIO_PFF6,
+	GPIO_PFF7,	/* pin 255 */
+};
+
+#endif	/* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h
new file mode 100644
index 0000000..114fce8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/hardware.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_HARDWARE_H_
+#define _TEGRA124_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra124
+ */
+
+#endif /* _TEGRA124_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
new file mode 100644
index 0000000..9662e2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *	- function
+ *	- pullup / pulldown
+ *	- tristate or normal
+ */
+enum pmux_pingrp {
+	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
+	PINGRP_ULPI_DATA1,
+	PINGRP_ULPI_DATA2,
+	PINGRP_ULPI_DATA3,
+	PINGRP_ULPI_DATA4,
+	PINGRP_ULPI_DATA5,
+	PINGRP_ULPI_DATA6,
+	PINGRP_ULPI_DATA7,
+	PINGRP_ULPI_CLK,
+	PINGRP_ULPI_DIR,
+	PINGRP_ULPI_NXT,
+	PINGRP_ULPI_STP,
+	PINGRP_DAP3_FS,
+	PINGRP_DAP3_DIN,
+	PINGRP_DAP3_DOUT,
+	PINGRP_DAP3_SCLK,
+	PINGRP_GPIO_PV0,
+	PINGRP_GPIO_PV1,
+	PINGRP_SDMMC1_CLK,
+	PINGRP_SDMMC1_CMD,
+	PINGRP_SDMMC1_DAT3,
+	PINGRP_SDMMC1_DAT2,
+	PINGRP_SDMMC1_DAT1,
+	PINGRP_SDMMC1_DAT0,
+	PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
+	PINGRP_CLK2_REQ,
+	PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
+	PINGRP_DDC_SCL,
+	PINGRP_DDC_SDA,
+	PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
+	PINGRP_UART2_TXD,
+	PINGRP_UART2_RTS_N,
+	PINGRP_UART2_CTS_N,
+	PINGRP_UART3_TXD,
+	PINGRP_UART3_RXD,
+	PINGRP_UART3_CTS_N,
+	PINGRP_UART3_RTS_N,
+	PINGRP_GPIO_PU0,
+	PINGRP_GPIO_PU1,
+	PINGRP_GPIO_PU2,
+	PINGRP_GPIO_PU3,
+	PINGRP_GPIO_PU4,
+	PINGRP_GPIO_PU5,
+	PINGRP_GPIO_PU6,
+	PINGRP_GEN1_I2C_SDA,
+	PINGRP_GEN1_I2C_SCL,
+	PINGRP_DAP4_FS,
+	PINGRP_DAP4_DIN,
+	PINGRP_DAP4_DOUT,
+	PINGRP_DAP4_SCLK,
+	PINGRP_CLK3_OUT,
+	PINGRP_CLK3_REQ,
+	/* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
+	PINGRP_GPIO_PC7,			/* offset 0x31c0 */
+	PINGRP_GPIO_PI5,
+	PINGRP_GPIO_PI7,
+	PINGRP_GPIO_PK0,
+	PINGRP_GPIO_PK1,
+	PINGRP_GPIO_PJ0,
+	PINGRP_GPIO_PJ2,
+	PINGRP_GPIO_PK3,
+	PINGRP_GPIO_PK4,
+	PINGRP_GPIO_PK2,
+	PINGRP_GPIO_PI3,
+	PINGRP_GPIO_PI6,
+	PINGRP_GPIO_PG0,
+	PINGRP_GPIO_PG1,
+	PINGRP_GPIO_PG2,
+	PINGRP_GPIO_PG3,
+	PINGRP_GPIO_PG4,
+	PINGRP_GPIO_PG5,
+	PINGRP_GPIO_PG6,
+	PINGRP_GPIO_PG7,
+	PINGRP_GPIO_PH0,
+	PINGRP_GPIO_PH1,
+	PINGRP_GPIO_PH2,
+	PINGRP_GPIO_PH3,
+	PINGRP_GPIO_PH4,
+	PINGRP_GPIO_PH5,
+	PINGRP_GPIO_PH6,
+	PINGRP_GPIO_PH7,
+	PINGRP_GPIO_PJ7,
+	PINGRP_GPIO_PB0,
+	PINGRP_GPIO_PB1,
+	PINGRP_GPIO_PK7,
+	PINGRP_GPIO_PI0,
+	PINGRP_GPIO_PI1,
+	PINGRP_GPIO_PI2,
+	PINGRP_GPIO_PI4,			/* offset 0x324c */
+	PINGRP_GEN2_I2C_SCL,
+	PINGRP_GEN2_I2C_SDA,
+	PINGRP_SDMMC4_CLK,
+	PINGRP_SDMMC4_CMD,
+	PINGRP_SDMMC4_DAT0,
+	PINGRP_SDMMC4_DAT1,
+	PINGRP_SDMMC4_DAT2,
+	PINGRP_SDMMC4_DAT3,
+	PINGRP_SDMMC4_DAT4,
+	PINGRP_SDMMC4_DAT5,
+	PINGRP_SDMMC4_DAT6,
+	PINGRP_SDMMC4_DAT7,
+	PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
+	PINGRP_GPIO_PCC1,
+	PINGRP_GPIO_PBB0,
+	PINGRP_CAM_I2C_SCL,
+	PINGRP_CAM_I2C_SDA,
+	PINGRP_GPIO_PBB3,
+	PINGRP_GPIO_PBB4,
+	PINGRP_GPIO_PBB5,
+	PINGRP_GPIO_PBB6,
+	PINGRP_GPIO_PBB7,
+	PINGRP_GPIO_PCC2,
+	PINGRP_JTAG_RTCK,
+	PINGRP_PWR_I2C_SCL,
+	PINGRP_PWR_I2C_SDA,
+	PINGRP_KB_ROW0,
+	PINGRP_KB_ROW1,
+	PINGRP_KB_ROW2,
+	PINGRP_KB_ROW3,
+	PINGRP_KB_ROW4,
+	PINGRP_KB_ROW5,
+	PINGRP_KB_ROW6,
+	PINGRP_KB_ROW7,
+	PINGRP_KB_ROW8,
+	PINGRP_KB_ROW9,
+	PINGRP_KB_ROW10,
+	PINGRP_KB_ROW11,
+	PINGRP_KB_ROW12,
+	PINGRP_KB_ROW13,
+	PINGRP_KB_ROW14,
+	PINGRP_KB_ROW15,
+	PINGRP_KB_COL0,				/* offset 0x32fc */
+	PINGRP_KB_COL1,
+	PINGRP_KB_COL2,
+	PINGRP_KB_COL3,
+	PINGRP_KB_COL4,
+	PINGRP_KB_COL5,
+	PINGRP_KB_COL6,
+	PINGRP_KB_COL7,
+	PINGRP_CLK_32K_OUT,
+	PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2,	/* offset 0x3324 */
+	PINGRP_CPU_PWR_REQ,
+	PINGRP_PWR_INT_N,
+	PINGRP_CLK_32K_IN,
+	PINGRP_OWR,
+	PINGRP_DAP1_FS,
+	PINGRP_DAP1_DIN,
+	PINGRP_DAP1_DOUT,
+	PINGRP_DAP1_SCLK,
+	PINGRP_CLK1_REQ,
+	PINGRP_CLK1_OUT,
+	PINGRP_SPDIF_IN,
+	PINGRP_SPDIF_OUT,
+	PINGRP_DAP2_FS,
+	PINGRP_DAP2_DIN,
+	PINGRP_DAP2_DOUT,
+	PINGRP_DAP2_SCLK,
+	PINGRP_DVFS_PWM,
+	PINGRP_GPIO_X1_AUD,
+	PINGRP_GPIO_X3_AUD,
+	PINGRP_DVFS_CLK,
+	PINGRP_GPIO_X4_AUD,
+	PINGRP_GPIO_X5_AUD,
+	PINGRP_GPIO_X6_AUD,
+	PINGRP_GPIO_X7_AUD,
+	PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
+	PINGRP_SDMMC3_CMD,
+	PINGRP_SDMMC3_DAT0,
+	PINGRP_SDMMC3_DAT1,
+	PINGRP_SDMMC3_DAT2,
+	PINGRP_SDMMC3_DAT3,
+	PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
+	PINGRP_PEX_L0_CLKREQ,
+	PINGRP_PEX_WAKE,
+	PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
+	PINGRP_PEX_L1_CLKREQ,
+	PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
+	PINGRP_SDMMC1_WP_N,
+	PINGRP_SDMMC3_CD_N,
+	PINGRP_GPIO_W2_AUD,
+	PINGRP_GPIO_W3_AUD,
+	PINGRP_USB_VBUS_EN0,
+	PINGRP_USB_VBUS_EN1,
+	PINGRP_SDMMC3_CLK_LB_IN,
+	PINGRP_SDMMC3_CLK_LB_OUT,
+	PINGRP_GMI_CLK_LB,
+	PINGRP_RESET_OUT_N,
+	PINGRP_KB_ROW16,			/* offset 0x340c */
+	PINGRP_KB_ROW17,
+	PINGRP_USB_VBUS_EN2,
+	PINGRP_GPIO_PFF2,
+	PINGRP_DP_HPD,				/* last reg offset = 0x3430 */
+	PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+	PDRIVE_PINGROUP_AO2,
+	PDRIVE_PINGROUP_AT1,
+	PDRIVE_PINGROUP_AT2,
+	PDRIVE_PINGROUP_AT3,
+	PDRIVE_PINGROUP_AT4,
+	PDRIVE_PINGROUP_AT5,
+	PDRIVE_PINGROUP_CDEV1,
+	PDRIVE_PINGROUP_CDEV2,
+	PDRIVE_PINGROUP_DAP1 = 10,	/* offset 0x890 */
+	PDRIVE_PINGROUP_DAP2,
+	PDRIVE_PINGROUP_DAP3,
+	PDRIVE_PINGROUP_DAP4,
+	PDRIVE_PINGROUP_DBG,
+	PDRIVE_PINGROUP_SDIO3 = 18,	/* offset 0x8B0 */
+	PDRIVE_PINGROUP_SPI,
+	PDRIVE_PINGROUP_UAA,
+	PDRIVE_PINGROUP_UAB,
+	PDRIVE_PINGROUP_UART2,
+	PDRIVE_PINGROUP_UART3,
+	PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
+	PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
+	PDRIVE_PINGROUP_GMA,
+	PDRIVE_PINGROUP_GME = 42,	/* offset 0x910 */
+	PDRIVE_PINGROUP_GMF,
+	PDRIVE_PINGROUP_GMG,
+	PDRIVE_PINGROUP_GMH,
+	PDRIVE_PINGROUP_OWR,
+	PDRIVE_PINGROUP_UAD,
+	PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
+	PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
+	PDRIVE_PINGROUP_AT6 = 75,	/* offset 0x994 */
+	PDRIVE_PINGROUP_DAP5,
+	PDRIVE_PINGROUP_VBUS,
+	PDRIVE_PINGROUP_AO3,
+	PDRIVE_PINGROUP_HVC,
+	PDRIVE_PINGROUP_SDIO4,
+	PDRIVE_PINGROUP_AO0,
+	PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+	PMUX_FUNC_AHB_CLK,
+	PMUX_FUNC_APB_CLK,
+	PMUX_FUNC_AUDIO_SYNC,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DAP3,
+	PMUX_FUNC_DAP4,
+	PMUX_FUNC_DAP5,
+	PMUX_FUNC_DISPA,
+	PMUX_FUNC_DISPB,
+	PMUX_FUNC_EMC_TEST0_DLL,
+	PMUX_FUNC_EMC_TEST1_DLL,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_INT,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_IDE,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_MIPI_HS,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_OSC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PLLA_OUT,
+	PMUX_FUNC_PLLC_OUT1,
+	PMUX_FUNC_PLLM_OUT1,
+	PMUX_FUNC_PLLP_OUT2,
+	PMUX_FUNC_PLLP_OUT3,
+	PMUX_FUNC_PLLP_OUT4,
+	PMUX_FUNC_PWM,
+	PMUX_FUNC_PWR_INTR,
+	PMUX_FUNC_PWR_ON,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SFLASH,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_TWC,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_SENSOR_CLK,
+	PMUX_FUNC_XIO,
+	/* End of Tegra2 MUX selectors */
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAPSDMMC2,
+	PMUX_FUNC_DDR,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT2,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_EMC_DLL,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2C5,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_POPSDIO4,
+	PMUX_FUNC_POPSDMMC4,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	/* End of Tegra3 MUX selectors */
+	PMUX_FUNC_USB,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_RESET_OUT_N,
+	/* End of Tegra114 MUX selectors */
+
+	PMUX_FUNC_SAFE,
+	PMUX_FUNC_MAX,
+
+	PMUX_FUNC_INVALID = 0x4000,
+	PMUX_FUNC_RSVD1 = 0x8000,
+	PMUX_FUNC_RSVD2 = 0x8001,
+	PMUX_FUNC_RSVD3 = 0x8002,
+	PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+	((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
+	(((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+	PMUX_PULL_NORMAL = 0,
+	PMUX_PULL_DOWN,
+	PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+				((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+	PMUX_TRI_NORMAL = 0,
+	PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+	(((tristate) >= PMUX_TRI_NORMAL) && \
+	((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+	PMUX_PIN_OUTPUT = 0,
+	PMUX_PIN_INPUT = 1,
+	PMUX_PIN_NONE,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+				((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+	PMUX_PIN_LOCK_DEFAULT = 0,
+	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+				((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+	PMUX_PIN_OD_DEFAULT = 0,
+	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+				((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+	PMUX_PIN_IO_RESET_DEFAULT = 0,
+	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+enum pmux_pin_rcv_sel {
+	PMUX_PIN_RCV_SEL_DEFAULT = 0,
+	PMUX_PIN_RCV_SEL_NORMAL,
+	PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+				(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+				((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+	PMUX_VDDIO_BB = 0,
+	PMUX_VDDIO_LCD,
+	PMUX_VDDIO_VI,
+	PMUX_VDDIO_UART,
+	PMUX_VDDIO_DDR,
+	PMUX_VDDIO_NAND,
+	PMUX_VDDIO_SYS,
+	PMUX_VDDIO_AUDIO,
+	PMUX_VDDIO_SD,
+	PMUX_VDDIO_CAM,
+	PMUX_VDDIO_GMI,
+	PMUX_VDDIO_PEXCTL,
+	PMUX_VDDIO_SDMMC1,
+	PMUX_VDDIO_SDMMC3,
+	PMUX_VDDIO_SDMMC4,
+
+	PMUX_VDDIO_NONE
+};
+
+#define PGRP_SLWF_NONE	-1
+#define PGRP_SLWF_MAX	3
+#define PGRP_SLWR_NONE	PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX	PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE	-1
+#define PGRP_DRVUP_MAX	127
+#define PGRP_DRVDN_NONE	PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX	PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE	-1
+#define PGRP_HSM_NONE	PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+				(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+				(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+				(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+	PGRP_LPMD_X8 = 0,
+	PGRP_LPMD_X4,
+	PGRP_LPMD_X2,
+	PGRP_LPMD_X,
+	PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+	PGRP_SCHMT_DISABLE = 0,
+	PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+	PGRP_HSM_DISABLE = 0,
+	PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+	enum pdrive_pingrp padgrp;	/* pin group PDRIVE_PINGRP_x */
+	int slwf;			/* falling edge slew         */
+	int slwr;			/* rising edge slew          */
+	int drvup;			/* pull-up drive strength    */
+	int drvdn;			/* pull-down drive strength  */
+	enum pgrp_lpmd lpmd;		/* low-power mode selection  */
+	enum pgrp_schmt schmt;		/* schmidt enable            */
+	enum pgrp_hsm hsm;		/* high-speed mode enable    */
+};
+
+/* Tegra124 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET	(0x868 >> 2)
+#define PMUX_OFFSET	((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+				PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+	uint pmt_reserved0[9];		/* ABP_MISC_PP_ offsets 00-20 */
+	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24        */
+
+	uint pmt_reserved[528];		/* ABP_MISC_PP_ reserved offs 28-864 */
+
+	uint pmt_drive[PDRIVE_PINGROUP_COUNT];	/* pin drive grps offs 868 */
+	uint pmt_reserved5[PMUX_OFFSET];
+	uint pmt_ctl[PINGRP_COUNT];	/* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+	enum pmux_pingrp pingroup;	/* pin group PINGRP_...             */
+	enum pmux_func func;		/* function to assign FUNC_...      */
+	enum pmux_pull pull;		/* pull up/down/normal PMUX_PULL_...*/
+	enum pmux_tristate tristate;	/* tristate or normal PMUX_TRI_...  */
+	enum pmux_pin_io io;		/* input or output PMUX_PIN_...  */
+	enum pmux_pin_lock lock;	/* lock enable/disable PMUX_PIN...  */
+	enum pmux_pin_od od;		/* open-drain or push-pull driver  */
+	enum pmux_pin_ioreset ioreset;	/* input/output reset PMUX_PIN...  */
+	enum pmux_pin_rcv_sel rcv_sel;	/* select between High and Normal  */
+					/* VIL/VIH receivers */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif	/* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h
new file mode 100644
index 0000000..b10100a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pmu.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PMU_H_
+#define _TEGRA124_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA124_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h
new file mode 100644
index 0000000..e266395
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/spl.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h
new file mode 100644
index 0000000..3f0309b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/sysctr.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA124_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
new file mode 100644
index 0000000..db3d837
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define NV_PA_SDRAM_BASE	0x80000000
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE		0x6000C000	/* System regs (AHB, etc.) */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1704	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE	0x48	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU		4
+#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#endif /* _TEGRA124_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h
new file mode 100644
index 0000000..7a2d785
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/usb.h
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_USB_H_
+#define _TEGRA124_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint reserved7_0;
+	uint reserved7_1;
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE		1
+
+#define VBUS_SENSE_CTL_SHIFT			1
+#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB			        (1 << 12)
+#define UTMIP_RESET			        (1 << 11)
+#define USB_PHY_CLK_VALID			(1 << 7)
+#define USB_SUSP_CLR				(1 << 5)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
+
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
+#define UTMIP_PLLU_STABLE_COUNT_MASK		\
+				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
+				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
+				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
+#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
+#define UTMIP_OTGPD				(1 << 11)
+#define UTMIP_BIASPD				(1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT		2
+#define UTMIP_HSDISCON_LEVEL_MASK		\
+				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
+#define UTMIP_HSSQUELCH_LEVEL_MASK		\
+				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN		1
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
+#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J			(1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG				1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL				(1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT			15
+#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT		10
+#define UTMIP_ELASTIC_LIMIT_MASK		\
+				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
+#define UTMIP_HS_SYNC_START_DLY_MASK		\
+				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1					(1 << 3)
+
+/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULPI	2
+#define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
+
+#define STS					(1 << 28)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC				(1 << 22)
+#define WKDS				(1 << 21)
+#define WKCN				(1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
+			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
+#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT		0
+#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
+			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS			(1 << 26)
+
+#endif	/* _TEGRA124_USB_H_ */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index a78f990..04925bc 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -567,7 +567,6 @@ u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -643,6 +642,7 @@ static inline u8 is_dra7xx(void)
 
 /* DRA7XX */
 #define DRA752_ES1_0	0x07520100
+#define DRA752_ES1_1	0x07520110
 
 /*
  * SRAM scratch space entries
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
index 30a3b90..4e2d342 100644
--- a/board/armltd/versatile/versatile.c
+++ b/board/armltd/versatile/versatile.c
@@ -52,7 +52,11 @@ int board_early_init_f (void)
 int board_init (void)
 {
 	/* arch number of Versatile Board */
+#ifdef CONFIG_ARCH_VERSATILE_AB
+	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB;
+#else
 	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
+#endif
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index cbfc7d2..51a3cfe 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -189,6 +189,31 @@ int wait_for_fpga_config(void)
 	return 0;
 }
 
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN	7
+int fpga_reset(void)
+{
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	printf("PCIe reset through GPIO7: ");
+	/* apply PCIe reset via GPIO */
+	kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+	kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+	udelay(1000*10);
+	kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+	printf(" done\n");
+
+	return 0;
+}
+
+#else
+
 #define PRST1		0x4
 #define PCIE_RST	0x10
 #define TRAFFIC_RST	0x04
@@ -219,6 +244,7 @@ int fpga_reset(void)
 
 	return 0;
 }
+#endif
 
 /* the FPGA was configured, we configure the BOCO2 so that the EEPROM
  * is available from the Bobcat SPI bus */
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5620737..35402c8 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = {
 	MPP4_NF_IO6,
 	MPP5_NF_IO7,
 	MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+	MPP7_GPO,
+#else
 	MPP7_PEX_RST_OUTn,
+#endif
 #if defined(CONFIG_SYS_I2C_SOFT)
 	MPP8_GPIO,		/* SDA */
 	MPP9_GPIO,		/* SCL */
@@ -102,7 +106,7 @@ static const u32 kwmpp_config[] = {
 /*
  * Wait for startup OK from mgcoge3ne
  */
-int startup_allowed(void)
+static int startup_allowed(void)
 {
 	unsigned char buf;
 
@@ -164,7 +168,6 @@ static int initialize_unit_leds(void)
 	return 0;
 }
 
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
 static void set_bootcount_addr(void)
 {
 	uchar buf[32];
@@ -173,7 +176,6 @@ static void set_bootcount_addr(void)
 	sprintf((char *)buf, "0x%x", bootcountaddr);
 	setenv("bootcountaddr", (char *)buf);
 }
-#endif
 
 int misc_init_r(void)
 {
@@ -210,9 +212,7 @@ int misc_init_r(void)
 
 	initialize_unit_leds();
 	set_km_env();
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
 	set_bootcount_addr();
-#endif
 	return 0;
 }
 
@@ -322,15 +322,15 @@ void reset_phy(void)
 		return;
 
 	/* RGMII clk transition on data stable */
-	if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
+	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
 		printf("Error reading PHY spec ctrl reg\n");
-	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
-		reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+			 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
 		printf("Error writing PHY spec ctrl reg\n");
 
 	/* leds setup */
-	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
-		PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+			 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
 		printf("Error writing PHY LED reg\n");
 
 	/* reset the phy */
diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt
index 922afea..d3c974f 100644
--- a/board/keymile/scripts/develop-arm.txt
+++ b/board/keymile/scripts/develop-arm.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt
index a6bb1b1..a80812a 100644
--- a/board/keymile/scripts/develop-common.txt
+++ b/board/keymile/scripts/develop-common.txt
@@ -3,6 +3,7 @@ bootcmd=run ${subbootcmds}
 configure=run set_uimage; km_setboardid && saveenv && reset
 subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
 nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
 tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
 toolchain=/opt/eldk
 rootfssize=0
diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt
index 909f6a3..d3c974f 100644
--- a/board/keymile/scripts/develop-ppc_82xx.txt
+++ b/board/keymile/scripts/develop-ppc_82xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt
index 909f6a3..d3c974f 100644
--- a/board/keymile/scripts/develop-ppc_8xx.txt
+++ b/board/keymile/scripts/develop-ppc_8xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt
index 79974f1..87e984e 100644
--- a/board/keymile/scripts/ramfs-arm.txt
+++ b/board/keymile/scripts/ramfs-arm.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt
index 502c863..d79ad2e 100644
--- a/board/keymile/scripts/ramfs-common.txt
+++ b/board/keymile/scripts/ramfs-common.txt
@@ -7,6 +7,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
 configure=run set_uimage; km_setboardid && saveenv && reset
 rootfsfile=${hostname}/rootfsImage
 setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
 tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
 tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
 set_uimage=printenv uimage || setenv uimage uImage
diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt
index 970927a..87e984e 100644
--- a/board/keymile/scripts/ramfs-ppc_82xx.txt
+++ b/board/keymile/scripts/ramfs-ppc_82xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt
index 970927a..87e984e 100644
--- a/board/keymile/scripts/ramfs-ppc_8xx.txt
+++ b/board/keymile/scripts/ramfs-ppc_8xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index e650fed..3b18e28 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -67,12 +67,14 @@ void __gpio_early_init_uart(void)
 void gpio_early_init_uart(void)
 __attribute__((weak, alias("__gpio_early_init_uart")));
 
+#if defined(CONFIG_TEGRA_NAND)
 void __pin_mux_nand(void)
 {
 	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
 }
 
 void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+#endif
 
 void __pin_mux_display(void)
 {
diff --git a/board/nvidia/dts/tegra124-venice2.dts b/board/nvidia/dts/tegra124-venice2.dts
new file mode 100644
index 0000000..2f8d1dc
--- /dev/null
+++ b/board/nvidia/dts/tegra124-venice2.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+	model = "NVIDIA Venice2";
+	compatible = "nvidia,venice2", "nvidia,tegra124";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		i2c5 = "/i2c@7000d100";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
+		spi0 = "/spi@7000d400";
+		spi1 = "/spi@7000da00";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d100 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@700b0400 {
+		status = "okay";
+		cd-gpios = <&gpio 170 0>; /* gpio PV2 */
+		power-gpios = <&gpio 136 0>; /* gpio PR0 */
+		bus-width = <4>;
+	};
+
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+	};
+};
diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile
new file mode 100644
index 0000000..5fac5ab
--- /dev/null
+++ b/board/nvidia/venice2/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= as3722_init.o
+obj-y	+= venice2.o
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
new file mode 100644
index 0000000..960fea7
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+	/* Don't need to set up VDD_CORE - already done - by OTP */
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
new file mode 100644
index 0000000..2a9e7cd
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
new file mode 100644
index 0000000..50868e6
--- /dev/null
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_VENICE2_H_
+#define _PINMUX_CONFIG_VENICE2_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od)	\
+	{								\
+		.pingroup   = PINGRP_##_pingroup,			\
+		.func       = PMUX_FUNC_##_mux,				\
+		.pull       = PMUX_PULL_##_pull,			\
+		.tristate   = PMUX_TRI_##_tri,				\
+		.io         = PMUX_PIN_##_io,				\
+		.lock       = PMUX_PIN_LOCK_##_lock,			\
+		.od         = PMUX_PIN_OD_##_od,			\
+		.ioreset    = PMUX_PIN_IO_RESET_DEFAULT,		\
+	}
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.padgrp = PDRIVE_PINGROUP_##_padgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PGRP_LPMD_##_lpmd,		\
+		.schmt  = PGRP_SCHMT_##_schmt,		\
+		.hsm    = PGRP_HSM_##_hsm,		\
+	}
+
+static struct pingroup_config tegra124_pinmux_common[] = {
+	/* EXTPERIPH1 pinmux */
+	DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S0 pinmux */
+	DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S1 pinmux */
+	DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S3 pinmux */
+	DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLDVFS pinmux */
+	DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* ULPI pinmux */
+	DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4,    ULPI,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+
+	/* EC KBC/SPI */
+	DEFAULT_PINMUX(ULPI_CLK,      SPI1,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DIR,      SPI1,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,      SPI1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_STP,      SPI1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2C3 (TPM) pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* UARTD pinmux (UART4 on Servo board, unused) */
+	DEFAULT_PINMUX(GPIO_PJ7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GPIO_PB0,      UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PB1,      UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PK7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SPI4 (Winbond 'boot ROM') */
+	DEFAULT_PINMUX(GPIO_PG5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PG6,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PG7,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PI3,       SPI4,        NORMAL,    NORMAL,   INPUT),
+
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GPIO_W3_AUD,   RSVD1,       NORMAL,    NORMAL,   INPUT),
+
+	/* PWM1 pinmux */
+	DEFAULT_PINMUX(GPIO_PH1,       PWM1,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      UP,        NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN,  SDMMC3,  UP,        TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,  DOWN,      NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      UP,        NORMAL,   INPUT),
+
+	/* BLINK pinmux */
+	DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* KBC pinmux */
+	DEFAULT_PINMUX(KB_COL0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL1,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL2,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW1,       KBC,         UP,        NORMAL,   INPUT),
+
+	/* Misc */
+	DEFAULT_PINMUX(GPIO_PV0,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(KB_ROW7,       RSVD1,       UP,        NORMAL,   INPUT),
+
+	/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
+	DEFAULT_PINMUX(KB_ROW9,       UARTA,       UP,        NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(KB_ROW10,      UARTA,       UP,        TRISTATE, INPUT),
+
+	/* I2CPWR pinmux (I2C5) */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* RTCK pinmux */
+	DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLK pinmux */
+	DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+	/* PWRON pinmux */
+	DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CPU pinmux */
+	DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+	/* PMI pinmux */
+	DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+	/* RESET_OUT_N pinmux */
+	DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+	/* EXTPERIPH3 pinmux */
+	DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* UARTB, GPS */
+	DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART2_RXD,     UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_TXD,     UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* UARTC (WIFI/BT) */
+	DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CEC pinmux */
+	CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C4 (HDMI_DDC) pinmux */
+	DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+	DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+	/* USB pinmux */
+	USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* Unused, marked SNN_ on schematic, TRISTATE 'em */
+	DEFAULT_PINMUX(GPIO_PBB0,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5,     RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PH3,      GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PI7,      GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PJ2,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_X5_AUD,   RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_X6_AUD,   GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD,   RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PFF2,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(USB_VBUS_EN2,  RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_COL5,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3,       KBC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5,       RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6,       KBC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW13,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW14,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW16,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(OWR,           RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_FS,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK,     RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CLK2_OUT,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC1_WP_N,   RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CLK3_REQ,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(CLK1_REQ,      RSVD3,    DOWN, TRISTATE, OUTPUT),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
+	DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_X7_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD,     RSVD1,  UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X3_AUD,     RSVD3,  UP,      NORMAL,    INPUT),
+
+	/* EN_VDD_BL */
+	DEFAULT_PINMUX(DAP3_DOUT,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+
+	/* MODEM */
+	DEFAULT_PINMUX(GPIO_PV0,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,        RSVD1,  NORMAL,  NORMAL,    INPUT),
+
+	/* BOOT_SEL0-3 */
+	DEFAULT_PINMUX(GPIO_PG0,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG1,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG2,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG3,         GMI,    NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(CLK2_REQ,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+
+	DEFAULT_PINMUX(KB_COL3,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL4,		SDMMC3, UP,	 NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL6,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL7,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_ROW4,         KBC,    DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW8,         KBC,    UP,      NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(GPIO_PU4,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PU5,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(HDMI_INT,        RSVD1,  DOWN,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPDIF_IN,	USB,	NORMAL,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3, UP,       NORMAL,   INPUT),
+
+	/* TS_SHDN_L */
+	DEFAULT_PINMUX(GPIO_PK1,        GMI,    NORMAL,   NORMAL,   OUTPUT),
+};
+
+static struct padctrl_config venice2_padctrl[] = {
+	/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+		       SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
+#endif /* PINMUX_CONFIG_VENICE2_H */
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
new file mode 100644
index 0000000..1ed2fd7
--- /dev/null
+++ b/board/nvidia/venice2/venice2.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-venice2.h"
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra124_pinmux_set_nontristate,
+			    ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+
+	pinmux_config_table(tegra124_pinmux_common,
+			    ARRAY_SIZE(tegra124_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+			    ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
+}
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 22bd6b1..7d2bb8c 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -8,6 +8,7 @@
 obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
 obj-$(CONFIG_THOR_FUNCTION) += thor.o
 obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
+obj-$(CONFIG_MISC_COMMON) += misc.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_BOARD_COMMON)	+= board.o
diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 0000000..d6ee8a2
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
new file mode 100644
index 0000000..eb15739
--- /dev/null
+++ b/board/samsung/common/misc.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <errno.h>
+#include <version.h>
+#include <asm/sizes.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <linux/input.h>
+#include <power/pmic.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+	char info[64];
+
+	snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f,
+		 (s5p_cpu_rev & 0xf0) >> 0x04);
+	setenv("soc_rev", info);
+
+	snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
+	setenv("soc_id", info);
+
+#ifdef CONFIG_REVISION_TAG
+	snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
+	setenv("board_rev", info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+	snprintf(info, ARRAY_SIZE(info),  "%s%x-%s.dtb",
+		 CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD);
+	setenv("fdtfile", info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+#ifdef CONFIG_LCD_MENU
+static int power_key_pressed(u32 reg)
+{
+	struct pmic *pmic;
+	u32 status;
+	u32 mask;
+
+	pmic = pmic_get(KEY_PWR_PMIC_NAME);
+	if (!pmic) {
+		printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+		return 0;
+	}
+
+	if (pmic_probe(pmic))
+		return 0;
+
+	if (reg == KEY_PWR_STATUS_REG)
+		mask = KEY_PWR_STATUS_MASK;
+	else
+		mask = KEY_PWR_INTERRUPT_MASK;
+
+	if (pmic_reg_read(pmic, reg, &status))
+		return 0;
+
+	return !!(status & mask);
+}
+
+static int key_pressed(int key)
+{
+	int value;
+
+	switch (key) {
+	case KEY_POWER:
+		value = power_key_pressed(KEY_PWR_INTERRUPT_REG);
+		break;
+	case KEY_VOLUMEUP:
+		value = !gpio_get_value(KEY_VOL_UP_GPIO);
+		break;
+	case KEY_VOLUMEDOWN:
+		value = !gpio_get_value(KEY_VOL_DOWN_GPIO);
+		break;
+	default:
+		value = 0;
+		break;
+	}
+
+	return value;
+}
+
+static int check_keys(void)
+{
+	int keys = 0;
+
+	if (key_pressed(KEY_POWER))
+		keys += KEY_POWER;
+	if (key_pressed(KEY_VOLUMEUP))
+		keys += KEY_VOLUMEUP;
+	if (key_pressed(KEY_VOLUMEDOWN))
+		keys += KEY_VOLUMEDOWN;
+
+	return keys;
+}
+
+/*
+ * 0 BOOT_MODE_INFO
+ * 1 BOOT_MODE_THOR
+ * 2 BOOT_MODE_UMS
+ * 3 BOOT_MODE_DFU
+ * 4 BOOT_MODE_EXIT
+ */
+static char *
+mode_name[BOOT_MODE_EXIT + 1] = {
+	"DEVICE",
+	"THOR",
+	"UMS",
+	"DFU",
+	"EXIT"
+};
+
+static char *
+mode_info[BOOT_MODE_EXIT + 1] = {
+	"info",
+	"downloader",
+	"mass storage",
+	"firmware update",
+	"and run normal boot"
+};
+
+#define MODE_CMD_ARGC	4
+
+static char *
+mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
+	{"", "", "", ""},
+	{"thor", "0", "mmc", "0"},
+	{"ums", "0", "mmc", "0"},
+	{"dfu", "0", "mmc", "0"},
+	{"", "", "", ""},
+};
+
+static void display_board_info(void)
+{
+#ifdef CONFIG_GENERIC_MMC
+	struct mmc *mmc = find_mmc_device(0);
+#endif
+	vidinfo_t *vid = &panel_info;
+
+	lcd_position_cursor(4, 4);
+
+	lcd_printf("%s\n\t", U_BOOT_VERSION);
+	lcd_puts("\n\t\tBoard Info:\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	lcd_printf("\tBoard rev: %u\n", get_board_rev());
+#endif
+	lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
+	lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
+
+#ifdef CONFIG_GENERIC_MMC
+	if (mmc) {
+		if (!mmc->capacity)
+			mmc_init(mmc);
+
+		lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M);
+	}
+#endif
+	if (vid)
+		lcd_printf("\tDisplay resolution: %u x % u\n",
+			   vid->vl_col, vid->vl_row);
+
+	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
+}
+
+static int mode_leave_menu(int mode)
+{
+	char *exit_option;
+	char *exit_boot = "boot";
+	char *exit_back = "back";
+	cmd_tbl_t *cmd;
+	int cmd_result;
+	int cmd_repeatable;
+	int leave;
+
+	lcd_clear();
+
+	switch (mode) {
+	case BOOT_MODE_EXIT:
+		return 1;
+	case BOOT_MODE_INFO:
+		display_board_info();
+		exit_option = exit_back;
+		leave = 0;
+		break;
+	default:
+		cmd = find_cmd(mode_cmd[mode][0]);
+		if (cmd) {
+			printf("Enter: %s %s\n", mode_name[mode],
+						 mode_info[mode]);
+			lcd_printf("\n\n\t%s %s\n", mode_name[mode],
+						    mode_info[mode]);
+			lcd_puts("\n\tDo not turn off device before finish!\n");
+
+			cmd_result = cmd_process(0, MODE_CMD_ARGC,
+						 *(mode_cmd + mode),
+						 &cmd_repeatable, NULL);
+
+			if (cmd_result == CMD_RET_SUCCESS) {
+				printf("Command finished\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s finished\n",
+					   mode_name[mode]);
+
+				exit_option = exit_boot;
+				leave = 1;
+			} else {
+				printf("Command error\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s command error\n",
+					   mode_name[mode]);
+
+				exit_option = exit_back;
+				leave = 0;
+			}
+		} else {
+			lcd_puts("\n\n\tThis mode is not supported.\n");
+			exit_option = exit_back;
+			leave = 0;
+		}
+	}
+
+	lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option);
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	/* Wait for PWR key */
+	while (!key_pressed(KEY_POWER))
+		mdelay(1);
+
+	lcd_clear();
+	return leave;
+}
+
+static void display_download_menu(int mode)
+{
+	char *selection[BOOT_MODE_EXIT + 1];
+	int i;
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		selection[i] = "[  ]";
+
+	selection[mode] = "[=>]";
+
+	lcd_clear();
+	lcd_printf("\n\t\tDownload Mode Menu\n");
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		lcd_printf("\t%s  %s - %s\n\n", selection[i],
+						mode_name[i],
+						mode_info[i]);
+}
+
+static void download_menu(void)
+{
+	int mode = 0;
+	int last_mode = 0;
+	int run;
+	int key;
+
+	display_download_menu(mode);
+
+	while (1) {
+		run = 0;
+
+		if (mode != last_mode)
+			display_download_menu(mode);
+
+		last_mode = mode;
+		mdelay(100);
+
+		key = check_keys();
+		switch (key) {
+		case KEY_POWER:
+			run = 1;
+			break;
+		case KEY_VOLUMEUP:
+			if (mode > 0)
+				mode--;
+			break;
+		case KEY_VOLUMEDOWN:
+			if (mode < BOOT_MODE_EXIT)
+				mode++;
+			break;
+		default:
+			break;
+		}
+
+		if (run) {
+			if (mode_leave_menu(mode))
+				break;
+
+			display_download_menu(mode);
+		}
+	}
+
+	lcd_clear();
+}
+
+static void display_mode_info(void)
+{
+	lcd_position_cursor(4, 4);
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_puts("\nDownload Mode Menu\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD);
+#endif
+	lcd_printf("Press POWER KEY to display MENU options.");
+}
+
+static int boot_menu(void)
+{
+	int key = 0;
+	int timeout = 10;
+
+	display_mode_info();
+
+	while (timeout--) {
+		lcd_printf("\rNormal boot will start in: %d seconds.", timeout);
+		mdelay(1000);
+
+		key = key_pressed(KEY_POWER);
+		if (key)
+			break;
+	}
+
+	lcd_clear();
+
+	/* If PWR pressed - show download menu */
+	if (key) {
+		printf("Power pressed - go to download menu\n");
+		download_menu();
+		printf("Download mode exit.\n");
+	}
+
+	return 0;
+}
+
+void check_boot_mode(void)
+{
+	int pwr_key;
+
+	pwr_key = power_key_pressed(KEY_PWR_STATUS_REG);
+	if (!pwr_key)
+		return;
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	if (key_pressed(KEY_VOLUMEUP))
+		boot_menu();
+	else if (key_pressed(KEY_VOLUMEDOWN))
+		mode_leave_menu(BOOT_MODE_THOR);
+}
+
+void keys_init(void)
+{
+	/* Set direction to input */
+	gpio_direction_input(KEY_VOL_UP_GPIO);
+	gpio_direction_input(KEY_VOL_DOWN_GPIO);
+}
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+	int x, y;
+	ulong addr;
+
+	addr = panel_info.logo_addr;
+	if (!addr) {
+		error("There is no logo data.");
+		return;
+	}
+
+	if (panel_info.vl_width >= panel_info.logo_width) {
+		x = ((panel_info.vl_width - panel_info.logo_width) >> 1);
+		x += panel_info.logo_x_offset; /* For X center align */
+	} else {
+		x = 0;
+		printf("Warning: image width is bigger than display width\n");
+	}
+
+	if (panel_info.vl_height >= panel_info.logo_height) {
+		y = ((panel_info.vl_height - panel_info.logo_height) >> 1);
+		y += panel_info.logo_y_offset; /* For Y center align */
+	} else {
+		y = 0;
+		printf("Warning: image height is bigger than display height\n");
+	}
+
+	bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
index c4ed346..9020382 100644
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ b/board/samsung/dts/exynos5250-smdk5250.dts
@@ -146,6 +146,6 @@
 	};
 
 	ehci@12110000 {
-		samsung,vbus-gpio = <&gpio 0xbe 0>; /* X26 */
+		samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
 	};
 };
diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts
index 091cdb9..9b48a0c 100644
--- a/board/samsung/dts/exynos5250-snow.dts
+++ b/board/samsung/dts/exynos5250-snow.dts
@@ -110,11 +110,11 @@
 	};
 
 	ehci@12110000 {
-		samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
+		samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
 	};
 
 	xhci@12000000 {
-		samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
+		samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
 	};
 
 	tmu@10060000 {
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 366f648..61b9ece 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -13,10 +13,17 @@
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
 #include <power/max8998_pmic.h>
+#include <samsung/misc.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct s5pc110_gpio *s5pc110_gpio;
 
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
 int board_init(void)
 {
 	/* Set Initial global variables */
@@ -173,3 +180,13 @@ struct s3c_plat_otg_data s5pc110_otg_data = {
 	.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
 };
 #endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 943c29a..a69f73d 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -26,22 +26,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_USB_EHCI_EXYNOS
-static int board_usb_vbus_init(void)
-{
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
-	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
-
-	/* VBUS turn ON time */
-	mdelay(3);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
@@ -56,9 +40,6 @@ static void  board_enable_audio_codec(void)
 
 int exynos_init(void)
 {
-#ifdef CONFIG_USB_EHCI_EXYNOS
-	board_usb_vbus_init();
-#endif
 #ifdef CONFIG_SOUND_MAX98095
 	board_enable_audio_codec();
 #endif
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 640a193..b725505 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -28,6 +28,7 @@
 #include <power/max17042_fg.h>
 #include <usb.h>
 #include <usb_mass_storage.h>
+#include <samsung/misc.h>
 
 #include "setup.h"
 
@@ -742,7 +743,7 @@ vidinfo_t panel_info = {
 	.vl_hsp		= CONFIG_SYS_LOW,
 	.vl_vsp		= CONFIG_SYS_LOW,
 	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= 5,	/* Bits per pixel, 2^5 = 32 */
+	.vl_bpix	= 4,	/* Bits per pixel, 2^4 = 16 */
 
 	/* s6e8ax0 Panel infomation */
 	.vl_hspw	= 5,
@@ -786,3 +787,21 @@ void init_panel_info(vidinfo_t *vid)
 
 	setenv("lcdinfo", "lcd=s6e8ax0");
 }
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index be15357..c17c24d 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -28,6 +28,7 @@
 #include <usb.h>
 #include <usb/s3c_udc.h>
 #include <usb_mass_storage.h>
+#include <samsung/misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -72,15 +73,12 @@ static void check_hw_revision(void)
 int checkboard(void)
 {
 	puts("Board:\tTRATS2\n");
+	printf("HW Revision:\t0x%04x\n", board_rev);
+
 	return 0;
 }
 #endif
 
-static void show_hw_revision(void)
-{
-	printf("HW Revision:\t0x%04x\n", board_rev);
-}
-
 u32 get_board_rev(void)
 {
 	return board_rev;
@@ -144,17 +142,17 @@ static void board_init_i2c(void)
 int get_soft_i2c_scl_pin(void)
 {
 	if (I2C_ADAP_HWNR)
-		return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
+		return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
 	else
-		return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
+		return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
 }
 
 int get_soft_i2c_sda_pin(void)
 {
 	if (I2C_ADAP_HWNR)
-		return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
+		return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
 	else
-		return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
+		return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
 }
 #endif
 
@@ -568,7 +566,7 @@ vidinfo_t panel_info = {
 	.vl_hsp		= CONFIG_SYS_LOW,
 	.vl_vsp		= CONFIG_SYS_LOW,
 	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= 5,	/* Bits per pixel, 2^5 = 32 */
+	.vl_bpix	= 4,	/* Bits per pixel, 2^4 = 16 */
 
 	/* s6e8ax0 Panel infomation */
 	.vl_hspw	= 5,
@@ -618,11 +616,17 @@ void init_panel_info(vidinfo_t *vid)
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
-	setenv("model", "GT-I8800");
-	setenv("board", "TRATS2");
-
-	show_hw_revision();
-
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
 	return 0;
 }
 #endif
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 3feef3f..96da7e0 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -22,6 +22,7 @@
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
 #include <power/max8998_pmic.h>
+#include <samsung/misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -446,7 +447,7 @@ vidinfo_t panel_info = {
 	.vl_vsp		= CONFIG_SYS_HIGH,
 	.vl_dp		= CONFIG_SYS_HIGH,
 
-	.vl_bpix	= 5,	/* Bits per pixel */
+	.vl_bpix	= 4,	/* Bits per pixel */
 
 	/* LD9040 LCD Panel */
 	.vl_hspw	= 2,
@@ -511,3 +512,21 @@ int board_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index ed87cd9..4e6846a 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -188,7 +188,7 @@ const struct ctrl_ioregs ioregs_ddr3 = {
 	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
 	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
 	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
-	.emif_sdram_config_ext	= 0x0043,
+	.emif_sdram_config_ext	= 0x0143,
 };
 
 const struct emif_regs ddr3_emif_regs_400Mhz = {
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index af854da..b549d72 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -157,19 +157,6 @@ void set_muxconf_regs_essential(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-void set_muxconf_regs_non_essential(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_non_essential,
-		   sizeof(core_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_non_essential,
-		   sizeof(wkup_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-}
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
index 31ce363..de7ce9f 100644
--- a/board/ti/omap5_uevm/mux_data.h
+++ b/board/ti/omap5_uevm/mux_data.h
@@ -55,238 +55,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
 
 };
 
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-
-	{C2C_DATAIN0, (IEN | M0)},    /*  C2C_DATAIN0   */
-	{C2C_DATAIN1, (IEN | M0)},    /*  C2C_DATAIN1   */
-	{C2C_DATAIN2, (IEN | M0)},    /*  C2C_DATAIN2   */
-	{C2C_DATAIN3, (IEN | M0)},    /*  C2C_DATAIN3   */
-	{C2C_DATAIN4, (IEN | M0)},    /*  C2C_DATAIN4   */
-	{C2C_DATAIN5, (IEN | M0)},    /*  C2C_DATAIN5   */
-	{C2C_DATAIN6, (IEN | M0)},    /*  C2C_DATAIN6   */
-	{C2C_DATAIN7, (IEN | M0)},    /*  C2C_DATAIN7   */
-	{C2C_CLKIN1,  (IEN | M0)},    /*  C2C_CLKIN1    */
-	{C2C_CLKIN0,  (IEN | M0)},    /*  C2C_CLKIN0    */
-	{C2C_CLKOUT0, (M0)},    /*  C2C_CLKOUT0   */
-	{C2C_CLKOUT1, (M0)},    /*  C2C_CLKOUT1   */
-	{C2C_DATAOUT0, (M0)},    /*  C2C_DATAOUT0  */
-	{C2C_DATAOUT1, (M0)},    /*  C2C_DATAOUT1  */
-	{C2C_DATAOUT2, (M0)},    /*  C2C_DATAOUT2  */
-	{C2C_DATAOUT3, (M0)},    /*  C2C_DATAOUT3  */
-	{C2C_DATAOUT4, (M0)},    /*  C2C_DATAOUT4  */
-	{C2C_DATAOUT5, (M0)},    /*  C2C_DATAOUT5  */
-	{C2C_DATAOUT6, (M0)},    /*  C2C_DATAOUT6  */
-	{C2C_DATAOUT7, (M0)},    /*  C2C_DATAOUT7  */
-	{C2C_DATA8, (IEN | M0)},    /*  C2C_DATA8     */
-	{C2C_DATA9, (IEN | M0)},    /*  C2C_DATA9     */
-	{C2C_DATA10, (IEN | M0)},    /*  C2C_DATA10    */
-	{C2C_DATA11, (IEN | M0)},    /*  C2C_DATA11    */
-	{C2C_DATA12, (IEN | M0)},    /*  C2C_DATA12    */
-	{C2C_DATA13, (IEN | M0)},    /*  C2C_DATA13    */
-	{C2C_DATA14, (IEN | M0)},    /*  C2C_DATA14    */
-	{C2C_DATA15, (IEN | M0)},    /*  C2C_DATA15    */
-	{LLIB_WAKEREQOUT, (PTU | IEN | M6)},    /*  GPIO2_32      */
-	{LLIA_WAKEREQOUT, (M1)},    /*  C2C_WAKEREQOUT */
-	{HSI1_ACREADY, (PTD | M6)},    /*  GPIO3_64  */
-	{HSI1_CAREADY, (PTD | M6)},    /*  GPIO3_65  */
-	{HSI1_ACWAKE,  (PTD | IEN | M6)},    /*  GPIO3_66  */
-	{HSI1_CAWAKE,  (PTU | IEN | M6)},    /*  GPIO3_67  */
-	{HSI1_ACFLAG,  (PTD | IEN | M6)},    /*  GPIO3_68  */
-	{HSI1_ACDATA,  (PTD | M6)},    /*  GPIO3_69  */
-	{HSI1_CAFLAG,  (M6)},    /*  GPIO3_70  */
-	{HSI1_CADATA,  (M6)},    /*  GPIO3_71  */
-	{UART1_TX, (M0)},    /*  UART1_TX  */
-	{UART1_CTS, (PTU | IEN | M0)},    /*  UART1_CTS */
-	{UART1_RX, (PTU | IEN | M0)},    /*  UART1_RX  */
-	{UART1_RTS, (M0)},    /*  UART1_RTS */
-	{HSI2_CAREADY, (IEN | M0)},    /*  HSI2_CAREADY */
-	{HSI2_ACREADY, (OFF_EN | M0)},    /*  HSI2_ACREADY */
-	{HSI2_CAWAKE, (IEN | PTD | M0)},    /*  HSI2_CAWAKE  */
-	{HSI2_ACWAKE, (M0)},    /*  HSI2_ACWAKE  */
-	{HSI2_CAFLAG, (IEN | PTD | M0)},    /*  HSI2_CAFLAG  */
-	{HSI2_CADATA, (IEN | PTD | M0)},    /*  HSI2_CADATA  */
-	{HSI2_ACFLAG, (M0)},    /*  HSI2_ACFLAG  */
-	{HSI2_ACDATA, (M0)},    /*  HSI2_ACDATA  */
-	{UART2_RTS, (IEN | M1)},    /*  MCSPI3_SOMI  */
-	{UART2_CTS, (IEN | M1)},    /*  MCSPI3_CS0   */
-	{UART2_RX, (IEN | M1)},    /*  MCSPI3_SIMO  */
-	{UART2_TX, (IEN | M1)},    /*  MCSPI3_CLK   */
-	{TIMER10_PWM_EVT, (IEN | M0)},    /*  TIMER10_PWM_EVT  */
-	{DSIPORTA_TE0, (IEN | M0)},    /*  DSIPORTA_TE0     */
-	{DSIPORTA_LANE0X, (IEN | M0)},    /*  DSIPORTA_LANE0X  */
-	{DSIPORTA_LANE0Y, (IEN | M0)},    /*  DSIPORTA_LANE0Y  */
-	{DSIPORTA_LANE1X, (IEN | M0)},    /*  DSIPORTA_LANE1X  */
-	{DSIPORTA_LANE1Y, (IEN | M0)},    /*  DSIPORTA_LANE1Y  */
-	{DSIPORTA_LANE2X, (IEN | M0)},    /*  DSIPORTA_LANE2X  */
-	{DSIPORTA_LANE2Y, (IEN | M0)},    /*  DSIPORTA_LANE2Y  */
-	{DSIPORTA_LANE3X, (IEN | M0)},    /*  DSIPORTA_LANE3X  */
-	{DSIPORTA_LANE3Y, (IEN | M0)},    /*  DSIPORTA_LANE3Y  */
-	{DSIPORTA_LANE4X, (IEN | M0)},    /*  DSIPORTA_LANE4X  */
-	{DSIPORTA_LANE4Y, (IEN | M0)},    /*  DSIPORTA_LANE4Y  */
-	{TIMER9_PWM_EVT, (IEN | M0)},    /*  TIMER9_PWM_EVT   */
-	{DSIPORTC_TE0, (IEN | M0)},    /*  DSIPORTC_TE0     */
-	{DSIPORTC_LANE0X, (IEN | M0)},    /*  DSIPORTC_LANE0X  */
-	{DSIPORTC_LANE0Y, (IEN | M0)},    /*  DSIPORTC_LANE0Y  */
-	{DSIPORTC_LANE1X, (IEN | M0)},    /*  DSIPORTC_LANE1X  */
-	{DSIPORTC_LANE1Y, (IEN | M0)},    /*  DSIPORTC_LANE1Y  */
-	{DSIPORTC_LANE2X, (IEN | M0)},    /*  DSIPORTC_LANE2X  */
-	{DSIPORTC_LANE2Y, (IEN | M0)},    /*  DSIPORTC_LANE2Y  */
-	{DSIPORTC_LANE3X, (IEN | M0)},    /*  DSIPORTC_LANE3X  */
-	{DSIPORTC_LANE3Y, (IEN | M0)},    /*  DSIPORTC_LANE3Y  */
-	{DSIPORTC_LANE4X, (IEN | M0)},    /*  DSIPORTC_LANE4X  */
-	{DSIPORTC_LANE4Y, (IEN | M0)},    /*  DSIPORTC_LANE4Y  */
-	{RFBI_HSYNC0, (M4)},    /*  KBD_COL5   */
-	{RFBI_TE_VSYNC0, (PTD | M6)},    /*  GPIO6_161  */
-	{RFBI_RE, (M4)},    /*  KBD_COL4   */
-	{RFBI_A0, (PTD | IEN | M6)},    /*  GPIO6_165  */
-	{RFBI_DATA8, (M4)},    /*  KBD_COL3   */
-	{RFBI_DATA9, (PTD | M6)},    /*  GPIO6_175  */
-	{RFBI_DATA10, (PTD | M6)},    /*  GPIO6_176  */
-	{RFBI_DATA11, (PTD | M6)},    /*  GPIO6_177  */
-	{RFBI_DATA12, (PTD | M6)},    /*  GPIO6_178  */
-	{RFBI_DATA13, (PTU | IEN | M6)},    /*  GPIO6_179  */
-	{RFBI_DATA14, (M4)},    /*  KBD_COL7   */
-	{RFBI_DATA15, (M4)},    /*  KBD_COL6   */
-	{GPIO6_182, (M6)},    /*  GPIO6_182  */
-	{GPIO6_183, (PTD | M6)},    /*  GPIO6_183  */
-	{GPIO6_184, (M4)},    /*  KBD_COL2   */
-	{GPIO6_185, (PTD | IEN | M6)},    /*  GPIO6_185  */
-	{GPIO6_186, (PTD | M6)},    /*  GPIO6_186  */
-	{GPIO6_187, (PTU | IEN | M4)},    /*  KBD_ROW2   */
-	{RFBI_DATA0, (PTD | M6)},    /*  GPIO6_166  */
-	{RFBI_DATA1, (PTD | M6)},    /*  GPIO6_167  */
-	{RFBI_DATA2, (PTD | M6)},    /*  GPIO6_168  */
-	{RFBI_DATA3, (PTD | IEN | M6)},    /*  GPIO6_169  */
-	{RFBI_DATA4, (IEN | M6)},    /*  GPIO6_170  */
-	{RFBI_DATA5, (IEN | M6)},    /*  GPIO6_171  */
-	{RFBI_DATA6, (PTD | M6)},    /*  GPIO6_172  */
-	{RFBI_DATA7, (PTD | M6)},    /*  GPIO6_173  */
-	{RFBI_CS0, (PTD | IEN | M6)},    /*  GPIO6_163  */
-	{RFBI_WE, (PTD | M6)},    /*  GPIO6_162  */
-	{MCSPI2_CS0, (M0)},    /*  MCSPI2_CS0 */
-	{MCSPI2_CLK, (IEN | M0)},    /*  MCSPI2_CLK */
-	{MCSPI2_SIMO, (IEN | M0)},    /*  MCSPI2_SIMO*/
-	{MCSPI2_SOMI, (PTU | IEN | M0)},    /*  MCSPI2_SOMI*/
-	{I2C4_SCL, (IEN | M0)},    /*  I2C4_SCL   */
-	{I2C4_SDA, (IEN | M0)},    /*  I2C4_SDA   */
-	{HDMI_CEC, (IEN | M0)},    /*  HDMI_CEC   */
-	{HDMI_HPD, (PTD | IEN | M0)},    /*  HDMI_HPD   */
-	{HDMI_DDC_SCL, (IEN | M0)},    /*  HDMI_DDC_SCL */
-	{HDMI_DDC_SDA, (IEN | M0)},    /*  HDMI_DDC_SDA */
-	{CSIPORTA_LANE0X, (IEN | M0)},    /*  CSIPORTA_LANE0X  */
-	{CSIPORTA_LANE0Y, (IEN | M0)},    /*  CSIPORTA_LANE0Y  */
-	{CSIPORTA_LANE1Y, (IEN | M0)},    /*  CSIPORTA_LANE1Y  */
-	{CSIPORTA_LANE1X, (IEN | M0)},    /*  CSIPORTA_LANE1X  */
-	{CSIPORTA_LANE2Y, (IEN | M0)},    /*  CSIPORTA_LANE2Y  */
-	{CSIPORTA_LANE2X, (IEN | M0)},    /*  CSIPORTA_LANE2X  */
-	{CSIPORTA_LANE3X, (IEN | M0)},    /*  CSIPORTA_LANE3X  */
-	{CSIPORTA_LANE3Y, (IEN | M0)},    /*  CSIPORTA_LANE3Y  */
-	{CSIPORTA_LANE4X, (IEN | M0)},    /*  CSIPORTA_LANE4X  */
-	{CSIPORTA_LANE4Y, (IEN | M0)},    /*  CSIPORTA_LANE4Y  */
-	{CSIPORTB_LANE0X, (IEN | M0)},    /*  CSIPORTB_LANE0X  */
-	{CSIPORTB_LANE0Y, (IEN | M0)},    /*  CSIPORTB_LANE0Y  */
-	{CSIPORTB_LANE1Y, (IEN | M0)},    /*  CSIPORTB_LANE1Y  */
-	{CSIPORTB_LANE1X, (IEN | M0)},    /*  CSIPORTB_LANE1X  */
-	{CSIPORTB_LANE2Y, (IEN | M0)},    /*  CSIPORTB_LANE2Y  */
-	{CSIPORTB_LANE2X, (IEN | M0)},    /*  CSIPORTB_LANE2X  */
-	{CSIPORTC_LANE0Y, (IEN | M0)},    /*  CSIPORTC_LANE0Y  */
-	{CSIPORTC_LANE0X, (IEN | M0)},    /*  CSIPORTC_LANE0X  */
-	{CSIPORTC_LANE1Y, (IEN | M0)},    /*  CSIPORTC_LANE1Y  */
-	{CSIPORTC_LANE1X, (IEN | M0)},    /*  CSIPORTC_LANE1X  */
-	{CAM_SHUTTER, (M0)},    /*  CAM_SHUTTER      */
-	{CAM_STROBE, (M0)},    /*  CAM_STROBE       */
-	{CAM_GLOBALRESET, (IEN | M0)},    /*  CAM_GLOBALRESET  */
-	{TIMER11_PWM_EVT, (PTD | M6)},    /*  GPIO8_227  */
-	{TIMER5_PWM_EVT, (PTD | M6)},    /*  GPIO8_228  */
-	{TIMER6_PWM_EVT, (PTD | M6)},    /*  GPIO8_229  */
-	{TIMER8_PWM_EVT,      (PTU | M6)},    /*  GPIO8_230  */
-	{I2C3_SCL, (IEN | M0)},    /*  I2C3_SCL   */
-	{I2C3_SDA, (IEN | M0)},    /*  I2C3_SDA   */
-	{GPIO8_233, (IEN | M2)},    /*  TIMER8_PWM_EVT   */
-	{ABE_CLKS, (IEN | M0)},    /*  ABE_CLKS  */
-	{ABEDMIC_DIN1, (IEN | M0)},    /*  ABEDMIC_DIN1 */
-	{ABEDMIC_DIN2, (IEN | M0)},    /*  ABEDMIC_DIN2 */
-	{ABEDMIC_DIN3, (IEN | M0)},    /*  ABEDMIC_DIN3 */
-	{ABEDMIC_CLK1, (M0)},    /*  ABEDMIC_CLK1 */
-	{ABEDMIC_CLK2, (IEN | M1)},    /*  ABEMCBSP1_FSX */
-	{ABEDMIC_CLK3, (M1)},    /*  ABEMCBSP1_DX  */
-	{ABESLIMBUS1_CLOCK, (IEN | M1)},    /*  ABEMCBSP1_CLKX   */
-	{ABESLIMBUS1_DATA, (IEN | M1)},    /*  ABEMCBSP1_DR */
-	{ABEMCBSP2_DR, (IEN | M0)},    /*  ABEMCBSP2_DR */
-	{ABEMCBSP2_DX, (M0)},    /*  ABEMCBSP2_DX */
-	{ABEMCBSP2_FSX, (IEN | M0)},    /*  ABEMCBSP2_FSX  */
-	{ABEMCBSP2_CLKX, (IEN | M0)},    /*  ABEMCBSP2_CLKX */
-	{ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_UL_DATA */
-	{ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_DL_DATA */
-	{ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_FRAME   */
-	{ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_LB_CLK  */
-	{WLSDIO_CLK, (PTU | IEN | M0)},    /*  WLSDIO_CLK  */
-	{WLSDIO_CMD, (PTU | IEN | M0)},    /*  WLSDIO_CMD  */
-	{WLSDIO_DATA0, (PTU | IEN | M0)},    /*  WLSDIO_DATA0*/
-	{WLSDIO_DATA1, (PTU | IEN | M0)},    /*  WLSDIO_DATA1*/
-	{WLSDIO_DATA2, (PTU | IEN | M0)},    /*  WLSDIO_DATA2*/
-	{WLSDIO_DATA3, (PTU | IEN | M0)},    /*  WLSDIO_DATA3*/
-	{UART5_RX, (PTU | IEN | M0)},    /*  UART5_RX    */
-	{UART5_TX, (M0)},    /*  UART5_TX    */
-	{UART5_CTS, (PTU | IEN | M0)},    /*  UART5_CTS   */
-	{UART5_RTS, (M0)},    /*  UART5_RTS   */
-	{I2C2_SCL, (IEN | M0)},    /*  I2C2_SCL    */
-	{I2C2_SDA, (IEN | M0)},    /*  I2C2_SDA    */
-	{MCSPI1_CLK, (M6)},    /*  GPIO5_140   */
-	{MCSPI1_SOMI, (IEN | M6)},    /*  GPIO5_141   */
-	{MCSPI1_SIMO, (PTD | M6)},    /*  GPIO5_142   */
-	{MCSPI1_CS0, (PTD | M6)},    /*  GPIO5_143   */
-	{MCSPI1_CS1, (PTD | IEN | M6)},    /*  GPIO5_144   */
-	{I2C5_SCL, (IEN | M0)},    /*  I2C5_SCL    */
-	{I2C5_SDA, (IEN | M0)},    /*  I2C5_SDA    */
-	{PERSLIMBUS2_CLOCK, (PTD | M6)},    /*  GPIO5_145   */
-	{PERSLIMBUS2_DATA, (PTD | IEN | M6)},    /*  GPIO5_146   */
-	{UART6_TX, (PTU | IEN | M6)},    /*  GPIO5_149   */
-	{UART6_RX, (PTU | IEN | M6)},    /*  GPIO5_150   */
-	{UART6_CTS, (PTU | IEN | M6)},    /*  GPIO5_151   */
-	{UART6_RTS, (PTU | M0)},    /*  UART6_RTS   */
-	{UART3_CTS_RCTX, (PTU | IEN | M6)},    /*  GPIO5_153   */
-	{UART3_RTS_IRSD, (PTU | IEN | M1)},    /*  HDQ_SIO     */
-	{I2C1_PMIC_SCL, (PTU | IEN | M0)},    /*  I2C1_PMIC_SCL  */
-	{I2C1_PMIC_SDA, (PTU | IEN | M0)},    /*  I2C1_PMIC_SDA  */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-
-/*
- * This pad keeps C2C Module always enabled.
- * Putting this in safe mode do not cause the issue.
- * C2C driver could enable this mux setting if needed.
- */
-	{LLIA_WAKEREQIN, (M7)},    /*  SAFE MODE  */
-	{LLIB_WAKEREQIN, (M7)},    /*  SAFE MODE  */
-	{DRM_EMU0, (PTU | IEN | M0)},    /*  DRM_EMU0    */
-	{DRM_EMU1, (PTU | IEN | M0)},    /*  DRM_EMU1    */
-	{JTAG_NTRST, (IEN | M0)},    /*  JTAG_NTRST  */
-	{JTAG_TCK, (IEN | M0)},    /*  JTAG_TCK    */
-	{JTAG_RTCK, (M0)},    /*  JTAG_RTCK   */
-	{JTAG_TMSC, (IEN | M0)},    /*  JTAG_TMSC   */
-	{JTAG_TDI, (IEN | M0)},    /*  JTAG_TDI    */
-	{JTAG_TDO, (M0)},    /*  JTAG_TDO    */
-	{FREF_CLK_IOREQ, (IEN | M0)},    /*  FREF_CLK_IOREQ */
-	{FREF_CLK0_OUT, (M0)},    /*  FREF_CLK0_OUT  */
-	{FREF_CLK1_OUT, (M0)},    /*  FREF_CLK1_OUT  */
-	{FREF_CLK2_OUT, (M0)},    /*  FREF_CLK2_OUT  */
-	{FREF_CLK2_REQ, (PTU | IEN | M6)},    /*  GPIO1_WK9      */
-	{FREF_CLK1_REQ, (PTD | IEN | M6)},    /*  GPIO1_WK8      */
-	{SYS_NRESPWRON, (IEN | M0)},    /*  SYS_NRESPWRON  */
-	{SYS_NRESWARM, (PTU | IEN | M0)},    /*  SYS_NRESWARM   */
-	{SYS_PWR_REQ, (M0)},    /*  SYS_PWR_REQ    */
-	{SYS_NIRQ1, (PTU | IEN | M0)},    /*  SYS_NIRQ1      */
-	{SYS_NIRQ2, (PTU | IEN | M0)},    /*  SYS_NIRQ2      */
-	{SYS_BOOT0, (IEN | M0)},    /*  SYS_BOOT0      */
-	{SYS_BOOT1, (IEN | M0)},    /*  SYS_BOOT1      */
-	{SYS_BOOT2, (IEN | M0)},    /*  SYS_BOOT2      */
-	{SYS_BOOT3, (IEN | M0)},    /*  SYS_BOOT3      */
-	{SYS_BOOT4, (IEN | M0)},    /*  SYS_BOOT4      */
-	{SYS_BOOT5, (IEN | M0)},    /*  SYS_BOOT5      */
-
-};
-
 #endif /* _EVM4430_MUX_DATA_H */
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index cda09a9..5ab6db9 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -284,36 +284,6 @@ void set_muxconf_regs_essential(void)
 			   sizeof(struct pad_conf_entry));
 }
 
-void set_muxconf_regs_non_essential(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_non_essential,
-		   sizeof(core_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() < OMAP4460_ES1_0)
-		do_set_mux((*ctrl)->control_padconf_core_base,
-			   core_padconf_array_non_essential_4430,
-			   sizeof(core_padconf_array_non_essential_4430) /
-			   sizeof(struct pad_conf_entry));
-	else
-		do_set_mux((*ctrl)->control_padconf_core_base,
-			   core_padconf_array_non_essential_4460,
-			   sizeof(core_padconf_array_non_essential_4460) /
-			   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_non_essential,
-		   sizeof(wkup_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() < OMAP4460_ES1_0)
-		do_set_mux((*ctrl)->control_padconf_wkup_base,
-			   wkup_padconf_array_non_essential_4430,
-			   sizeof(wkup_padconf_array_non_essential_4430) /
-			   sizeof(struct pad_conf_entry));
-}
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index fb83eac..53c7080 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -84,190 +84,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
 
 };
 
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
-	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
-	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
-	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
-	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
-	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
-	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
-	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
-	{GPMC_A16, (M3)},						/* gpio_40 */
-	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
-	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
-	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
-	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
-	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
-	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
-	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
-	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
-	{GPMC_NCS0, (M3)},						/* gpio_50 */
-	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
-	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
-	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
-	{GPMC_NWP, (M3)},						/* gpio_54 */
-	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
-	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
-	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
-	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
-	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
-	{C2C_DATA14, (M1)},						/* dsi2_te0 */
-	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
-	{HDMI_HPD, (M0)},						/* hdmi_hpd */
-	{HDMI_CEC, (M0)},						/* hdmi_cec */
-	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
-	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
-	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
-	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
-	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
-	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
-	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
-	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
-	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
-	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
-	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
-	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
-	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
-	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
-	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
-	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
-	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
-	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
-	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
-	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
-	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M0)},					/* abe_mcbsp1_clkx */
-	{ABE_MCBSP1_DR, (IEN | M0)},					/* abe_mcbsp1_dr */
-	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
-	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
-	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
-	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
-	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
-	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
-	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
-	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
-	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
-	{ABE_DMIC_DIN2, (PTU | IEN | M3)},				/* gpio_121 */
-	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
-	{UART2_CTS, (PTU | IEN | M7)},					/* uart2_cts */
-	{UART2_RTS, (M7)},						/* uart2_rts */
-	{UART2_RX, (PTU | IEN | M7)},					/* uart2_rx */
-	{UART2_TX, (M7)},						/* uart2_tx */
-	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
-	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
-	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
-	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
-	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
-	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
-	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
-	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
-	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
-	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
-	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
-	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
-	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
-	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
-	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
-	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
-	{UART4_RX, (IEN | M0)},						/* uart4_rx */
-	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
-	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
-	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
-	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
-	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
-	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
-	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
-	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
-	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
-	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
-	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
-	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
-	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
-	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
-	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
-	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
-	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
-	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
-	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
-	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
-	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
-	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
-	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
-	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
-	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
-	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
-	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
-	{SYS_BOOT1, (M3)},						/* gpio_185 */
-	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
-	{SYS_BOOT4, (M3)},						/* gpio_188 */
-	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
-	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
-	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
-	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
-	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
-	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
-	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
-	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
-	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
-	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
-	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
-	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
-	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
-	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
-	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
-	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
-	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
-	{DPM_EMU16, (M3)},						/* gpio_27 */
-	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
-	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
-	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
-};
-
-const struct pad_conf_entry core_padconf_array_non_essential_4430[] = {
-	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
-};
-
-const struct pad_conf_entry core_padconf_array_non_essential_4460[] = {
-	{ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* led status_1 */
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
-	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, M7},		/* safe mode */
-	{PAD0_FREF_CLK4_OUT, (PTU | M3)},	/* led status_2 */
-	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
-	{PAD1_FREF_CLK4_REQ, (PTU | M3)},	/* led status_1 */
-};
-
 #endif /* _PANDA_MUX_DATA_H_ */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 79270a9..1e9ef9e 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -73,26 +73,6 @@ void set_muxconf_regs_essential(void)
 				 sizeof(struct pad_conf_entry));
 }
 
-void set_muxconf_regs_non_essential(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_non_essential,
-		   sizeof(core_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_non_essential,
-		   sizeof(wkup_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() < OMAP4460_ES1_0) {
-		do_set_mux((*ctrl)->control_padconf_wkup_base,
-			wkup_padconf_array_non_essential_4430,
-			sizeof(wkup_padconf_array_non_essential_4430) /
-			sizeof(struct pad_conf_entry));
-	}
-}
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index 4394dba..9a9efe7 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -65,201 +65,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
 
 };
 
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
-	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
-	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
-	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
-	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
-	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
-	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
-	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
-	{GPMC_A16, (M3)},						/* gpio_40 */
-	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
-	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
-	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
-	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
-	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
-	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
-	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
-	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
-	{GPMC_NCS0, (M3)},						/* gpio_50 */
-	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
-	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
-	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
-	{GPMC_NWP, (M3)},						/* gpio_54 */
-	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
-	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
-	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
-	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
-	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (M1)},						/* dsi1_te0 */
-	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
-	{C2C_DATA14, (M1)},						/* dsi2_te0 */
-	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
-	{HDMI_HPD, (M0)},						/* hdmi_hpd */
-	{HDMI_CEC, (M0)},						/* hdmi_cec */
-	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
-	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
-	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
-	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
-	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
-	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
-	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
-	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
-	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
-	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
-	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
-	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
-	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
-	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
-	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
-	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
-	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
-	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
-	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
-	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
-	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
-	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
-	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
-	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
-	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
-	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
-	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
-	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
-	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
-	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
-	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
-	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
-	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
-	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
-	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
-	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
-	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
-	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
-	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
-	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
-	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
-	{UART2_RTS, (M0)},						/* uart2_rts */
-	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
-	{UART2_TX, (M0)},						/* uart2_tx */
-	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
-	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
-	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
-	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
-	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
-	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
-	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
-	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
-	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
-	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
-	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
-	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
-	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
-	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
-	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
-	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
-	{UART4_RX, (IEN | M0)},						/* uart4_rx */
-	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
-	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
-	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
-	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
-	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
-	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
-	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
-	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
-	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
-	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
-	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
-	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
-	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
-	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
-	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
-	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
-	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
-	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
-	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
-	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
-	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
-	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
-	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
-	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
-	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
-	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
-	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
-	{SYS_BOOT1, (M3)},						/* gpio_185 */
-	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
-	{SYS_BOOT4, (M3)},						/* gpio_188 */
-	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
-	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
-	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
-	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
-	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
-	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
-	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
-	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
-	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
-	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
-	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
-	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
-	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
-	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
-	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
-	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
-	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
-	{DPM_EMU16, (M3)},						/* gpio_27 */
-	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
-	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
-	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)}					/* i2c4_sda */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
-	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 - Debug led-1 */
-	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 - Debug led-3 */
-	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
-	{PAD1_FREF_CLK4_REQ, (M3)}	/* gpio_wk7 - Debug led-2 */
-};
-
 #endif /* _SDP4430_MUX_DATA_H */
diff --git a/boards.cfg b/boards.cfg
index c97c4bd..7a8688a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -173,6 +173,7 @@ Active  arm         arm926ejs      kirkwood    keymile         km_arm
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              km_kirkwood_pci                      km_kirkwood:KM_KIRKWOOD_PCI                                                                                                       Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmcoge5un                            km_kirkwood:KM_COGE5UN                                                                                                            Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmnusa                               km_kirkwood:KM_NUSA                                                                                                               Valentin Longchamp <valentin.longchamp@keymile.com>
+Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmsugp1                              km_kirkwood:KM_SUGP1                                                                                                              Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmsuv31                              km_kirkwood:KM_SUV31                                                                                                              Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              mgcoge3un                            km_kirkwood:KM_MGCOGE3UN                                                                                                          Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              portl2                               km_kirkwood:KM_PORTL2                                                                                                             Valentin Longchamp <valentin.longchamp@keymile.com>
@@ -364,6 +365,7 @@ Active  arm         armv7          zynq        xilinx          zynq
 Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_xm013                     zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 Active  arm         armv7          zynq        xilinx          zynq                zynq_zed                             -                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
+Active  arm         armv7:arm720t  tegra124    nvidia          venice2             venice2                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
diff --git a/common/lcd.c b/common/lcd.c
index 56bf067..aa81522 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -26,7 +26,7 @@
 #endif
 #include <lcd.h>
 #include <watchdog.h>
-
+#include <asm/unaligned.h>
 #include <splash.h>
 
 #if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
@@ -777,9 +777,9 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb,
 	int x, y;
 	int decode = 1;
 
-	width = le32_to_cpu(bmp->header.width);
-	height = le32_to_cpu(bmp->header.height);
-	bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
+	width = get_unaligned_le32(&bmp->header.width);
+	height = get_unaligned_le32(&bmp->header.height);
+	bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
 
 	x = 0;
 	y = height - 1;
@@ -900,9 +900,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		return 1;
 	}
 
-	width = le32_to_cpu(bmp->header.width);
-	height = le32_to_cpu(bmp->header.height);
-	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	width = get_unaligned_le32(&bmp->header.width);
+	height = get_unaligned_le32(&bmp->header.height);
+	bmp_bpix = get_unaligned_le16(&bmp->header.bit_count);
+
 	colors = 1 << bmp_bpix;
 
 	bpix = NBITS(panel_info.vl_bpix);
@@ -917,9 +918,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	/* We support displaying 8bpp BMPs on 16bpp LCDs */
 	if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
-			bpix,
-			le16_to_cpu(bmp->header.bit_count));
-
+			bpix, get_unaligned_le16(&bmp->header.bit_count));
 		return 1;
 	}
 
@@ -956,7 +955,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		}
 	}
 #endif
-
 	/*
 	 *  BMP format for Monochrome assumes that the state of a
 	 * pixel is described on a per Bit basis, not per Byte.
@@ -987,15 +985,16 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	if ((y + height) > panel_info.vl_row)
 		height = panel_info.vl_row - y;
 
-	bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
-	fb   = (uchar *) (lcd_base +
+	bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
+	fb   = (uchar *)(lcd_base +
 		(y + height - 1) * lcd_line_length + x * bpix / 8);
 
 	switch (bmp_bpix) {
 	case 1: /* pass through */
 	case 8:
 #ifdef CONFIG_LCD_BMP_RLE8
-		if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) {
+		u32 compression = get_unaligned_le32(&bmp->header.compression);
+		if (compression == BMP_BI_RLE8) {
 			if (bpix != 16) {
 				/* TODO implement render code for bpix != 16 */
 				printf("Error: only support 16 bpix");
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index 1c79c14..16819c7 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -19,22 +19,6 @@ Who:	Tom Rini <trini@ti.com>
 
 ---------------------------
 
-What:	Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL
-When:	Release v2013.07
-
-Why:	When set these options enable "all" of the pads and clocks found
-	on OMAP4/5 platforms, so that the Linux Kernel does not have to.
-	It has been agreed that this goes against the U-Boot design
-	philosophy and since f3f98bb0 we have not enabled more than is
-	used in U-Boot.  The kernel has been updating drivers to enable
-	rather than assume pads/clocks have been enabled already.  Our
-	expectation is that by v2013.07 a suitable kernel shall exist that
-	does not need these options set for a reasonable I/O set to function.
-
-Who:	Tom Rini <trini@ti.com> and Sricharan R <r.sricharan@ti.com>
-
----------------------------
-
 What:	Users of the legacy miiphy_* code
 When:	undetermined
 
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 7eeb96d..11a0472 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -9,6 +9,11 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
+#define S5P_GPIO_GET_BANK(x)	((x >> S5P_GPIO_BANK_SHIFT) \
+				& S5P_GPIO_BANK_MASK)
+
+#define S5P_GPIO_GET_PIN(x)	(x & S5P_GPIO_PIN_MASK)
+
 #define CON_MASK(x)		(0xf << ((x) << 2))
 #define CON_SFR(x, v)		((v) << ((x) << 2))
 
@@ -124,17 +129,15 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
-	int bank;
-	unsigned g = gpio - s5p_gpio_part_max(gpio);
+	unsigned bank = S5P_GPIO_GET_BANK(gpio);
+	unsigned base = s5p_gpio_base(gpio);
 
-	bank = g / GPIO_PER_BANK;
-	bank *= sizeof(struct s5p_gpio_bank);
-	return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
+	return (struct s5p_gpio_bank *)(base + bank);
 }
 
 int s5p_gpio_get_pin(unsigned gpio)
 {
-	return gpio % GPIO_PER_BANK;
+	return S5P_GPIO_GET_PIN(gpio);
 }
 
 /* Common GPIO API */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index e1817e2..3d1ce12 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -668,6 +668,15 @@ void tegra_mmc_init(void)
 	const void *blob = gd->fdt_blob;
 	debug("%s entry\n", __func__);
 
+	/* See if any Tegra124 MMC controllers are present */
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
+	debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing T30 mmc node(s)!\n", __func__);
+		return;
+	}
+
 	/* See if any Tegra30 MMC controllers are present */
 	count = fdtdec_find_aliases_for_id(blob, "sdhci",
 		COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c
index f264832..94015aa 100644
--- a/drivers/power/battery/bat_trats2.c
+++ b/drivers/power/battery/bat_trats2.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <power/pmic.h>
 #include <power/battery.h>
-#include <power/max8997_pmic.h>
+#include <power/max77693_pmic.h>
 #include <errno.h>
 
 static struct battery battery_trats;
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 89f5d68..98c62b4 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -100,8 +100,8 @@ static int serial_init_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
-	/* enable FIFOs */
-	writel(0x1, &uart->ufcon);
+	/* enable FIFOs, auto clear Rx FIFO */
+	writel(0x3, &uart->ufcon);
 	writel(0, &uart->umcon);
 	/* 8N1 */
 	writel(0x3, &uart->ulcon);
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index 7d4c6e0..00a0a11 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -62,31 +62,6 @@ static void exynos_lcd_init(vidinfo_t *vid)
 	lcd_set_flush_dcache(1);
 }
 
-#ifdef CONFIG_CMD_BMP
-static void draw_logo(void)
-{
-	int x, y;
-	ulong addr;
-
-	if (panel_width >= panel_info.logo_width) {
-		x = ((panel_width - panel_info.logo_width) >> 1);
-	} else {
-		x = 0;
-		printf("Warning: image width is bigger than display width\n");
-	}
-
-	if (panel_height >= panel_info.logo_height) {
-		y = ((panel_height - panel_info.logo_height) >> 1) - 4;
-	} else {
-		y = 0;
-		printf("Warning: image height is bigger than display height\n");
-	}
-
-	addr = panel_info.logo_addr;
-	bmp_display(addr, x, y);
-}
-#endif
-
 void __exynos_cfg_lcd_gpio(void)
 {
 }
@@ -323,9 +298,6 @@ void lcd_enable(void)
 	if (panel_info.logo_on) {
 		memset((void *) gd->fb_base, 0, panel_width * panel_height *
 				(NBITS(panel_info.vl_bpix) >> 3));
-#ifdef CONFIG_CMD_BMP
-		draw_logo();
-#endif
 	}
 
 	lcd_panel_on(&panel_info);
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f962c4f..cebbba7 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -73,18 +73,19 @@ static void exynos_fimd_set_par(unsigned int win_id)
 	/* DATAPATH is DMA */
 	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
 
-	if (pvid->logo_on) /* To get proprietary LOGO */
-		cfg |= EXYNOS_WINCON_WSWP_ENABLE;
-	else /* To get output console on LCD */
-		cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
 
 	/* dma burst is 16 */
 	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
 
-	if (pvid->logo_on) /* To get proprietary LOGO */
-		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-	else /* To get output console on LCD */
+	switch (pvid->vl_bpix) {
+	case 4:
 		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+		break;
+	default:
+		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+		break;
+	}
 
 	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 			EXYNOS_WINCON(win_id));
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index f45deeb..d3c4756 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -34,7 +34,7 @@
 
 /* SPL defines. */
 #define CONFIG_SPL_TEXT_BASE		0x40300350
-#define CONFIG_SPL_MAX_SIZE		(0x40337C00 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_MAX_SIZE		(220 << 10)	/* 220KB */
 #define CONFIG_SPL_YMODEM_SUPPORT
 
 /* Enabling L2 Cache */
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 4abb03e..e80d1a6 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -30,6 +30,10 @@
 #define V_PROMPT		"Tegra30 (Cardhu) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
 
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"board_name=cardhu-a04\0" \
+	"fdtfile=tegra30-cardhu-a04.dtb\0"
+
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
 #define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 3c53f0a..86574c8 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -4,7 +4,7 @@
  * Lokesh Vutla	  <lokeshvutla@ti.com>
  *
  * Configuration settings for the TI DRA7XX board.
- * See omap5_common.h for omap5 common settings.
+ * See ti_omap5_common.h for omap5 common settings.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -34,7 +34,7 @@
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
 
-#include <configs/omap5_common.h>
+#include <configs/ti_omap5_common.h>
 
 /* CPSW Ethernet */
 #define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index a4e0f7c..517f46a 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -141,8 +141,8 @@
  * - 'release': for a standalone system		kernel/rootfs from flash
  */
 #define CONFIG_KM_DEF_ENV_BOOTTARGETS					\
-	"subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel "	\
-		"flashargs add_default addpanic boot\0"			\
+	"subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh "	\
+		"cramfsloadkernel flashargs add_default addpanic boot\0"\
 	"develop="							\
 		"tftp 200000 scripts/develop-${arch}.txt && "		\
 		"env import -t 200000 ${filesize} && "			\
@@ -226,6 +226,7 @@
 	CONFIG_KM_DEF_ENV_FLASH_BOOT					\
 	CONFIG_KM_DEF_ENV_CONSTANTS					\
 	"altbootcmd=run bootcmd\0"					\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
 	"bootcmd=km_checkbidhwk &&  "					\
 		"setenv bootcmd \'if km_checktestboot; then; "          \
 				"setenv boot_bank ${test_bank}; else; " \
@@ -235,6 +236,10 @@
 			"run ${subbootcmds}; reset\' && "		\
 		"saveenv && saveenv && boot\0"				\
 	"bootlimit=3\0"							\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0"		\
 	"init=/sbin/init-overlay.sh\0"					\
 	"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0"		\
 	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index 2cebb2b..763c5ba 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -70,11 +70,6 @@
 #define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
 
 #define CONFIG_KM_DEF_ENV_CPU						\
-	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
-	"cramfsloadfdt="						\
-		"cramfsload ${fdt_addr_r} "				\
-		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
-	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
 	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
 	"update="							\
 		"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
@@ -82,6 +77,7 @@
 		"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START)	\
 		"  ${filesize} && "					\
 		"protect on " __stringify(BOOTFLASH_START) "  +${filesize}\0"\
+	"set_fdthigh=true\0"						\
 	""
 
 #endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index e74f85f..6d77680 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -70,7 +70,8 @@
 #define CONFIG_KM_PHRAM		0x17F000
 
 #define CONFIG_KM_CRAMFS_ADDR	0x2400000
-#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 4096KBytes */
+#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
+#define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */
 
 /* architecture specific default bootargs */
 #define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
@@ -78,15 +79,17 @@
 		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
 
 #define CONFIG_KM_DEF_ENV_CPU						\
-	"boot=bootm ${load_addr_r} - -\0"				\
-	"cramfsloadfdt=true\0"						\
 	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0"		\
 	CONFIG_KM_UPDATE_UBOOT						\
+	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
 	""
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 #define CONFIG_MISC_INIT_R
 
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
 /*
  * NS16550 Configuration
  */
@@ -289,10 +292,15 @@ int get_scl(void);
 		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
 #endif
 
+#ifndef CONFIG_KM_BOARD_EXTRA_ENV
+#define CONFIG_KM_BOARD_EXTRA_ENV       ""
+#endif
+
 /*
  * Default environment variables
  */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_BOARD_EXTRA_ENV					\
 	CONFIG_KM_DEF_ENV						\
 	CONFIG_KM_NEW_ENV						\
 	"arch=arm\0"							\
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index b9e1bac..0d24f78 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -437,6 +437,7 @@ int get_scl(void);
 	"update="							\
 		"sf probe 0;sf erase 0 +${filesize};"			\
 		"sf write ${load_addr_r} 0 ${filesize};\0"		\
+	"set_fdthigh=true\0"						\
 	""
 
 #define CONFIG_HW_ENV_SETTINGS						\
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 74c7232..2cde177 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -45,11 +45,19 @@
 #define CONFIG_KM_DISABLE_PCIE
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 
-/* KM_NUSA */
-#elif defined(CONFIG_KM_NUSA)
+/* KM_NUSA / KM_SUGP1 */
+#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+
+# if defined(CONFIG_KM_NUSA)
 #define CONFIG_IDENT_STRING		"\nKeymile NUSA"
 #define CONFIG_HOSTNAME			kmnusa
+# elif defined(CONFIG_KM_SUGP1)
+#define CONFIG_IDENT_STRING		"\nKeymile SUGP1"
+#define CONFIG_HOSTNAME			kmsugp1
+#define KM_PCIE_RESET_MPP7
+#endif
+
 #undef CONFIG_SYS_KWD_CONFIG
 #define CONFIG_SYS_KWD_CONFIG \
 		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
@@ -97,6 +105,9 @@
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_IDENT_STRING		"\nKeymile SUV31"
 #define CONFIG_HOSTNAME			kmsuv31
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_KM_FPGA_CONFIG
 
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 71062a6..20fbbec 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -10,20 +10,13 @@
 #ifndef __IGEP00X0_H
 #define __IGEP00X0_H
 
-#include <asm/sizes.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_NAND
+#endif
 
-#define CONFIG_SDRC	/* The chip has SDRC controller */
+#define CONFIG_NR_DRAM_BANKS            2
 
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <configs/ti_omap3_common.h>
 #include <asm/mach-types.h>
 
 /*
@@ -32,47 +25,12 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
 #define CONFIG_REVISION_TAG		1
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_SUPPORT_RAW_INITRD
 
-/*
- * NS16550 Configuration
- */
-
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/* select serial console configuration */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
-					115200}
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
 /* define to enable boot progress via leds */
 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
     (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
@@ -95,21 +53,10 @@
 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
 #define CONFIG_USBD_PRODUCT_NAME	"IGEP"
 
-/* commands to include */
-#include <config_cmd_default.h>
-
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_CMD_ONENAND	/* ONENAND support		*/
 #endif
-#ifdef CONFIG_BOOT_NAND
-#define CONFIG_CMD_NAND
-#endif
 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
     (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
 #define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
@@ -117,24 +64,8 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS		/* NFS support			*/
-#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
-#define CONFIG_MTD_DEVICE
-
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
 
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_OMAP34XX
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-
-#define CONFIG_BOOTDELAY		3
+/*#undef CONFIG_ENV_IS_NOWHERE*/
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"usbtty=cdc_acm\0" \
@@ -205,48 +136,6 @@
 	"fi;" \
 	"run nandboot;" \
 
-#define CONFIG_AUTO_COMPLETE		1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"U-Boot # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
-								/* works on */
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
-							/* load address */
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- *
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
 /*
  * FLASH and environment organization
  */
@@ -263,24 +152,16 @@
 #define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
 #endif
 
-#ifdef CONFIG_BOOT_NAND
+#ifdef CONFIG_NAND
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_BASE		NAND_BASE
 #define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 #define CONFIG_ENV_IS_IN_NAND	        1
 #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
 #define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
 #endif
 
 /*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-
-/*
  * SMSC911x Ethernet
  */
 #if defined(CONFIG_CMD_NET)
@@ -289,54 +170,9 @@
 #define CONFIG_SMC911X_BASE	0x2C000000
 #endif /* (CONFIG_CMD_NET) */
 
-/*
- * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- * and older u-boot.bin with the new U-Boot SPL.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80008000
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-/* SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-
-/* move malloc and bss high to prevent clashing with the main image */
-#define CONFIG_SYS_SPL_MALLOC_START	0x87000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
-#define CONFIG_SPL_BSS_START_ADDR	0x87080000	/* end of minimum RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
-/* MMC boot config */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
-
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
-
+/* OneNAND boot config */
 #ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_SPL_ONENAND_SUPPORT
-
-/* OneNAND boot config */
 #define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
 #define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
 #define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
@@ -345,13 +181,8 @@
 
 #endif
 
-#ifdef CONFIG_BOOT_NAND
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-
 /* NAND boot config */
+#ifdef CONFIG_NAND
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
@@ -363,8 +194,6 @@
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #endif
 
 #endif /* __IGEP00X0_H */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 73dc088..7378acd 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -4,7 +4,7 @@
  * Steve Sakoman  <steve@sakoman.com>
  *
  * Configuration settings for the TI OMAP4 Panda board.
- * See omap4_common.h for OMAP4 common part
+ * See ti_omap4_common.h for OMAP4 common part
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -36,7 +36,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 
-#include <configs/omap4_common.h>
+#include <configs/ti_omap4_common.h>
 #define CONFIG_CMD_NET
 
 /* GPIO */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index b352511..a837974 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -5,7 +5,7 @@
  * Steve Sakoman  <steve@sakoman.com>
  *
  * Configuration settings for the TI SDP4430 board.
- * See omap4_common.h for OMAP4 common part
+ * See ti_omap4_common.h for OMAP4 common part
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -19,7 +19,7 @@
 #define CONFIG_4430SDP		1	/* working with SDP */
 #define CONFIG_MACH_TYPE	MACH_TYPE_OMAP_4430SDP
 
-#include <configs/omap4_common.h>
+#include <configs/ti_omap4_common.h>
 
 /* Battery Charger */
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 3df502e..783b7c3 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -4,7 +4,7 @@
  * Sricharan R	  <r.sricharan@ti.com>
  *
  * Configuration settings for the TI EVM5430 board.
- * See omap5_common.h for omap5 common settings.
+ * See ti_omap5_common.h for omap5 common settings.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -17,7 +17,7 @@
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
 
-#include <configs/omap5_common.h>
+#include <configs/ti_omap5_common.h>
 
 #define CONFIG_CONS_INDEX		3
 #define CONFIG_SYS_NS16550_COM3		UART3_BASE
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index 0b7add7..976ceaa 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -123,6 +123,7 @@
 	"scriptaddr=0x00000000\0" \
 	"kernel_addr_r=0x01000000\0" \
 	"fdt_addr_r=0x02000000\0" \
+	"fdtfile=bcm2835-rpi-b.dtb\0" \
 	"ramdisk_addr_r=0x02100000\0" \
 	"boot_targets=mmc0\0" \
 	\
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 0590d20..991c43e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -34,6 +34,7 @@
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
 
@@ -113,8 +114,13 @@
 
 #define CONFIG_UBIFS_OPTION	"rootflags=bulk_read,no_chk_data_crc"
 
+#define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_UPDATEB \
 	"updatek=" \
@@ -208,8 +214,8 @@
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3)
-#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
+#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index d9e4c56..67921e9 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -124,6 +124,9 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"updateb=" \
 		"onenand erase 0x0 0x100000;" \
@@ -229,8 +232,8 @@
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
@@ -253,10 +256,10 @@
  */
 #define CONFIG_SOFT_SPI
 #define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
-#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
-#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
-#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
+#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
+#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
+#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
+#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
 
 #define SPI_DELAY udelay(1)
 #undef SPI_INIT
@@ -269,16 +272,43 @@ void universal_spi_sda(int bit);
 int universal_spi_read(void);
 #endif
 
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8998_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX8998_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8998_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 7)
+#define KEY_PWR_INTERRUPT_REG		MAX8998_REG_IRQ1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 7)
+
+#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 /*
  * LCD Settings
  */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
 #define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
 #define CONFIG_LD9040
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index a3242fe..e1a3bbc 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -99,6 +99,7 @@
 	BOOTCMDS_DHCP
 
 #define CONFIG_BOOTCOMMAND \
+	"set usb_need_init; " \
 	"for target in ${boot_targets}; do run bootcmd_${target}; done"
 
 #endif
@@ -129,10 +130,15 @@
 	"stderr=serial" STDOUT_LCD "\0" \
 	""
 
+#ifndef BOARD_EXTRA_ENV_SETTINGS
+#define BOARD_EXTRA_ENV_SETTINGS
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	TEGRA_DEVICE_SETTINGS \
 	MEM_LAYOUT_ENV_SETTINGS \
-	BOOTCMDS_COMMON
+	BOOTCMDS_COMMON \
+	BOARD_EXTRA_ENV_SETTINGS
 
 #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
 #define CONFIG_FDT_SPI
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
new file mode 100644
index 0000000..0a4541b
--- /dev/null
+++ b/include/configs/tegra124-common.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_COMMON_H_
+#define _TEGRA124_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA124			/* is an NVIDIA Tegra124 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* Total I2C ports on Tegra124 */
+#define TEGRA_I2C_NUM_CONTROLLERS	5
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+
+#endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 4364eef..91f97dd 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -73,6 +73,10 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
 /* Now bring in the rest of the common code. */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 99b60fc..69d69a5 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -45,11 +45,15 @@
 #define CONFIG_BOOTDELAY		1
 
 /*
- * DDR information.  We say (for simplicity) that we have 1 bank,
- * always, even when we have more.  We always start at 0x80000000,
- * and we place the initial stack pointer in our SRAM.
+ * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
+ * we say (for simplicity) that we have 1 bank, always, even when
+ * we have more.  We always start at 0x80000000, and we place the
+ * initial stack pointer in our SRAM. Otherwise, we can define
+ * CONFIG_NR_DRAM_BANKS before including this file.
  */
+#ifndef CONFIG_NR_DRAM_BANKS
 #define CONFIG_NR_DRAM_BANKS		1
+#endif
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
 						GENERATED_GBL_DATA_SIZE)
@@ -237,7 +241,6 @@
 #define CONFIG_SPL_BOARD_INIT
 
 #ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_AM33XX_BCH	/* OMAP4 and later ELM support */
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
new file mode 100644
index 0000000..854cb78
--- /dev/null
+++ b/include/configs/ti_omap3_common.h
@@ -0,0 +1,73 @@
+/*
+ * ti_omap3_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the technical documents listed at
+ *   http://www.ti.com/product/omap3530
+ *   http://www.ti.com/product/omap3630
+ *   http://www.ti.com/product/dm3730
+ */
+
+#ifndef __CONFIG_TI_OMAP3_COMMON_H__
+#define __CONFIG_TI_OMAP3_COMMON_H__
+
+#define CONFIG_OMAP34XX
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* The chip has SDRC controller */
+#define CONFIG_SDRC
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+/* NS16550 Configuration */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+
+/* Select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER		1
+
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_POWER_SUPPORT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
+
+#endif	/* __CONFIG_TI_OMAP3_COMMON_H__ */
diff --git a/include/configs/omap4_common.h b/include/configs/ti_omap4_common.h
index d099bfd..2f0e4c0 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -9,8 +9,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_OMAP4_COMMON_H
-#define __CONFIG_OMAP4_COMMON_H
+#ifndef __CONFIG_TI_OMAP4_COMMON_H
+#define __CONFIG_TI_OMAP4_COMMON_H
 
 /*
  * High Level Configuration Options
@@ -159,4 +159,8 @@
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 
-#endif /* __CONFIG_OMAP4_COMMON_H */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+#endif /* __CONFIG_TI_OMAP4_COMMON_H */
diff --git a/include/configs/omap5_common.h b/include/configs/ti_omap5_common.h
index c7fa37e..7b10fbd 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -14,8 +14,8 @@
  * http://www.ti.com/product/omap5432
  */
 
-#ifndef __CONFIG_OMAP5_COMMON_H
-#define __CONFIG_OMAP5_COMMON_H
+#ifndef __CONFIG_TI_OMAP5_COMMON_H
+#define __CONFIG_TI_OMAP5_COMMON_H
 
 #define CONFIG_OMAP54XX
 #define CONFIG_DISPLAY_CPUINFO
@@ -146,4 +146,8 @@
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 
-#endif /* __CONFIG_OMAP5_COMMON_H */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+#endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index fdd8b46..718107a 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -147,15 +147,23 @@
 	""PARTS_BOOT" part 0 2;" \
 	""PARTS_ROOT" part 0 5;" \
 	""PARTS_DATA" part 0 6;" \
-	""PARTS_UMS" part 0 7\0"
+	""PARTS_UMS" part 0 7;" \
+	"params.bin mmc 0x38 0x8\0"
 
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
 	"updatemmc=" \
 		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
 		"mmc boot 0 1 1 0\0" \
@@ -178,7 +186,7 @@
 	"mmcboot=" \
 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run bootk\0" \
 	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
 	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
@@ -217,7 +225,6 @@
 		   "setenv spl_imgaddr;" \
 		   "setenv spl_addr_tmp;\0" \
 	"fdtaddr=40800000\0" \
-	"fdtfile=exynos4210-trats.dtb\0"
 
 
 /* Miscellaneous configurable options */
@@ -287,8 +294,8 @@
 #include <asm/arch/gpio.h>
 
 /* I2C FG */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
 
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
@@ -306,16 +313,43 @@
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_CABLE_CHECK
 
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8997_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 0)
+
+#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 /* LCD */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
 #define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_GADGET_MASS_STORAGE
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 83633b0..e30c428 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -152,6 +152,9 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 /* Tizen - partitions definitions */
 #define PARTS_CSA		"csa"
 #define PARTS_BOOT		"boot"
@@ -178,11 +181,16 @@
 	""PARTS_BOOT" part 0 2;" \
 	""PARTS_ROOT" part 0 5;" \
 	""PARTS_DATA" part 0 6;" \
-	""PARTS_UMS" part 0 7\0"
+	""PARTS_UMS" part 0 7;" \
+	"params.bin mmc 0x38 0x8\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
 	"updatemmc=" \
 		"mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
 		"mmc boot 0 1 1 0\0" \
@@ -196,7 +204,7 @@
 	"mmcboot=" \
 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run bootk\0" \
 	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
 	"verify=n\0" \
@@ -237,7 +245,6 @@
 		   "setenv spl_imgaddr;" \
 		   "setenv spl_addr_tmp;\0" \
 	"fdtaddr=40800000\0" \
-	"fdtfile=exynos4412-trats2.dtb\0"
 
 /*
  * Miscellaneous configurable options
@@ -277,7 +284,6 @@
 #define CONFIG_EFI_PARTITION
 #define CONFIG_PARTITION_UUIDS
 
-#define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* I2C */
@@ -318,16 +324,43 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_CABLE_CHECK
 
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max77686_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX77686_PMIC"
+#define KEY_PWR_STATUS_REG		MAX77686_REG_PMIC_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 1)
+
+#define KEY_VOL_UP_GPIO			exynos4x12_gpio_get(2, x2, 2)
+#define KEY_VOL_DOWN_GPIO		exynos4x12_gpio_get(2, x3, 3)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP                 LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 /* LCD */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
 #define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_GADGET_MASS_STORAGE
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
new file mode 100644
index 0000000..91808e9
--- /dev/null
+++ b/include/configs/venice2.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-venice2
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra124 (Venice2) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Venice2"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI		/* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS	6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 10738ac..29c32fe 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -101,7 +101,8 @@
 
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS		"root=/dev/nfs mem=128M ip=dhcp "\
-				"netdev=25,0,0xf1010000,0xf1010010,eth0"
+				"netdev=25,0,0xf1010000,0xf1010010,eth0 "\
+				"console=ttyAMA0,38400n1"
 
 /*
  * Static configuration when assigning fixed address
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e7a8e9f..9b6db04 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -164,7 +164,7 @@
 		"fatload mmc 0 ${load_addr} ${fit_image} && " \
 		"bootm ${load_addr}\0" \
 	"jtagboot=echo TFTPing FIT to RAM... && " \
-		"tftp ${load_addr} ${fit_image} && " \
+		"tftpboot ${load_addr} ${fit_image} && " \
 		"bootm ${load_addr}\0"
 #define CONFIG_BOOTCOMMAND		"run $modeboot"
 #define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
@@ -228,6 +228,8 @@
 # define CONFIG_SYS_MMC_MAX_DEVICE	1
 #endif
 
+#define CONFIG_SYS_LDSCRIPT  "arch/arm/cpu/armv7/zynq/u-boot.lds"
+
 /* Commands */
 #include <config_cmd_default.h>
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 433d6a7..19bab79 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -59,6 +59,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra20 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
diff --git a/include/lcd.h b/include/lcd.h
index 40e8d2a..d06d6f1 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -223,6 +223,8 @@ typedef struct vidinfo {
 	unsigned int logo_on;
 	unsigned int logo_width;
 	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
 	unsigned long logo_addr;
 	unsigned int rgb_mode;
 	unsigned int resolution;
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index 16e9016..c2a772a 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -8,6 +8,8 @@
 #ifndef __MAX77686_H_
 #define __MAX77686_H_
 
+#include <power/pmic.h>
+
 enum {
 	MAX77686_REG_PMIC_ID		= 0x0,
 	MAX77686_REG_PMIC_INTSRC,
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 0e7aa31..8f282dd 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -8,7 +8,6 @@
 #ifndef __CORE_PMIC_H_
 #define __CORE_PMIC_H_
 
-#include <common.h>
 #include <linux/list.h>
 #include <i2c.h>
 #include <power/power_chrg.h>
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
new file mode 100644
index 0000000..ede6c15
--- /dev/null
+++ b/include/samsung/misc.h
@@ -0,0 +1,29 @@
+#ifndef __SAMSUNG_MISC_COMMON_H__
+#define __SAMSUNG_MISC_COMMON_H__
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void);
+#endif
+
+#ifdef CONFIG_LCD_MENU
+enum {
+	BOOT_MODE_INFO,
+	BOOT_MODE_THOR,
+	BOOT_MODE_UMS,
+	BOOT_MODE_DFU,
+	BOOT_MODE_EXIT,
+};
+
+void keys_init(void);
+void check_boot_mode(void);
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void);
+#endif
+
+#endif /* __SAMSUNG_MISC_COMMON_H__ */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 207314f..1fecab3 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -32,6 +32,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
 	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
 	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c
index e872591..814ed18 100644
--- a/lib/tizen/tizen.c
+++ b/lib/tizen/tizen.c
@@ -9,18 +9,25 @@
 #include <lcd.h>
 #include <libtizen.h>
 
-#include "tizen_hd_logo.h"
-#include "tizen_hd_logo_data.h"
+#include "tizen_logo_16bpp.h"
+#include "tizen_logo_16bpp_gzip.h"
 
 void get_tizen_logo_info(vidinfo_t *vid)
 {
-	switch (vid->resolution) {
-	case HD_RESOLUTION:
-		vid->logo_width = TIZEN_HD_LOGO_WIDTH;
-		vid->logo_height = TIZEN_HD_LOGO_HEIGHT;
-		vid->logo_addr = (ulong)tizen_hd_logo;
+	switch (vid->vl_bpix) {
+	case 4:
+		vid->logo_width = TIZEN_LOGO_16BPP_WIDTH;
+		vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT;
+		vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET;
+		vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET;
+#if defined(CONFIG_VIDEO_BMP_GZIP)
+		vid->logo_addr = (ulong)tizen_logo_16bpp_gzip;
+#else
+		vid->logo_addr = (ulong)tizen_logo_16bpp;
+#endif
 		break;
 	default:
+		vid->logo_addr = 0;
 		break;
 	}
 }
diff --git a/lib/tizen/tizen_hd_logo.h b/lib/tizen/tizen_hd_logo.h
deleted file mode 100644
index 28377b7..0000000
--- a/lib/tizen/tizen_hd_logo.h
+++ /dev/null
@@ -1,5057 +0,0 @@
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _TIZEN_HD_LOGO_H_
-#define _TIZEN_HD_LOGO_H_
-
-unsigned char tizen_hd_logo[]={
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-0xd2,0xdd,0x64,0x9e,0x98,0xeb,0xd6,0x85,0x7c,0xcd,0x14,0x38,0xfd,0x43,0x71,0x78,
-0x25,0xf8,0x96,0x01,0x8d,0xe8,0x8c,0x0a,0x3c,0x26,0xde,0xab,0x28,0x5e,0x3f,0x6c,
-0xdd,0xbc,0x57,0xdf,0x3e,0xc1,0x43,0xc2,0xe3,0xe4,0xc2,0x61,0x15,0xf9,0xf1,0x5f,
-0x69,0xd7,0x24,0x79,0xb6,0xa9,0x03,0x00,0x00
-};
-
-#endif	/* _TIZEN_HD_LOGO_H_ */
diff --git a/lib/tizen/tizen_hd_logo_data.h b/lib/tizen/tizen_hd_logo_data.h
deleted file mode 100644
index 95e5f82..0000000
--- a/lib/tizen/tizen_hd_logo_data.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _TIZEN_HD_LOGO_DATA_H_
-#define _TIZEN_HD_LOGO_DATA_H_
-
-#define TIZEN_HD_LOGO_WIDTH		520
-#define	TIZEN_HD_LOGO_HEIGHT		120
-#define	TIZEN_HD_LOGO_BPP		32
-
-#endif	/* _TIZEN_HD_LOGO_DATA_H_ */
diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h
new file mode 100644
index 0000000..9a0b6fa
--- /dev/null
+++ b/lib/tizen/tizen_logo_16bpp.h
@@ -0,0 +1,10025 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __TIZEN_LOGO_16BPP__
+#define __TIZEN_LOGO_16BPP__
+
+#define TIZEN_LOGO_16BPP_WIDTH		500
+#define TIZEN_LOGO_16BPP_HEIGHT		160
+
+/* Center align offsets for word "TIZEN" */
+#define TIZEN_LOGO_16BPP_X_OFFSET	(30)
+#define TIZEN_LOGO_16BPP_Y_OFFSET	(-26)
+
+/* Format: BMP RGB565 16BPP 500x160 */
+unsigned char tizen_logo_16bpp[] = {
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+0x00,0x00,0x00,0x00,0x00,0x00};
+#endif
diff --git a/lib/tizen/tizen_logo_16bpp_gzip.h b/lib/tizen/tizen_logo_16bpp_gzip.h
new file mode 100644
index 0000000..a8af646
--- /dev/null
+++ b/lib/tizen/tizen_logo_16bpp_gzip.h
@@ -0,0 +1,727 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __TIZEN_LOGO_16BPP_GZIP__
+#define __TIZEN_LOGO_16BPP_GZIP__
+
+/* Format: GZIP: BMP RGB565 16BPP 500x160 */
+unsigned char tizen_logo_16bpp_gzip[] = {
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+0x1b,0x4a,0xc3,0x5f,0x09,0x6e,0x4e,0xc8,0x28,0x87,0x5d,0xac,0xef,0x52,0xce,0xa9,
+0xa8,0x36,0x98,0x66,0xbe,0x34,0xfe,0xe5,0x1d,0x0e,0x36,0x73,0x26,0x05,0x4e,0x93,
+0x3f,0x4b,0x39,0xa7,0xa2,0xda,0x58,0x72,0xfe,0xd3,0x17,0xdf,0xb6,0xed,0x71,0xec,
+0x70,0x48,0x27,0x4c,0x29,0xe7,0x54,0x54,0x1b,0x51,0xf7,0x2c,0x3f,0xb5,0xee,0x40,
+0x3d,0xf9,0x1e,0xc4,0xf9,0x7b,0x8e,0xcf,0x04,0xce,0x69,0x6c,0x47,0x2a,0xaa,0x8d,
+0x26,0xaf,0x25,0x54,0x7f,0xd1,0x9e,0x10,0x22,0xc3,0x34,0x39,0x28,0xe7,0x54,0x54,
+0x1b,0x55,0x7f,0x59,0x77,0xc7,0x96,0x70,0xbc,0xf0,0xd0,0xf3,0x8e,0x17,0x29,0xe7,
+0x54,0x54,0x1b,0x56,0xdf,0xb7,0xfc,0xc4,0xfa,0x9e,0x63,0xb7,0x83,0x8e,0xcf,0xa9,
+0xa8,0x36,0xb6,0x42,0xf5,0x3f,0xb1,0xde,0x30,0x9c,0x88,0xff,0x0f,0xa8,0x0b,0x24,
+0x15,0x46,0x71,0x02,0x00};
+#endif
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
index 93b4c39..670b9fd 100644
--- a/tools/relocate-rela.c
+++ b/tools/relocate-rela.c
@@ -120,7 +120,7 @@ int main(int argc, char **argv)
 	}
 
 	if (rela_start > rela_end || rela_start < text_base ||
-	    (rela_end - rela_start) % 24) {
+	    (rela_end - rela_start) % sizeof(Elf64_Rela)) {
 		fprintf(stderr, "%s: bad rela bounds\n", argv[0]);
 		return 3;
 	}