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authorPiotr Wilczek <p.wilczek@samsung.com>2012-09-20 00:19:55 +0000
committerMinkyu Kang <mk7.kang@samsung.com>2012-11-15 21:08:18 +0900
commitb5598578f5260a2703012154d0388eaff10c965a (patch)
treefedd91b88dac4711e163823c3b300326958bd931
parent061562c423aa5929231b0d2039699bcb2b74079a (diff)
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arm:exynos4:trats: Correct SDRAM configuration for trats
SDRAM setup alike to ORIGEN Dev board. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
-rw-r--r--include/configs/trats.h17
1 files changed, 11 insertions, 6 deletions
diff --git a/include/configs/trats.h b/include/configs/trats.h
index d7808aa..a24e945 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -189,12 +189,17 @@
#define CONFIG_SYS_HZ 1000
-/* TRATS has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */