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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2012-03-05 20:11:12 +0000
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2012-03-26 10:09:30 +0900
commit566f63d5cfdf5e706a5f1304a475d35e71cd6065 (patch)
tree299fe570f3aa0bd4d5cc622b39dafae1636d0942
parent7cb30b13f12077c7eec8ce2419cd96cd65ace8e2 (diff)
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sh: sh7757lcr: add supporting for MMCIF
The sh7757lcr has 2GByte eMMC chip. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-rw-r--r--board/renesas/sh7757lcr/sh7757lcr.c5
-rw-r--r--doc/README.sh7757lcr1
-rw-r--r--include/configs/sh7757lcr.h11
3 files changed, 17 insertions, 0 deletions
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
index a62be24..adae9ce 100644
--- a/board/renesas/sh7757lcr/sh7757lcr.c
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -263,6 +263,11 @@ int dram_init(void)
return 0;
}
+int board_mmc_init(bd_t *bis)
+{
+ return mmcif_mmc_init();
+}
+
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
struct spi_flash *spi;
diff --git a/doc/README.sh7757lcr b/doc/README.sh7757lcr
index 37c1a7a..3e9c1c1 100644
--- a/doc/README.sh7757lcr
+++ b/doc/README.sh7757lcr
@@ -12,6 +12,7 @@ The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
- SPI ROM 8MB
- 2D Graphic controller
- Ethernet controller
+ - eMMC 2GB
configuration for This board:
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index c1f9ce8..73d2a87 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -49,6 +49,10 @@
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
@@ -123,6 +127,13 @@
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
+/* MMCIF */
+#define CONFIG_MMC 1
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_SH_MMCIF 1
+#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
+#define CONFIG_SH_MMCIF_CLK 48000000
+
/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
#define SH7757LCR_GRA_OFFSET 0x1f000000