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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-05-22 03:57:46 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-24 09:51:03 -0400 |
| commit | 843a76b66be70a28a55f295fa72faa74dde9e02b (patch) | |
| tree | fb1224f566335c6e5e07b2271589edeae1ff0840 | |
| parent | a79b5e684822e16298f46dd6fa5bbcdaec01af46 (diff) | |
| download | u-boot-imx-843a76b66be70a28a55f295fa72faa74dde9e02b.zip u-boot-imx-843a76b66be70a28a55f295fa72faa74dde9e02b.tar.gz u-boot-imx-843a76b66be70a28a55f295fa72faa74dde9e02b.tar.bz2 | |
MIPS: start.S: emulate REVISION register for qemu-malta
On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.
This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index b08a897..2f1e486 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -41,7 +41,7 @@ _start: nop .org 0x10 -#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG +#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) /* * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to * access external NOR flashes. If the board boots from NOR flash the @@ -51,6 +51,12 @@ _start: */ .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 +#elif defined(CONFIG_QEMU_MALTA) + /* + * Linux expects the Board ID here. + */ + .word 0x00000420 # 0x420 (Malta Board with CoreLV) + .word 0x00000000 #endif .org 0x200 |