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| author | Wolfgang Denk <wd@denx.de> | 2011-10-04 22:08:13 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-04 22:08:13 +0200 |
| commit | 1fed668b3fb9c35932f58af00ff5539239fa4e1d (patch) | |
| tree | eaaaead8ca19924af1823caae040f504be9b6d98 | |
| parent | c52575350fd6e794717f6bee4f81dbb8038fe22e (diff) | |
| parent | 6d7b061af153bc5beb633c3bd15348284716a067 (diff) | |
| download | u-boot-imx-1fed668b3fb9c35932f58af00ff5539239fa4e1d.zip u-boot-imx-1fed668b3fb9c35932f58af00ff5539239fa4e1d.tar.gz u-boot-imx-1fed668b3fb9c35932f58af00ff5539239fa4e1d.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p3060: Add SoC related support for P3060 platform
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
powerpc/85xx: Refactor some defines out of corenet_ds.h
fm-eth: Add ability for board code to disable a port
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
powerpc/mpc85xxcds: Fix PCI speed
powerpc/mpc8548cds: Fix booting message
powerpc/p4080: Add support for secure boot flow
powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
powerpc/p2041rdb: remove watch dog related codes
powerpc/p2041rdb: updated description of cpld command
powerpc/p2041rdb: add more ddr frequencies support
powerpc/p2041rdb: set sysclk according to status of physical switch SW1
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
powerpc/mpc8xxx: Add DDR2 to unified DDR driver
powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
powerpc/85xx: Enable CMD_REGINFO on corenet boards
powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
powerpc/85xx: Fix USB protocol definitions for P1020RDB
powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
powerpc/mpc8xxx: Move DDR RCW overriding to common code
powerpc/mpc8xxx: Extend CWL table
powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
powerpc/85xx: Cleanup extern in corenet_ds board code
powerpc/p2041rdb: Add ethernet support on P2041RDB board
powerpc/85xx: Add networking support to P1023RDS
powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
powerpc/85xx: Add FMan ethernet support to P4080DS
powerpc/85xx: Add support for FMan ethernet in Independent mode
powerpc/mpc8548cds: Cleanup mpc8548cds.c
powerpc/mp: add support for discontiguous cores
powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
fdt: Add new fdt_create_phandle helper
fdt: Rename fdt_create_phandle to fdt_set_phandle
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
nand: Freescale Integrated Flash Controller NAND support
powerpc/85xx: Add basic support for P1010RDB
powerpc/85xx: Add support for new P102x/P2020 RDB style boards
powerpc/85xx: relocate CCSR before creating the initial RAM area
powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
147 files changed, 12055 insertions, 737 deletions
@@ -253,10 +253,12 @@ LIBS += drivers/power/libpower.o LIBS += drivers/spi/libspi.o ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/libqe.o +LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/libqe.o +LIBS += drivers/net/fm/libfm.o LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o endif @@ -2862,6 +2862,43 @@ Low Level (hardware related) configuration options: and RPXsuper) to be able to adjust the position of the IMMR register after a reset. +- CONFIG_SYS_CCSRBAR_DEFAULT: + Default (power-on reset) physical address of CCSR on Freescale + PowerPC SOCs. + +- CONFIG_SYS_CCSRBAR: + Virtual address of CCSR. On a 32-bit build, this is typically + the same value as CONFIG_SYS_CCSRBAR_DEFAULT. + + CONFIG_SYS_DEFAULT_IMMR must also be set to this value, + for cross-platform code that uses that macro instead. + +- CONFIG_SYS_CCSRBAR_PHYS: + Physical address of CCSR. CCSR can be relocated to a new + physical address, if desired. In this case, this macro should + be set to that address. Otherwise, it should be set to the + same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR + is typically relocated on 36-bit builds. It is recommended + that this macro be defined via the _HIGH and _LOW macros: + + #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + +- CONFIG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically + either 0 (32-bit build) or 0xF (36-bit build). This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is + used in assembly code, so it must not contain typecasts or + integer size suffixes (e.g. "ULL"). + +- CONFIG_SYS_CCSR_DO_NOT_RELOCATE: + If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be + forced to a value that ensures that CCSR is not relocated. + - Floppy Disk Support: CONFIG_SYS_FDC_DRIVE_NUMBER diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 3979b6f..b353036 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -34,7 +34,6 @@ COBJS-y += cpu.o COBJS-y += cpu_init.o COBJS-y += speed.o COBJS-y += interrupts.o -COBJS-y += spd_sdram.o COBJS-y += ecc.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_FSL_SERDES) += serdes.o @@ -42,6 +41,13 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_PCIE) += pcie.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +ifdef CONFIG_FSL_DDR2 +COBJS-$(CONFIG_MPC8349) += ddr-gen2.o +else +COBJS-y += spd_sdram.o +endif +COBJS-$(CONFIG_FSL_DDR2) += law.o + COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -52,6 +58,18 @@ all: $(obj).depend $(START) $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(obj)ddr-gen1.c: + @rm -f $(obj)ddr-gen1.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c + +$(obj)ddr-gen2.c: + @rm -f $(obj)ddr-gen2.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c + +$(obj)ddr-gen3.c: + @rm -f $(obj)ddr-gen3.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c + ######################################################################### # defines $(obj).depend target diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index f8eab96..717365c 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * based on the contribution of Marian Balakowicz <m8@semihalf.com> @@ -20,8 +20,12 @@ #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) void ecc_print_status(void) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_FSL_DDR2 + ccsr_ddr_t *ddr = &immap->ddr; +#else + ddr83xx_t *ddr = &immap->ddr; +#endif printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); @@ -100,8 +104,12 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_FSL_DDR2 + ccsr_ddr_t *ddr = &immap->ddr; +#else + ddr83xx_t *ddr = &immap->ddr; +#endif volatile u32 val; u64 *addr; u32 count; diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c new file mode 100644 index 0000000..66c88b6 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -0,0 +1,61 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) +{ + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; + u64 start_align, law_sz; + int law_sz_enc; + + if (start == 0) + start_align = 1ull << (LAW_SIZE_2G + 1); + else + start_align = 1ull << (ffs64(start) - 1); + law_sz = min(start_align, sz); + law_sz_enc = __ilog2_u64(law_sz) - 1; + + /* + * Set up LAWBAR for all of DDR. + */ + ecm->bar = start & 0xfffff000; + ecm->ar = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc)); + debug("DDR:bar=0x%08x\n", ecm->bar); + debug("DDR:ar=0x%08x\n", ecm->ar); + + /* recalculate size based on what was actually covered by the law */ + law_sz = 1ull << __ilog2_u64(law_sz); + + /* do we still have anything to map */ + sz = sz - law_sz; + if (sz) { + start += law_sz; + + start_align = 1ull << (ffs64(start) - 1); + law_sz = min(start_align, sz); + law_sz_enc = __ilog2_u64(law_sz) - 1; + ecm = &immap->sysconf.ddrlaw[1]; + ecm->bar = start & 0xfffff000; + ecm->ar = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc)); + debug("DDR:bar=0x%08x\n", ecm->bar); + debug("DDR:ar=0x%08x\n", ecm->ar); + } else { + return 0; + } + + /* do we still have anything to map */ + sz = sz - law_sz; + if (sz) + return 1; + + return 0; +} diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 4542ab1..f78099d 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -507,6 +507,15 @@ ulong get_bus_freq(ulong dummy) return gd->csb_clk; } +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq(ulong dummy) +{ + return gd->mem_clk; +} + int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { char buf[32]; diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 7026bca..058d609 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -67,6 +67,7 @@ COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o @@ -81,6 +82,7 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o +COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -114,6 +116,7 @@ COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o +COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 7b9f773..a09eb91 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -87,6 +87,22 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum DDR111 enabled\n"); puts("Work-around for Erratum DDR134 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 + puts("Work-around for Erratum IFC-A002769 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 + puts("Work-around for Erratum P1010-A003549 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 + puts("Work-around for Erratum IFC A-003399 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG DDR120 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 + puts("Work-around for Erratum NMG_LBC103 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 22fa461..49c0551 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -64,13 +64,11 @@ int checkcpu (void) u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ - int i; + unsigned int i, core, nr_cores = cpu_numcores(); + u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); -#ifdef CONFIG_MPC8536 - major &= 0x7; /* the msb of this nibble is a mfg code */ -#endif minor = SVR_MIN(svr); if (cpu_numcores() > 1) { @@ -119,11 +117,11 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:"); - for (i = 0; i < cpu_numcores(); i++) { + for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); - printf("CPU%d:%-4s MHz, ", - i,strmhz(buf1, sysinfo.freqProcessor[i])); + printf("CPU%d:%-4s MHz, ", core, + strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6aca166..0a4ce53 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -31,6 +31,7 @@ #include <asm/processor.h> #include <ioports.h> #include <sata.h> +#include <fm_eth.h> #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> @@ -225,7 +226,9 @@ void cpu_init_f (void) #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif - +#if defined(CONFIG_SECURE_BOOT) + struct law_entry law; +#endif #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -243,6 +246,13 @@ void cpu_init_f (void) disable_tlb(14); disable_tlb(15); +#if defined(CONFIG_SECURE_BOOT) + /* Disable the LAW created for NOR flash by the PBI commands */ + law = find_law(CONFIG_SYS_PBI_FLASH_BASE); + if (law.index != -1) + disable_law(law.index); +#endif + #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); #endif @@ -453,6 +463,9 @@ skip_l2: clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); __raw_readl(&lbc->lcrr); isync(); +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 + udelay(100); +#endif #endif #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE @@ -472,6 +485,10 @@ skip_l2: } #endif +#ifdef CONFIG_FMAN_ENET + fman_enet_init(); +#endif + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 32aa94b..4ef3c9a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc + * Copyright 2009-2011 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,59 +21,59 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) -#ifdef CONFIG_FSL_CORENET -static void setup_ccsrbar(void) +#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) +void setup_ifc(void) { - u32 temp; - volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - volatile ccsr_local_t *ccm; + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 _mas0, _mas1, _mas2, _mas3, _mas7; + phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; /* - * We can't call set_law() because we haven't moved - * CCSR yet. + * Adjust the TLB we were running out of to match the phys addr of the + * chip select we are adjusting and will return to. */ - ccm = (void *)ccsr_virt; - - out_be32(&ccm->law[0].lawbarh, - (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); - out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); - out_be32(&ccm->law[0].lawar, - LAW_EN | (0x1e << 20) | LAW_SIZE_4K); - - in_be32((u32 *)(ccsr_virt + 0)); - in_be32((u32 *)(ccsr_virt + 1)); - isync(); - - ccm = (void *)CONFIG_SYS_CCSRBAR; - /* Now use the temporary LAW to move CCSR */ - out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); - out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); - out_be32(&ccm->ccsrar, CCSRAR_C); - temp = in_be32(&ccm->ccsrar); - disable_law(0); -} -#else -static void setup_ccsrbar(void) -{ - u32 temp; - volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; + + _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); + asm volatile("isync;msync;tlbwe;isync"); + + out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); + out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); + out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + + return ; } #endif -#endif /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { u32 mas0, mas1, mas2, mas3, mas7; int i; +#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + u32 *l2srbar, *dst, *src; + void (*setup_ifc_sram)(void); +#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -85,28 +85,77 @@ void cpu_init_early_f(void) for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0); - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K); + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); write_tlb(mas0, mas1, mas2, mas3, mas7); - /* set up CCSR if we want it moved */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); +/* + * Work Around for IFC Erratum A-003549. This issue is P1010 + * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC + * Hence specifically selecting CS3. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); +#endif + + init_laws(); + +/* + * Work Around for IFC Erratum A003399, issue will hit only when execution + * from NOR Flash + */ +#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) +#define SRAM_BASE_ADDR (0x00000000) + /* TLB for SRAM */ + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | + MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); + mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(0); write_tlb(mas0, mas1, mas2, mas3, mas7); - setup_ccsrbar(); + out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); + + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* + * Copy the code in setup_ifc to L2SRAM. Do a word copy + * because NOR Flash on P1010 does not support byte + * access (Erratum IFC-A002769) + */ + setup_ifc_sram = (void *)SRAM_BASE_ADDR; + dst = (u32 *) SRAM_BASE_ADDR; + src = (u32 *) setup_ifc; + for (i = 0; i < 1024; i++) + *l2srbar++ = *src++; + + setup_ifc_sram(); + + /* CLEANUP */ + clrbits_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + out_be32(&l2cache->l2srbar0, 0x0); +#endif + + invalidate_tlb(1); + +#if defined(CONFIG_SECURE_BOOT) + /* Disable the TLBs created by ISBC */ + for (i = CONFIG_SYS_ISBC_START_TLB; + i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++) + disable_tlb(i); #endif - init_laws(); - invalidate_tlb(0); init_tlbs(); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 796d398..f33db02 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -21,10 +21,12 @@ */ #include <common.h> +#include <asm/fsl_ifc.h> #include <asm/io.h> void cpu_init_f(void) { +#ifdef CONFIG_FSL_LBC fsl_lbc_t *lbc = LBC_BASE_ADDR; /* @@ -39,6 +41,16 @@ void cpu_init_f(void) #else #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined #endif +#endif +#ifdef CONFIG_FSL_IFC +#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); +#endif +#endif +#endif #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c index 655f99c..49000a1 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -8,6 +8,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/processor.h> #include <asm/fsl_ddr_sdram.h> #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) @@ -18,13 +19,36 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; +#ifdef CONFIG_MPC83xx + ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR; +#else + ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint svr; +#endif +#endif if (ctrl_num) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); return; } +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + /* + * Set the DDR IO receiver to an acceptable bias point. + * Fixed in Rev 2.1. + */ + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { + if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == + SDRAM_CFG_SDRAM_TYPE_DDR2) + out_be32(&gur->ddrioovcr, 0x90000000); + else + out_be32(&gur->ddrioovcr, 0xA8000000); + } +#endif + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 8f13cd8..d20c94c 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -361,6 +361,7 @@ void fdt_add_enet_stashing(void *fdt) } #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) +#ifdef CONFIG_SYS_DPAA_FMAN static void ft_fixup_clks(void *blob, const char *compat, u32 offset, unsigned long freq) { @@ -374,12 +375,14 @@ static void ft_fixup_clks(void *blob, const char *compat, u32 offset, "for %s: %s\n", compat, fdt_strerror(off)); } } +#endif static void ft_fixup_dpaa_clks(void *blob) { sys_info_t sysinfo; get_sys_info(&sysinfo); +#ifdef CONFIG_SYS_DPAA_FMAN ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, sysinfo.freqFMan[0]); @@ -387,6 +390,7 @@ static void ft_fixup_dpaa_clks(void *blob) ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, sysinfo.freqFMan[1]); #endif +#endif #ifdef CONFIG_SYS_DPAA_PME do_fixup_by_compat_u32(blob, "fsl,pme", diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 4307a4c..07e58ed 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -482,6 +482,13 @@ static void wait_for_rstdone(unsigned int bank) printf("SERDES: timeout resetting bank %u\n", bank + 1); } + +void __soc_serdes_init(void) +{ + /* Allow for SoC-specific initialization in <SOC>_serdes.c */ +}; +void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); + void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -570,6 +577,8 @@ void fsl_serdes_init(void) } } + soc_serdes_init(); + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 /* * Bank two uses the clock from bank three, so if bank two is enabled, diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index bd19094..e0ea502 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -120,6 +120,19 @@ static void setup_pme_liodn_base(void) #endif } +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +static void setup_raide_liodn_base(void) +{ + struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR; + + /* setup raid engine liodn base for data/desc ; both set to 47 */ + u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0]; + + out_be32(&raide->liodnbr, base); +} +#endif + void set_liodns(void) { /* setup general liodn offsets */ @@ -145,6 +158,12 @@ void set_liodns(void) #endif /* setup PME liodn base */ setup_pme_liodn_base(); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + /* raid engine ccr addr code for liodn */ + set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz); + setup_raide_liodn_base(); +#endif } static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) @@ -184,4 +203,8 @@ void fdt_fixup_liodn(void *blob) #endif #endif fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 758e6d7..ffc2a9a 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -221,14 +221,14 @@ ulong get_spin_virt_addr(void) #ifdef CONFIG_FSL_CORENET static void plat_mp_up(unsigned long bootpg) { - u32 up, cpu_up_mask, whoami; + u32 cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_virt_addr(); volatile ccsr_gur_t *gur; volatile ccsr_local_t *ccm; volatile ccsr_rcpm_t *rcpm; volatile ccsr_pic_t *pic; int timeout = 10; - u32 nr_cpus; + u32 mask = cpu_mask(); struct law_entry e; gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -236,8 +236,6 @@ static void plat_mp_up(unsigned long bootpg) rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); - nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; - whoami = in_be32(&pic->whoami); cpu_up_mask = 1 << whoami; out_be32(&ccm->bstrl, bootpg); @@ -251,19 +249,18 @@ static void plat_mp_up(unsigned long bootpg) /* disable time base at the platform */ out_be32(&rcpm->ctbenrl, cpu_up_mask); - /* release the hounds */ - up = ((1 << nr_cpus) - 1); - out_be32(&gur->brrl, up); + out_be32(&gur->brrl, mask); /* wait for everyone */ while (timeout) { - int i; - for (i = 0; i < nr_cpus; i++) { - if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) - cpu_up_mask |= (1 << i); - }; + unsigned int i, cpu, nr_cpus = cpu_numcores(); - if ((cpu_up_mask & up) == up) + for_each_cpu(i, cpu, nr_cpus, mask) { + if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << cpu); + } + + if ((cpu_up_mask & mask) == mask) break; udelay(100); @@ -272,7 +269,7 @@ static void plat_mp_up(unsigned long bootpg) if (timeout == 0) printf("CPU up timeout. CPU up mask is %x should be %x\n", - cpu_up_mask, up); + cpu_up_mask, mask); /* enable time base at the platform */ out_be32(&rcpm->ctbenrl, 0); @@ -283,7 +280,7 @@ static void plat_mp_up(unsigned long bootpg) mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0); - out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); + out_be32(&rcpm->ctbenrl, mask); #ifdef CONFIG_MPC8xxx_DISABLE_BPTR /* diff --git a/arch/powerpc/cpu/mpc85xx/p3060_ids.c b/arch/powerpc/cpu/mpc85xx/p3060_ids.c new file mode 100644 index 0000000..07703d4 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p3060_ids.c @@ -0,0 +1,113 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO(11, 12, 6, 5), + SET_QP_INFO(13, 14, 7, 6), + SET_QP_INFO(15, 16, 8, 7), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ +}; +#endif + +struct liodn_id_table liodn_tbl[] = { + SET_USB_LIODN(1, "fsl-usb2-mph", 127), + SET_USB_LIODN(2, "fsl-usb2-dr", 157), + + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + + SET_DMA_LIODN(1, 196), + SET_DMA_LIODN(2, 197), + + SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), + +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + SET_PME_LIODN(128), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 1, 12), + SET_FMAN_RX_1G_LIODN(1, 2, 13), + SET_FMAN_RX_1G_LIODN(1, 3, 14), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); + +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 16), + SET_FMAN_RX_1G_LIODN(2, 1, 17), + SET_FMAN_RX_1G_LIODN(2, 2, 18), + SET_FMAN_RX_1G_LIODN(2, 3, 19), +}; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), + SET_SEC_JR_LIODN_ENTRY(1, 147, 155), + SET_SEC_JR_LIODN_ENTRY(2, 178, 186), + SET_SEC_JR_LIODN_ENTRY(3, 179, 187), + SET_SEC_RTIC_LIODN_ENTRY(a, 144), + SET_SEC_RTIC_LIODN_ENTRY(b, 145), + SET_SEC_RTIC_LIODN_ENTRY(c, 176), + SET_SEC_RTIC_LIODN_ENTRY(d, 177), + SET_SEC_DECO_LIODN_ENTRY(0, 129, 161), + SET_SEC_DECO_LIODN_ENTRY(1, 130, 162), + SET_SEC_DECO_LIODN_ENTRY(2, 131, 163), + SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), + SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c new file mode 100644 index 0000000..6387276 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c @@ -0,0 +1,138 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1, + SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, + NONE, NONE, AURORA, AURORA}, + [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, + SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA}, + [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, + [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, + [0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE, + AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} + +void soc_serdes_init(void) +{ + /* + * On the P3060 the devdisr2 register does not correctly reflect + * the state of the MACs based on the RCW fields. So disable the MACs + * based on the srds_prtcl and ec1, ec2, ec3 fields + */ + + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + u32 ec1_ext, ec2_ext; + + /* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */ + + if (!is_serdes_configured(SGMII_FM1_DTSEC3)) + devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3; + + if (!is_serdes_configured(SGMII_FM1_DTSEC4)) + devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4; + + if (!is_serdes_configured(SGMII_FM2_DTSEC1)) + devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1; + + if (!is_serdes_configured(SGMII_FM2_DTSEC2)) + devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2; + + if (!is_serdes_configured(SGMII_FM2_DTSEC3)) + devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3; + + if (!is_serdes_configured(SGMII_FM2_DTSEC4)) + devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4; + + if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) { + devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2; + } + + if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) { + devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1; + } + + ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT; + if (ec1_ext) { + if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) || + (ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII)) + devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4; + } + + ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT; + if (ec2_ext) { + if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) || + (ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII)) + devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4; + } + + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) == + FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII) + devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4; + + out_be32(&gur->devdisr2, devdisr2); +} diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 9836588..2911c13 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -97,6 +97,16 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), #ifdef CONFIG_SYS_DPAA_FMAN @@ -105,4 +115,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_PME [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), +#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index ecaa30d..418dd9d 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -151,7 +151,7 @@ static int fdt_qportal(void *blob, int off, int id, char *name, dev_handle = fdt_get_phandle(blob, dev_off); if (dev_handle <= 0) { dev_handle = fdt_alloc_phandle(blob); - ret = fdt_create_phandle(blob, dev_off, + ret = fdt_set_phandle(blob, dev_off, dev_handle); if (ret < 0) return ret; @@ -198,7 +198,10 @@ void fdt_fixup_qportals(void *blob) u32 liodns[2]; #endif const int *ci = fdt_getprop(blob, off, "cell-index", NULL); - int j, i = *ci; + int i = *ci; +#ifdef CONFIG_SYS_DPAA_FMAN + int j; +#endif err = fdt_setprop(blob, off, "compatible", compat, compat_len); if (err < 0) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a83dfeb..ce47532 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -41,6 +41,7 @@ void get_sys_info (sys_info_t * sysInfo) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + unsigned int cpu; const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -97,11 +98,11 @@ void get_sys_info (sys_info_t * sysInfo) freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; } rcw_tmp = in_be32(&gur->rcwsr[3]); - for (i = 0; i < cpu_numcores(); i++) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; - sysInfo->freqProcessor[i] = + sysInfo->freqProcessor[cpu] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; } diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 878a3d6..5e0d78d 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -83,6 +83,45 @@ _start_e500: +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) + /* ISBC uses L2 as stack. + * Disable L2 cache here so that u-boot can enable it later + * as part of it's normal flow + */ + + /* Check if L2 is enabled */ + mfspr r3, SPRN_L2CSR0 + lis r2, L2CSR0_L2E@h + ori r2, r2, L2CSR0_L2E@l + and. r4, r3, r2 + beq l2_disabled + + mfspr r3, SPRN_L2CSR0 + /* Flush L2 cache */ + lis r2,(L2CSR0_L2FL)@h + ori r2, r2, (L2CSR0_L2FL)@l + or r3, r2, r3 + sync + isync + mtspr SPRN_L2CSR0,r3 + isync +1: + mfspr r3, SPRN_L2CSR0 + and. r1, r3, r2 + bne 1b + + mfspr r3, SPRN_L2CSR0 + lis r2, L2CSR0_L2E@h + ori r2, r2, L2CSR0_L2E@l + andc r4, r3, r2 + sync + isync + mtspr SPRN_L2CSR0,r4 + isync + +l2_disabled: +#endif + /* clear registers/arrays not reset by hardware */ /* L1 */ @@ -279,10 +318,244 @@ _start_e500: #endif /* CONFIG_MPC8569 */ +/* + * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default + * location is not where we want it. This typically happens on a 36-bit + * system, where we want to move CCSR to near the top of 36-bit address space. + * + * To move CCSR, we create two temporary TLBs, one for the old location, and + * another for the new location. On CoreNet systems, we also need to create + * a special, temporary LAW. + * + * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for + * long-term TLBs, so we use TLB0 here. + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) + +#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) +#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." +#endif + +purge_old_ccsr_tlb: + lis r8, CONFIG_SYS_CCSRBAR@h + ori r8, r8, CONFIG_SYS_CCSRBAR@l + lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l + + /* + * In a multi-stage boot (e.g. NAND boot), a previous stage may have + * created a TLB for CCSR, which will interfere with our relocation + * code. Since we're going to create a new TLB for CCSR anyway, + * it should be safe to delete this old TLB here. We have to search + * for it, though. + */ + + li r1, 0 + mtspr MAS6, r1 /* Search the current address space and PID */ + tlbsx 0, r8 + mfspr r1, MAS1 + andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ + beq 1f /* Skip if no TLB found */ + + rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ + mtspr MAS1, r1 + tlbwe +1: + +create_ccsr_new_tlb: + /* + * Create a TLB for the new location of CCSR. Register R8 is reserved + * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). + */ + lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h + ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l + lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h + ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l + lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h + ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l + lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS0, r0 + mtspr MAS1, r1 + mtspr MAS2, r2 + mtspr MAS3, r3 + mtspr MAS7, r7 + isync + msync + tlbwe + + /* + * Create a TLB for the old location of CCSR. Register R9 is reserved + * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). + */ +create_ccsr_old_tlb: + lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h + ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l + lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h + ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l + lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l + li r7, 0 /* The default CCSR address is always a 32-bit number */ + mtspr MAS0, r0 + /* MAS1 is the same as above */ + mtspr MAS2, r2 + mtspr MAS3, r3 + mtspr MAS7, r7 + isync + msync + tlbwe + +#ifdef CONFIG_FSL_CORENET + +#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define LAW_EN 0x80000000 +#define LAW_SIZE_4K 0xb +#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) +#define CCSRAR_C 0x80000000 /* Commit */ + +create_temp_law: + /* + * On CoreNet systems, we create the temporary LAW using a special LAW + * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. + */ + lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r2, CCSRBAR_LAWAR@h + ori r2, r2, CCSRBAR_LAWAR@l + + stw r0, 0xc00(r9) /* LAWBARH0 */ + stw r1, 0xc04(r9) /* LAWBARL0 */ + sync + stw r2, 0xc08(r9) /* LAWAR0 */ + + /* + * Read back from LAWAR to ensure the update is complete. e500mc + * cores also require an isync. + */ + lwz r0, 0xc08(r9) /* LAWAR0 */ + isync + + /* + * Read the current CCSRBARH and CCSRBARL using load word instructions. + * Follow this with an isync instruction. This forces any outstanding + * accesses to configuration space to completion. + */ +read_old_ccsrbar: + lwz r0, 0(r9) /* CCSRBARH */ + lwz r0, 4(r9) /* CCSRBARH */ + isync + + /* + * Write the new values for CCSRBARH and CCSRBARL to their old + * locations. The CCSRBARH has a shadow register. When the CCSRBARH + * has a new value written it loads a CCSRBARH shadow register. When + * the CCSRBARL is written, the CCSRBARH shadow register contents + * along with the CCSRBARL value are loaded into the CCSRBARH and + * CCSRBARL registers, respectively. Follow this with a sync + * instruction. + */ +write_new_ccsrbar: + lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r2, CCSRAR_C@h + ori r2, r2, CCSRAR_C@l + + stw r0, 0(r9) /* Write to CCSRBARH */ + sync /* Make sure we write to CCSRBARH first */ + stw r1, 4(r9) /* Write to CCSRBARL */ + sync + + /* + * Write a 1 to the commit bit (C) of CCSRAR at the old location. + * Follow this with a sync instruction. + */ + stw r2, 8(r9) + sync + + /* Delete the temporary LAW */ +delete_temp_law: + li r1, 0 + stw r1, 0xc08(r8) + sync + stw r1, 0xc00(r8) + stw r1, 0xc04(r8) + sync + +#else /* #ifdef CONFIG_FSL_CORENET */ + +write_new_ccsrbar: + /* + * Read the current value of CCSRBAR using a load word instruction + * followed by an isync. This forces all accesses to configuration + * space to complete. + */ + sync + lwz r0, 0(r9) + isync + +/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ +#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ + (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) + + /* Write the new value to CCSRBAR. */ + lis r0, CCSRBAR_PHYS_RS12@h + ori r0, r0, CCSRBAR_PHYS_RS12@l + stw r0, 0(r9) + sync + + /* + * The manual says to perform a load of an address that does not + * access configuration space or the on-chip SRAM using an existing TLB, + * but that doesn't appear to be necessary. We will do the isync, + * though. + */ + isync + + /* + * Read the contents of CCSRBAR from its new location, followed by + * another isync. + */ + lwz r0, 0(r8) + isync + +#endif /* #ifdef CONFIG_FSL_CORENET */ + + /* Delete the temporary TLBs */ +delete_temp_tlbs: + lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h + ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l + li r1, 0 + lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h + ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l + mtspr MAS0, r0 + mtspr MAS1, r1 + mtspr MAS2, r2 + isync + msync + tlbwe + + lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h + ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l + lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h + ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l + mtspr MAS0, r0 + mtspr MAS2, r2 + isync + msync + tlbwe +#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ + +create_init_ram_area: lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l -#ifndef CONFIG_SYS_RAMBOOT +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) /* create a temp mapping in AS=1 to the 4M boot window */ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l @@ -293,6 +566,20 @@ _start_e500: /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + /* create a temp mapping in AS = 1 for Flash mapping + * created by PBL for ISBC code + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l #else /* * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 8410bd7..852f9aa 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -23,6 +23,8 @@ * MA 02111-1307 USA */ +#include "config.h" /* CONFIG_BOARDDIR */ + OUTPUT_ARCH(powerpc) SECTIONS { @@ -52,8 +54,18 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; - - .resetvec ADDR(.text) + 0xffc : { +#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ + .bootpg ADDR(.text) + 0x1000 : + { + start.o (.bootpg) + } +#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#elif defined(CONFIG_FSL_ELBC) +#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ +#else +#error unknown NAND controller +#endif + .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff @@ -64,4 +76,4 @@ SECTIONS } __bss_end__ = .; } -ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big"); +ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 767bc52..0365ca8 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -27,6 +27,7 @@ #include <common.h> #include <command.h> #include <tsec.h> +#include <fm_eth.h> #include <netdev.h> #include <asm/cache.h> #include <asm/io.h> @@ -102,6 +103,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2041, P2041_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), CPU_TYPE_ENTRY(P3041, P3041_E, 4), + CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3), + CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3), CPU_TYPE_ENTRY(P4040, P4040, 4), CPU_TYPE_ENTRY(P4040, P4040_E, 4), CPU_TYPE_ENTRY(P4080, P4080, 8), @@ -129,13 +132,33 @@ struct cpu_type *identify_cpu(u32 ver) return &cpu_type_unknown; } +#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 +#define MPC8xxx_PICFRR_NCPU_SHIFT 8 + +/* + * Return a 32-bit mask indicating which cores are present on this SOC. + */ +u32 cpu_mask() +{ + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + struct cpu_type *cpu = gd->cpu; + + /* better to query feature reporting register than just assume 1 */ + if (cpu == &cpu_type_unknown) + return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> + MPC8xxx_PICFRR_NCPU_SHIFT) + 1; + + return cpu->mask; +} + +/* + * Return the number of cores on this SOC. + */ int cpu_numcores() { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->cpu; /* better to query feature reporting register than just assume 1 */ -#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 -#define MPC8xxx_PICFRR_NCPU_SHIFT 8 if (cpu == &cpu_type_unknown) return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> MPC8xxx_PICFRR_NCPU_SHIFT) + 1; @@ -143,6 +166,18 @@ int cpu_numcores() { return cpu->num_cores; } +/* + * Check if the given core ID is valid + * + * Returns zero if it isn't, 1 if it is. + */ +int is_core_valid(unsigned int core) +{ + struct cpu_type *cpu = gd->cpu; + + return !!((1 << core) & cpu->mask); +} + int probecpu (void) { uint svr; @@ -174,5 +209,8 @@ int cpu_eth_init(bd_t *bis) tsec_standard_init(bis); #endif +#ifdef CONFIG_FMAN_ENET + fm_standard_init(bis); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 3824aad..15cd375 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -18,7 +18,9 @@ #include "ddr.h" -#ifdef CONFIG_MPC85xx +#ifdef CONFIG_MPC83xx + #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR +#elif defined(CONFIG_MPC85xx) #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR #elif defined(CONFIG_MPC86xx) #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR @@ -94,6 +96,10 @@ static inline int fsl_ddr_get_rtt(void) * 6 if 2.5ns > tCK >= 1.875ns * 7 if 1.875ns > tCK >= 1.5ns * 8 if 1.5ns > tCK >= 1.25ns + * 9 if 1.25ns > tCK >= 1.07ns + * 10 if 1.07ns > tCK >= 0.935ns + * 11 if 0.935ns > tCK >= 0.833ns + * 12 if 0.833ns > tCK >= 0.75ns */ static inline unsigned int compute_cas_write_latency(void) { @@ -108,8 +114,18 @@ static inline unsigned int compute_cas_write_latency(void) cwl = 7; else if (mclk_ps >= 1250) cwl = 8; - else - cwl = 8; + else if (mclk_ps >= 1070) + cwl = 9; + else if (mclk_ps >= 935) + cwl = 10; + else if (mclk_ps >= 833) + cwl = 11; + else if (mclk_ps >= 750) + cwl = 12; + else { + cwl = 12; + printf("Warning: CWL is out of range\n"); + } return cwl; } @@ -146,7 +162,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, break; case 2: if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ - (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0)) + (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) go_config = 1; break; case 3: @@ -617,7 +633,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ unsigned int dll_rst_dis; /* DLL reset disable */ unsigned int dqs_cfg; /* DQS configuration */ - unsigned int odt_cfg; /* ODT configuration */ + unsigned int odt_cfg = 0; /* ODT configuration */ unsigned int num_pr; /* Number of posted refreshes */ unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ unsigned int ap_en; /* Address Parity Enable */ @@ -625,15 +641,16 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int rcw_en = 0; /* Register Control Word Enable */ unsigned int md_en = 0; /* Mirrored DIMM Enable */ unsigned int qd_en = 0; /* quad-rank DIMM Enable */ + int i; dll_rst_dis = 1; /* Make this configurable */ dqs_cfg = popts->DQS_config; - if (popts->cs_local_opts[0].odt_rd_cfg - || popts->cs_local_opts[0].odt_wr_cfg) { - /* FIXME */ - odt_cfg = 2; - } else { - odt_cfg = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->cs_local_opts[i].odt_rd_cfg + || popts->cs_local_opts[i].odt_wr_cfg) { + odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; + break; + } } num_pr = 1; /* Make this configurable */ @@ -1018,7 +1035,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR2) const unsigned int mclk_ps = get_memory_clk_period_ps(); #endif - + dqs_en = !popts->DQS_config; rtt = fsl_ddr_get_rtt(); al = additive_latency; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 8132e68..20c7db0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -448,7 +448,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, #if defined(CONFIG_FSL_DDR2) if (lowest_good_caslat < 4) { - additive_latency = picos_to_mclk(tRCD_ps) - lowest_good_caslat; + additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat) + ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0; if (mclk_to_picos(additive_latency) > tRCD_ps) { additive_latency = picos_to_mclk(tRCD_ps); debug("setting additive_latency to %u because it was " diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 249fd7d..5699b0c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -34,14 +34,17 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS, }; -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ }; -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index bd9c466..4dc748b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -26,14 +26,15 @@ extern void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num); -typedef struct { +struct dynamic_odt { unsigned int odt_rd_cfg; unsigned int odt_wr_cfg; unsigned int odt_rtt_norm; unsigned int odt_rtt_wr; -} dynamic_odt_t; +}; -static const dynamic_odt_t single_Q[4] = { +#ifdef CONFIG_FSL_DDR3 +static const struct dynamic_odt single_Q[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_CS_AND_OTHER_DIMM, @@ -60,7 +61,7 @@ static const dynamic_odt_t single_Q[4] = { } }; -static const dynamic_odt_t single_D[4] = { +static const struct dynamic_odt single_D[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_ALL, @@ -77,7 +78,7 @@ static const dynamic_odt_t single_D[4] = { {0, 0, 0, 0} }; -static const dynamic_odt_t single_S[4] = { +static const struct dynamic_odt single_S[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_ALL, @@ -89,7 +90,7 @@ static const dynamic_odt_t single_S[4] = { {0, 0, 0, 0}, }; -static const dynamic_odt_t dual_DD[4] = { +static const struct dynamic_odt dual_DD[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_SAME_DIMM, @@ -116,7 +117,7 @@ static const dynamic_odt_t dual_DD[4] = { } }; -static const dynamic_odt_t dual_DS[4] = { +static const struct dynamic_odt dual_DS[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_SAME_DIMM, @@ -137,7 +138,7 @@ static const dynamic_odt_t dual_DS[4] = { }, {0, 0, 0, 0} }; -static const dynamic_odt_t dual_SD[4] = { +static const struct dynamic_odt dual_SD[4] = { { /* cs0 */ FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_ALL, @@ -159,7 +160,7 @@ static const dynamic_odt_t dual_SD[4] = { } }; -static const dynamic_odt_t dual_SS[4] = { +static const struct dynamic_odt dual_SS[4] = { { /* cs0 */ FSL_DDR_ODT_OTHER_DIMM, FSL_DDR_ODT_ALL, @@ -176,7 +177,7 @@ static const dynamic_odt_t dual_SS[4] = { {0, 0, 0, 0} }; -static const dynamic_odt_t dual_D0[4] = { +static const struct dynamic_odt dual_D0[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_SAME_DIMM, @@ -193,7 +194,7 @@ static const dynamic_odt_t dual_D0[4] = { {0, 0, 0, 0} }; -static const dynamic_odt_t dual_0D[4] = { +static const struct dynamic_odt dual_0D[4] = { {0, 0, 0, 0}, {0, 0, 0, 0}, { /* cs2 */ @@ -210,7 +211,7 @@ static const dynamic_odt_t dual_0D[4] = { } }; -static const dynamic_odt_t dual_S0[4] = { +static const struct dynamic_odt dual_S0[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_CS, @@ -223,7 +224,7 @@ static const dynamic_odt_t dual_S0[4] = { }; -static const dynamic_odt_t dual_0S[4] = { +static const struct dynamic_odt dual_0S[4] = { {0, 0, 0, 0}, {0, 0, 0, 0}, { /* cs2 */ @@ -236,7 +237,7 @@ static const dynamic_odt_t dual_0S[4] = { }; -static const dynamic_odt_t odt_unknown[4] = { +static const struct dynamic_odt odt_unknown[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, FSL_DDR_ODT_CS, @@ -262,7 +263,218 @@ static const dynamic_odt_t odt_unknown[4] = { DDR3_RTT_OFF } }; +#else /* CONFIG_FSL_DDR3 */ +static const struct dynamic_odt single_Q[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt single_D[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; +static const struct dynamic_odt single_S[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, +}; + +static const struct dynamic_odt dual_DD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; + +static const struct dynamic_odt dual_DS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_SD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; + +static const struct dynamic_odt dual_SS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_D0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_0D[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; + +static const struct dynamic_odt dual_S0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt dual_0S[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt odt_unknown[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; +#endif unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, dimm_params_t *pdimm, @@ -271,7 +483,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; - const dynamic_odt_t *pdodt = odt_unknown; + const struct dynamic_odt *pdodt = odt_unknown; + ulong ddr_freq; /* * Extract hwconfig from environment since we have not properly setup @@ -336,7 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -#if defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; @@ -716,6 +929,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1; + ddr_freq = get_ddr_freq(0) / 1000000; + if (popts->registered_dimm_en) { + popts->rcw_override = 1; + popts->rcw_1 = 0x000a5a00; + if (ddr_freq <= 800) + popts->rcw_2 = 0x00000000; + else if (ddr_freq <= 1066) + popts->rcw_2 = 0x00100000; + else if (ddr_freq <= 1333) + popts->rcw_2 = 0x00200000; + else + popts->rcw_2 = 0x00300000; + } + fsl_ddr_board_options(popts, pdimm, ctrl_num); return 0; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 104d360..eb6a17a 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -20,7 +20,8 @@ #define ULL_8FS 0xFFFFFFFFULL /* - * Round mclk_ps to nearest 10 ps in memory controller code. + * Round up mclk_ps to nearest 1 ps in memory controller code + * if the error is 0.5ps or more. * * If an imprecise data rate is too high due to rounding error * propagation, compute a suitably rounded mclk_ps to compute @@ -32,42 +33,37 @@ unsigned int get_memory_clk_period_ps(void) unsigned int result; /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ - unsigned long long mclk_ps = ULL_2E12; - - /* Add 5*data_rate, for rounding */ - mclk_ps += 5*(unsigned long long)data_rate; + unsigned long long rem, mclk_ps = ULL_2E12; /* Now perform the big divide, the result fits in 32-bits */ - do_div(mclk_ps, data_rate); - result = mclk_ps; + rem = do_div(mclk_ps, data_rate); + result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; - /* We still need to round to 10ps */ - return 10 * (result/10); + return result; } /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ unsigned int picos_to_mclk(unsigned int picos) { unsigned long long clks, clks_rem; + unsigned long data_rate = get_ddr_freq(0); /* Short circuit for zero picos */ if (!picos) return 0; /* First multiply the time by the data rate (32x32 => 64) */ - clks = picos * (unsigned long long)get_ddr_freq(0); - + clks = picos * (unsigned long long)data_rate; /* * Now divide by 5^12 and track the 32-bit remainder, then divide * by 2*(2^12) using shifts (and updating the remainder). */ clks_rem = do_div(clks, UL_5POW12); - clks_rem <<= 13; - clks_rem |= clks & (UL_2POW13-1); + clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; clks >>= 13; - /* If we had a remainder, then round up */ - if (clks_rem) + /* If we had a remainder greater than the 1ps error, then round up */ + if (clks_rem > data_rate) clks++; /* Clamp to the maximum representable value */ @@ -133,10 +129,13 @@ fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, void board_add_ram_info(int use_default) { -#if defined(CONFIG_MPC85xx) - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); +#if defined(CONFIG_MPC83xx) + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + ccsr_ddr_t *ddr = (void *)&immap->ddr; +#elif defined(CONFIG_MPC85xx) + ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); #elif defined(CONFIG_MPC86xx) - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR); + ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR); #endif #if (CONFIG_NUM_DDR_CONTROLLERS > 1) uint32_t cs0_config = in_be32(&ddr->cs0_config); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 285051d..5bb9f53 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -63,7 +63,7 @@ void ft_fixup_num_cores(void *blob) { while (off != -FDT_ERR_NOTFOUND) { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - if ((*reg > num_cores-1) || (is_core_disabled(*reg))) { + if (!is_core_valid(*reg) || is_core_disabled(*reg)) { int ph = fdt_get_phandle(blob, off); /* Delete the cpu node once there are no cpu handles */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index e794821..6682496 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -43,10 +43,12 @@ void init_early_memctl_regs(void) set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT) set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); #endif +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 9aad9be..d138636 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -42,7 +42,10 @@ #define CONFIG_SYS_BOOT_GET_KBD #ifndef CONFIG_MAX_MEM_MAPPED -#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || \ + defined(CONFIG_E500) || \ + defined(CONFIG_MPC86xx) || \ + defined(CONFIG_E300) #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #else #define CONFIG_MAX_MEM_MAPPED (256 << 20) @@ -96,6 +99,11 @@ #endif /* TSEC_ENET */ #endif /* !CONFIG_PHYLIB */ +/* The FMAN driver uses the PHYLIB infrastructure */ +#if defined(CONFIG_FMAN_ENET) +#define CONFIG_PHYLIB +#endif + /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 04ca989..c3d6ba9 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,6 +23,10 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ +#ifdef CONFIG_SYS_CCSRBAR_DEFAULT +#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." +#endif + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -34,34 +38,43 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 +#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 @@ -70,6 +83,7 @@ #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 @@ -78,11 +92,13 @@ #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 @@ -97,6 +113,10 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 +#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -105,6 +125,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -115,6 +136,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -127,6 +149,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -141,6 +164,10 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 +#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 /* P1015 is single core version of P1024 */ #elif defined(CONFIG_P1015) @@ -149,6 +176,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -164,6 +192,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -177,6 +206,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -184,6 +214,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -193,6 +224,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -204,6 +236,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -219,6 +252,7 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -227,6 +261,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -237,6 +272,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -248,6 +284,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -255,6 +292,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -269,8 +307,10 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P2041) @@ -285,8 +325,10 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) @@ -301,10 +343,27 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#elif defined(CONFIG_PPC_P3060) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 + #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 @@ -313,6 +372,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -328,6 +388,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -354,8 +415,10 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) @@ -370,12 +433,18 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform #endif +#ifndef CONFIG_SYS_CCSRBAR_DEFAULT +#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index bc063ea..93639ba 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -31,6 +31,11 @@ #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ +#define DDR2_RTT_OFF 0 +#define DDR2_RTT_75_OHM 1 +#define DDR2_RTT_150_OHM 2 +#define DDR2_RTT_50_OHM 3 + #if defined(CONFIG_FSL_DDR1) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; @@ -92,6 +97,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG2_D_INIT 0x00000010 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 +#define SDRAM_CFG2_ODT_NEVER 0 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1 +#define SDRAM_CFG2_ODT_ONLY_READ 2 +#define SDRAM_CFG2_ODT_ALWAYS 3 #define TIMING_CFG_2_CPO_MASK 0x0F800000 diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/arch/powerpc/include/asm/fsl_dtsec.h new file mode 100644 index 0000000..d1d993c --- /dev/null +++ b/arch/powerpc/include/asm/fsl_dtsec.h @@ -0,0 +1,244 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __DTSEC_H__ +#define __DTSEC_H__ + +#include <asm/types.h> + +struct dtsec { + u32 tsec_id; /* controller ID and version */ + u32 tsec_id2; /* controller ID and configuration */ + u32 ievent; /* interrupt event */ + u32 imask; /* interrupt mask */ + u32 res0; + u32 ecntrl; /* ethernet control and configuration */ + u32 ptv; /* pause time value */ + u32 tbipa; /* TBI PHY address */ + u32 res1[8]; + u32 tctrl; /* Transmit control register */ + u32 res2[3]; + u32 rctrl; /* Receive control register */ + u32 res3[11]; + u32 igaddr[8]; /* Individual group address */ + u32 gaddr[8]; /* group address */ + u32 res4[16]; + u32 maccfg1; /* MAC configuration register 1 */ + u32 maccfg2; /* MAC configuration register 2 */ + u32 ipgifg; /* inter-packet/inter-frame gap */ + u32 hafdup; /* half-duplex control */ + u32 maxfrm; /* Maximum frame size */ + u32 res5[3]; + u32 miimcfg; /* MII management configuration */ + u32 miimcom; /* MII management command */ + u32 miimadd; /* MII management address */ + u32 miimcon; /* MII management control */ + u32 miimstat; /* MII management status */ + u32 miimind; /* MII management indicator */ + u32 res6; + u32 ifstat; /* Interface status */ + u32 macstnaddr1; /* MAC station address 1 */ + u32 macstnaddr2; /* MAC station address 2 */ + u32 res7[46]; + /* transmit and receive counter */ + u32 tr64; /* Tx and Rx 64 bytes frame */ + u32 tr127; /* Tx and Rx 65 to 127 bytes frame */ + u32 tr255; /* Tx and Rx 128 to 255 bytes frame */ + u32 tr511; /* Tx and Rx 256 to 511 bytes frame */ + u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */ + u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */ + u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */ + /* receive counters */ + u32 rbyt; /* Receive byte counter */ + u32 rpkt; /* Receive packet counter */ + u32 rfcs; /* Receive FCS error */ + u32 rmca; /* Receive multicast packet */ + u32 rbca; /* Receive broadcast packet */ + u32 rxcf; /* Receive control frame */ + u32 rxpf; /* Receive pause frame */ + u32 rxuo; /* Receive unknown OP code */ + u32 raln; /* Receive alignment error */ + u32 rflr; /* Receive frame length error */ + u32 rcde; /* Receive code error */ + u32 rcse; /* Receive carrier sense error */ + u32 rund; /* Receive undersize packet */ + u32 rovr; /* Receive oversize packet */ + u32 rfrg; /* Receive fragments counter */ + u32 rjbr; /* Receive jabber counter */ + u32 rdrp; /* Receive drop counter */ + /* transmit counters */ + u32 tbyt; /* Transmit byte counter */ + u32 tpkt; /* Transmit packet */ + u32 tmca; /* Transmit multicast packet */ + u32 tbca; /* Transmit broadcast packet */ + u32 txpf; /* Transmit pause control frame */ + u32 tdfr; /* Transmit deferral packet */ + u32 tedf; /* Transmit excessive deferral pkt */ + u32 tscl; /* Transmit single collision pkt */ + u32 tmcl; /* Transmit multiple collision pkt */ + u32 tlcl; /* Transmit late collision pkt */ + u32 txcl; /* Transmit excessive collision */ + u32 tncl; /* Transmit total collision */ + u32 res8; + u32 tdrp; /* Transmit drop frame */ + u32 tjbr; /* Transmit jabber frame */ + u32 tfcs; /* Transmit FCS error */ + u32 txcf; /* Transmit control frame */ + u32 tovr; /* Transmit oversize frame */ + u32 tund; /* Transmit undersize frame */ + u32 tfrg; /* Transmit fragments frame */ + /* counter controls */ + u32 car1; /* carry register 1 */ + u32 car2; /* carry register 2 */ + u32 cam1; /* carry register 1 mask */ + u32 cam2; /* carry register 2 mask */ + u32 res9[80]; +}; + + +/* TBI register addresses */ +#define TBI_CR 0x00 +#define TBI_SR 0x01 +#define TBI_ANA 0x04 +#define TBI_ANLPBPA 0x05 +#define TBI_ANEX 0x06 +#define TBI_TBICON 0x11 + +/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +/* IEVENT - interrupt events register */ +#define IEVENT_BABR 0x80000000 /* Babbling receive error */ +#define IEVENT_RXC 0x40000000 /* pause control frame received */ +#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */ +#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ +#define IEVENT_BABT 0x01000000 /* Babbling transmit error */ +#define IEVENT_TXC 0x00800000 /* control frame transmitted */ +#define IEVENT_TXE 0x00400000 /* Transmit channel error */ +#define IEVENT_LC 0x00040000 /* Late collision occurred */ +#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */ +#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ +#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */ +#define IEVENT_MMRD 0x00000400 /* MII management read complete */ +#define IEVENT_MMWR 0x00000200 /* MII management write complete */ +#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */ +#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */ +#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +/* IMASK - interrupt mask register */ +#define IMASK_BREN 0x80000000 /* Babbling receive enable */ +#define IMASK_RXCEN 0x40000000 /* receive control enable */ +#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */ +#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */ +#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */ +#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */ +#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */ +#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */ +#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */ +#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */ +#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */ +#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */ +#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */ +#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */ +#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */ +#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */ + +#define IMASK_MASK_ALL 0x00000000 + +/* ECNTRL - ethernet control register */ +#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */ +#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */ +#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */ +#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */ +#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */ +#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */ +#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */ +#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps + 0- RGMII 10 Mbps, SGMII 10 Mbps */ +#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */ +#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */ + +#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM) + +/* TCTRL - Transmit control register */ +#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */ +#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */ +#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */ +#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */ + +/* RCTRL - Receive control register */ +#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */ +#define RCTRL_PAL_SHIFT 16 +#define RCTRL_CFA 0x00008000 /* control frame accept enable */ +#define RCTRL_GHTX 0x00000800 /* group address hash table extend */ +#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */ +#define RCTRL_GRS 0x00000020 /* graceful receive stop */ +#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */ +#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */ +#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */ +#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */ +#define RCTRL_UPROM 0x00000001 /* all unicast frame received */ + +/* MACCFG1 - MAC configuration 1 register */ +#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */ +#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */ +#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */ +#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */ +#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */ +#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */ +#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ +#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ +#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */ +#define MACCFG1_RX_EN 0x00000004 /* Rx enable */ +#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */ +#define MACCFG1_TX_EN 0x00000001 /* Tx enable */ +#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN) + +/* MACCFG2 - MAC configuration 2 register */ +#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */ +#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK) +#define MACCFG2_IF_MODE_MASK 0x00000300 +#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */ +#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */ +#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */ +#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */ +#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */ +#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */ +#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */ +#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */ +#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */ +#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */ + +struct fsl_enet_mac; + +void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h index 6c01ffc..fddc0cc 100644 --- a/arch/powerpc/include/asm/fsl_fman.h +++ b/arch/powerpc/include/asm/fsl_fman.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -82,6 +82,189 @@ typedef struct fm_qmi { u8 res[1024]; } fm_qmi_t; +struct fm_bmi_rx_port { + u32 fmbm_rcfg; /* Rx configuration */ + u32 fmbm_rst; /* Rx status */ + u32 fmbm_rda; /* Rx DMA attributes */ + u32 fmbm_rfp; /* Rx FIFO parameters */ + u32 fmbm_rfed; /* Rx frame end data */ + u32 fmbm_ricp; /* Rx internal context parameters */ + u32 fmbm_rim; /* Rx internal margins */ + u32 fmbm_rebm; /* Rx external buffer margins */ + u32 fmbm_rfne; /* Rx frame next engine */ + u32 fmbm_rfca; /* Rx frame command attributes */ + u32 fmbm_rfpne; /* Rx frame parser next engine */ + u32 fmbm_rpso; /* Rx parse start offset */ + u32 fmbm_rpp; /* Rx policer profile */ + u32 fmbm_rccb; /* Rx coarse classification base */ + u32 res1[0x2]; + u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */ + u32 fmbm_rfqid; /* Rx frame queue ID */ + u32 fmbm_refqid; /* Rx error frame queue ID */ + u32 fmbm_rfsdm; /* Rx frame status discard mask */ + u32 fmbm_rfsem; /* Rx frame status error mask */ + u32 fmbm_rfene; /* Rx frame enqueue next engine */ + u32 res2[0x23]; + u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */ + u32 fmbm_acnt[0x8]; /* allocate counter */ + u32 res3[0x8]; + u32 fmbm_cgm[0x8]; /* congestion group map */ + u32 fmbm_mpd; /* BMan pool depletion */ + u32 res4[0x1F]; + u32 fmbm_rstc; /* Rx statistics counters */ + u32 fmbm_rfrc; /* Rx frame counters */ + u32 fmbm_rfbc; /* Rx bad frames counter */ + u32 fmbm_rlfc; /* Rx large frames counter */ + u32 fmbm_rffc; /* Rx filter frames counter */ + u32 fmbm_rfdc; /* Rx frame discard counter */ + u32 fmbm_rfldec; /* Rx frames list DMA error counter */ + u32 fmbm_rodc; /* Rx out of buffers discard counter */ + u32 fmbm_rbdc; /* Rx buffers deallocate counter */ + u32 res5[0x17]; + u32 fmbm_rpc; /* Rx performance counters */ + u32 fmbm_rpcp; /* Rx performance count parameters */ + u32 fmbm_rccn; /* Rx cycle counter */ + u32 fmbm_rtuc; /* Rx tasks utilization counter */ + u32 fmbm_rrquc; /* Rx receive queue utilization counter */ + u32 fmbm_rduc; /* Rx DMA utilization counter */ + u32 fmbm_rfuc; /* Rx FIFO utilization counter */ + u32 fmbm_rpac; /* Rx pause activation counter */ + u32 res6[0x18]; + u32 fmbm_rdbg; /* Rx debug configuration */ +}; + +/* FMBM_RCFG - Rx configuration */ +#define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */ +#define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */ +#define FMBM_RCFG_IM 0x01000000 /* independent mode */ + +/* FMBM_RST - Rx status */ +#define FMBM_RST_BSY 0x80000000 /* Rx port is busy */ + +/* FMBM_RFCA - Rx frame command attributes */ +#define FMBM_RFCA_ORDER 0x80000000 +#define FMBM_RFCA_MR_MASK 0x003f0000 +#define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK) + +/* FMBM_RSTC - Rx statistics */ +#define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */ + +struct fm_bmi_tx_port { + u32 fmbm_tcfg; /* Tx configuration */ + u32 fmbm_tst; /* Tx status */ + u32 fmbm_tda; /* Tx DMA attributes */ + u32 fmbm_tfp; /* Tx FIFO parameters */ + u32 fmbm_tfed; /* Tx frame end data */ + u32 fmbm_ticp; /* Tx internal context parameters */ + u32 fmbm_tfne; /* Tx frame next engine */ + u32 fmbm_tfca; /* Tx frame command attributes */ + u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */ + u32 fmbm_tfeqid;/* Tx error frame queue ID */ + u32 fmbm_tfene; /* Tx frame enqueue next engine */ + u32 fmbm_trlmts;/* Tx rate limiter scale */ + u32 fmbm_trlmt; /* Tx rate limiter */ + u32 res0[0x73]; + u32 fmbm_tstc; /* Tx statistics counters */ + u32 fmbm_tfrc; /* Tx frame counter */ + u32 fmbm_tfdc; /* Tx frames discard counter */ + u32 fmbm_tfledc;/* Tx frame length error discard counter */ + u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */ + u32 fmbm_tbdc; /* Tx buffers deallocate counter */ + u32 res1[0x1a]; + u32 fmbm_tpc; /* Tx performance counters */ + u32 fmbm_tpcp; /* Tx performance count parameters */ + u32 fmbm_tccn; /* Tx cycle counter */ + u32 fmbm_ttuc; /* Tx tasks utilization counter */ + u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */ + u32 fmbm_tduc; /* Tx DMA utilization counter */ + u32 fmbm_tfuc; /* Tx FIFO utilization counter */ + u32 res2[0x19]; + u32 fmbm_tdcfg; /* Tx debug configuration */ +}; + +/* FMBM_TCFG - Tx configuration */ +#define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */ +#define FMBM_TCFG_IM 0x01000000 /* independent mode enable */ + +/* FMBM_TST - Tx status */ +#define FMBM_TST_BSY 0x80000000 /* Tx port is busy */ + +/* FMBM_TFCA - Tx frame command attributes */ +#define FMBM_TFCA_ORDER 0x80000000 +#define FMBM_TFCA_MR_MASK 0x003f0000 +#define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK) + +/* FMBM_TSTC - Tx statistics counters */ +#define FMBM_TSTC_EN 0x80000000 + +/* FMBM_INIT - BMI initialization register */ +#define FMBM_INIT_START 0x80000000 /* init internal buffers */ + +/* FMBM_CFG1 - BMI configuration 1 */ +#define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */ +#define FMBM_CFG1_FBPS_SHIFT 16 +#define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */ + +/* FMBM_IEVR - interrupt event */ +#define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */ +#define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */ +#define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */ +#define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC) + +/* FMBM_IER - interrupt enable */ +#define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */ +#define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */ +#define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */ + +#define FMBM_IER_DISABLE_ALL 0x00000000 + +/* FMBM_PP - BMI Port Parameters */ +#define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */ +#define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK) +#define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */ +#define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK) + +/* FMBM_PFS - BMI Port FIFO Size */ +#define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */ +#define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK) + +/* FMQM_GC - global configuration */ +#define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */ +#define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */ +#define FMQM_GC_STEN 0x10000000 /* enable global stat counters */ +#define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */ +#define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS) +#define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */ +#define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK) + +/* FMQM_EIE - error interrupt event register */ +#define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */ +#define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */ +#define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE) + +/* FMQM_EIEN - error interrupt enable register */ +#define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */ +#define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */ +#define FMQM_EIEN_DISABLE_ALL 0x00000000 + +/* FMQM_IE - interrupt event register */ +#define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */ +#define FMQM_IE_CLEAR_ALL FMQM_IE_SEE + +/* FMQM_IEN - interrupt enable register */ +#define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */ +#define FMQM_IEN_DISABLE_ALL 0x00000000 + +/* NIA - next invoked action */ +#define NIA_ENG_RISC 0x00000000 +#define NIA_ENG_MASK 0x007c0000 + +/* action code */ +#define NIA_RISC_AC_CC 0x00000006 +#define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */ +#define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */ +#define NIA_RISC_AC_HC 0x0000000c + typedef struct fm_parser { u8 res[1024]; } fm_parser_t; @@ -113,6 +296,27 @@ typedef struct fm_dma { u32 res[0x3c8]; } fm_dma_t; +/* FMDMSR - Fman DMA status register */ +#define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */ +#define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */ +#define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */ +#define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */ +#define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */ +#define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */ +#define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */ +#define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */ +#define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */ +#define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */ + +#define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \ + | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \ + | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \ + | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \ + | FMDMSR_SPDAT_FECC) + +/* FMDMMR - FMan DMA mode register */ +#define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */ + typedef struct fm_fpm { u32 fpmtnc; /* TNUM control */ u32 fpmprc; /* Port_ID control */ @@ -141,7 +345,7 @@ typedef struct fm_fpm { u32 fmcld; /* classifier debug control */ u32 fmnpi; /* normal pending interrupts */ u32 res5; - u32 fmnee; /* event and enable */ + u32 fmfpee; /* event and enable */ u32 fpmcev[0x4]; /* CPU event 0-3 */ u32 res6[0x4]; u32 fmfp_ps[0x40]; /* port status */ @@ -150,9 +354,47 @@ typedef struct fm_fpm { u32 res8[0xa0]; } fm_fpm_t; +/* FMFP_PRC - FPM Port_ID Control Register */ +#define FMFPPRC_PORTID_MASK 0x3f000000 +#define FMFPPRC_PORTID_SHIFT 24 +#define FMFPPRC_ORA_SHIFT 16 +#define FMFPPRC_RISC1 0x00000001 +#define FMFPPRC_RISC2 0x00000002 +#define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2) + +/* FPM Flush Control Register */ +#define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */ + +/* FMFP_EE - FPM event and enable register */ +#define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */ +#define FMFPEE_STL 0x40000000 /* stall of task ... */ +#define FMFPEE_SECC 0x20000000 /* single ECC error */ +#define FMFPEE_RFM 0x00010000 /* release FMan */ +#define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */ +#define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */ +#define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */ +#define FMFPEE_EHM 0x00000008 /* external halt enable */ +#define FMFPEE_UEC 0x00000004 /* FMan is not halted */ +#define FMFPEE_CER 0x00000002 /* only errornous task stalled */ +#define FMFPEE_DER 0x00000001 /* DMA error is just reported */ + +#define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \ + FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \ + FMFPEE_DER | FMFPEE_RFM) + +/* FMFP_RCR - FMan Rams Control and Event */ +#define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */ +#define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */ + typedef struct fm_imem { - u8 res[4*1024]; + u32 iadd; /* instruction address register */ + u32 idata; /* instruction data register */ + u32 itcfg; /* timing config register */ + u32 iready; /* ready register */ + u8 res[0xff0]; } fm_imem_t; +#define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */ +#define IRAM_READY 0x80000000 /* ready to use */ typedef struct fm_soft_parser { u8 res[4*1024]; @@ -200,10 +442,11 @@ typedef struct ccsr_fman { struct { fm_dtsec_t fm_dtesc; fm_mdio_t fm_mdio; - } mac[4]; - u8 res3[32*1024]; - fm_10gec_t fm_10gec; - fm_10gec_mdio_t fm_10gec_mdio; + } mac_1g[8]; /* support up to 8 1g controllers */ + struct { + fm_10gec_t fm_10gec; + fm_10gec_mdio_t fm_10gec_mdio; + } mac_10g[1]; u8 res4[48*1024]; fm_1588_t fm_1588; u8 res5[4*1024]; diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index d4d9809..7d95eb4 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -69,6 +69,7 @@ */ /* Enable ECC Encoder */ #define CSOR_NAND_ECC_ENC_EN 0x80000000 +#define CSOR_NAND_ECC_MODE_MASK 0x30000000 /* 4 bit correction per 520 Byte sector */ #define CSOR_NAND_ECC_MODE_4 0x00000000 /* 8 bit correction per 528 Byte sector */ @@ -857,10 +858,7 @@ struct fsl_ifc_nand { u32 res19[0x10]; u32 nand_fsr; u32 res20; - u32 nand_eccstat0; - u32 nand_eccstat1; - u32 nand_eccstat2; - u32 nand_eccstat3; + u32 nand_eccstat[4]; u32 res21[0x20]; u32 nanndcr; u32 res22[0x2]; @@ -953,5 +951,10 @@ struct fsl_ifc { struct fsl_ifc_gpcm ifc_gpcm; }; +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 +#undef CSPR_MSEL_NOR +#define CSPR_MSEL_NOR CSPR_MSEL_GPCM +#endif + #endif /* __ASSEMBLY__ */ #endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 801571f..9ad104e 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -147,9 +147,18 @@ extern void fdt_fixup_liodn(void *blob); offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, 0) +#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \ + SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \ + liodnA, \ + offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \ + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \ + offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \ + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) + extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; +extern struct liodn_id_table raide_liodn_tbl[]; extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; -extern int liodn_tbl_sz, sec_liodn_tbl_sz; +extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; #endif diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index e1c1212..8c3ea0b 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -35,6 +35,9 @@ enum fsl_dpaa_dev { #ifdef CONFIG_SYS_DPAA_PME FSL_HW_PORTAL_PME, #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + FSL_HW_PORTAL_RAID_ENGINE, +#endif }; struct qportal_info { diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h new file mode 100644 index 0000000..d1c1967 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -0,0 +1,43 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_SECURE_BOOT_H +#define __FSL_SECURE_BOOT_H + +/* Starting TLB number for the TLB entried for 3.5 G space created by ISBC */ +#if defined(CONFIG_FSL_CORENET) +#define CONFIG_SYS_ISBC_START_TLB 3 +#else +#define CONFIG_SYS_ISBC_START_TLB 0 +#endif + +/* Number fo TLB's created by ISBC */ +#define CONFIG_SYS_ISBC_NUM_TLBS 5 + +#if defined(CONFIG_FSL_CORENET) +#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#else +#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 +#endif +#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 + +#endif diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h new file mode 100644 index 0000000..8de37c9 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_tgec.h @@ -0,0 +1,215 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TGEC_H__ +#define __TGEC_H__ + +#include <phy.h> + +struct tgec { + /* 10GEC general control and status registers */ + u32 tgec_id; /* Controller ID register */ + u32 res0; + u32 command_config; /* Control and configuration register */ + u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ + u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ + u32 maxfrm; /* Maximum frame length register */ + u32 pause_quant; /* Pause quanta register */ + u32 res1[4]; + u32 hashtable_ctrl; /* Hash table control register */ + u32 res2[4]; + u32 status; /* MAC status register */ + u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ + u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */ + u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */ + u32 res3[4]; + u32 imask; /* Interrupt mask register */ + u32 ievent; /* Interrupt event register */ + u32 res4[6]; + /* 10GEC statistics counter registers */ + u32 tx_frame_u; /* Tx frame counter upper */ + u32 tx_frame_l; /* Tx frame counter lower */ + u32 rx_frame_u; /* Rx frame counter upper */ + u32 rx_frame_l; /* Rx frame counter lower */ + u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ + u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ + u32 rx_align_err_u; /* Rx alignment error upper */ + u32 rx_align_err_l; /* Rx alignment error lower */ + u32 tx_pause_frame_u; /* Tx valid pause frame upper */ + u32 tx_pause_frame_l; /* Tx valid pause frame lower */ + u32 rx_pause_frame_u; /* Rx valid pause frame upper */ + u32 rx_pause_frame_l; /* Rx valid pause frame upper */ + u32 rx_long_err_u; /* Rx too long frame error upper */ + u32 rx_long_err_l; /* Rx too long frame error lower */ + u32 rx_frame_err_u; /* Rx frame length error upper */ + u32 rx_frame_err_l; /* Rx frame length error lower */ + u32 tx_vlan_u; /* Tx VLAN frame upper */ + u32 tx_vlan_l; /* Tx VLAN frame lower */ + u32 rx_vlan_u; /* Rx VLAN frame upper */ + u32 rx_vlan_l; /* Rx VLAN frame lower */ + u32 tx_oct_u; /* Tx octets upper */ + u32 tx_oct_l; /* Tx octets lower */ + u32 rx_oct_u; /* Rx octets upper */ + u32 rx_oct_l; /* Rx octets lower */ + u32 rx_uni_u; /* Rx unicast frame upper */ + u32 rx_uni_l; /* Rx unicast frame lower */ + u32 rx_multi_u; /* Rx multicast frame upper */ + u32 rx_multi_l; /* Rx multicast frame lower */ + u32 rx_brd_u; /* Rx broadcast frame upper */ + u32 rx_brd_l; /* Rx broadcast frame lower */ + u32 tx_frame_err_u; /* Tx frame error upper */ + u32 tx_frame_err_l; /* Tx frame error lower */ + u32 tx_uni_u; /* Tx unicast frame upper */ + u32 tx_uni_l; /* Tx unicast frame lower */ + u32 tx_multi_u; /* Tx multicast frame upper */ + u32 tx_multi_l; /* Tx multicast frame lower */ + u32 tx_brd_u; /* Tx broadcast frame upper */ + u32 tx_brd_l; /* Tx broadcast frame lower */ + u32 rx_drop_u; /* Rx dropped packets upper */ + u32 rx_drop_l; /* Rx dropped packets lower */ + u32 rx_eoct_u; /* Rx ethernet octets upper */ + u32 rx_eoct_l; /* Rx ethernet octets lower */ + u32 rx_pkt_u; /* Rx packets upper */ + u32 rx_pkt_l; /* Rx packets lower */ + u32 tx_undsz_u; /* Undersized packet upper */ + u32 tx_undsz_l; /* Undersized packet lower */ + u32 rx_64_u; /* Rx 64 oct packet upper */ + u32 rx_64_l; /* Rx 64 oct packet lower */ + u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ + u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ + u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ + u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ + u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ + u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ + u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ + u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ + u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ + u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ + u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ + u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ + u32 tx_oversz_u; /* oversized packet upper */ + u32 tx_oversz_l; /* oversized packet lower */ + u32 tx_jabber_u; /* Jabber packet upper */ + u32 tx_jabber_l; /* Jabber packet lower */ + u32 tx_frag_u; /* Fragment packet upper */ + u32 tx_frag_l; /* Fragment packet lower */ + u32 rx_err_u; /* Rx frame error upper */ + u32 rx_err_l; /* Rx frame error lower */ + u32 res5[0x39a]; +}; + +/* EC10G_ID - 10-gigabit ethernet MAC controller ID */ +#define EC10G_ID_VER_MASK 0x0000ff00 +#define EC10G_ID_VER_SHIFT 8 +#define EC10G_ID_REV_MASK 0x000000ff + +/* COMMAND_CONFIG - command and configuration register */ +#define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */ +#define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */ +#define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */ +#define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */ +#define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */ +#define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */ +#define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */ +#define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */ +#define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */ +#define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */ +#define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */ +#define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */ +#define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */ +#define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */ +#define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ +#define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ +#define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN) + +/* HASHTABLE_CTRL - Hashtable control register */ +#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ +#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff + +/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ +#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff + +/* IMASK - interrupt mask register */ +#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ +#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ +#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ +#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ +#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ +#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ +#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ +#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ +#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ +#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ +#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ +#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ +#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ +#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ +#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ +#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ + +#define IMASK_MASK_ALL 0x00000000 + +/* IEVENT - interrupt event register */ +#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ +#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ +#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ +#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ +#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ +#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ +#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ +#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ +#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ +#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ +#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ +#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ +#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ +#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ +#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ +#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +struct tgec_mdio_controller { + u32 res0[0xc]; + u32 mdio_stat; /* MDIO configuration and status */ + u32 mdio_ctl; /* MDIO control */ + u32 mdio_data; /* MDIO data */ + u32 mdio_addr; /* MDIO address */ +}; + +#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) +#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_DATA(x) (x & 0xffff) +#define MDIO_DATA_BSY (1 << 31) + +struct fsl_enet_mac; + +void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index cc0293a..8d4c9cb 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2011 Freescale Semiconductor, Inc. * * MPC83xx Internal Memory Map * @@ -285,6 +285,105 @@ typedef struct qesba83xx { /* * DDR Memory Controller Memory Map */ +#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) +typedef struct ccsr_ddr { + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u8 res1[4]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u8 res2[4]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u8 res3[4]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u8 res4[100]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u8 res4a[48]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u8 res5[48]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u8 res6[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res7[20]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u8 res8_1[16]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u8 reg8_1a[8]; + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u8 reg8_1aa[4]; + u32 ddr_sr_cntr; /* self refresh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u8 reg_1ab[8]; + u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ + u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ + u8 res8_1b[104]; + u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ + u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ + u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ + u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ + u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ + u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ + u8 res8_1ba[0x908]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u8 res8_1c[200]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u32 eor; /* Enhanced Optimization Register */ + u8 res8_2[252]; + u32 mtcr; /* Memory Test Control Register */ + u8 res8_3[28]; + u32 mtp1; /* Memory Test Pattern 1 */ + u32 mtp2; /* Memory Test Pattern 2 */ + u32 mtp3; /* Memory Test Pattern 3 */ + u32 mtp4; /* Memory Test Pattern 4 */ + u32 mtp5; /* Memory Test Pattern 5 */ + u32 mtp6; /* Memory Test Pattern 6 */ + u32 mtp7; /* Memory Test Pattern 7 */ + u32 mtp8; /* Memory Test Pattern 8 */ + u32 mtp9; /* Memory Test Pattern 9 */ + u32 mtp10; /* Memory Test Pattern 10 */ + u8 res8_4[184]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u8 res9[20]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u8 res10[20]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u8 res11[164]; + u32 debug[32]; /* debug_1 to debug_32 */ + u8 res12[128]; +} ccsr_ddr_t; +#else typedef struct ddr_cs_bnds { u32 csbnds; u8 res0[4]; @@ -334,6 +433,7 @@ typedef struct ddr83xx { u32 debug_reg; u8 res9[0xFC]; } ddr83xx_t; +#endif /* * DUART @@ -641,7 +741,11 @@ typedef struct immap { u8 dll_ddr[0x100]; u8 dll_lbc[0x100]; u8 res1[0xE00]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ +#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) + ccsr_ddr_t ddr; /* DDR Memory Controller Memory */ +#else + ddr83xx_t ddr; /* DDR Memory Controller Memory */ +#endif fsl_i2c_t i2c[2]; /* I2C Controllers */ u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ @@ -869,10 +973,15 @@ typedef struct immap { } immap_t; #endif +#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC83xx_DDR_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET) #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) -#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) +#define CONFIG_SYS_MPC83xx_DMA_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) -#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6aaade0..fb5ef91 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1700,12 +1700,34 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ -#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 -#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 +#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060) +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 +#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ -#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 -#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 -#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 +#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 +#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 +#endif +#if defined(CONFIG_PPC_P3060) +#define FSL_CORENET_RCWSR13_EC1_EXT 0x1c000000 +#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII 0x04000000 +#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_EXT 0x01c00000 +#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII 0x00400000 +#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII 0x00800000 +#define FSL_CORENET_RCWSR13_EC3 0x00380000 +#define FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII 0x00100000 +#endif +#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \ + || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 +#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ +#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 +#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 +#endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -1873,6 +1895,7 @@ typedef struct ccsr_gur { #if defined(CONFIG_P1017) || defined(CONFIG_P1023) #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 +#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 #else #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 @@ -1971,6 +1994,9 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 #endif +#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PMUXCR_TSEC1_1 0x10000000 +#else #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 @@ -1989,6 +2015,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE10 0x00000020 #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 +#endif #if defined(CONFIG_P1013) || defined(CONFIG_P1022) #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 #define MPC85xx_PMUXCR_TDM 0x00014800 @@ -2301,6 +2328,22 @@ typedef struct ccsr_usb_phy { } ccsr_usb_phy_t; #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct ccsr_raide { + u8 res0[0x543]; + u32 liodnbr; /* LIODN Base Register */ + u8 res1[0xab8]; + struct { + struct { + u32 cfg0; /* cfg register 0 */ + u32 cfg1; /* cfg register 1 */ + u8 res1[0x3f8]; + } ring[2]; + u8 res[0x800]; + } jq[2]; +}; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2331,6 +2374,7 @@ typedef struct ccsr_usb_phy { #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2379,6 +2423,8 @@ typedef struct ccsr_usb_phy { #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 +#define CONFIG_SYS_SNVS_OFFSET 0xE6000 +#define CONFIG_SYS_SFP_OFFSET 0xE7000 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 @@ -2399,6 +2445,8 @@ typedef struct ccsr_usb_phy { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) +#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 0c4cc25..1b96b84 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1022,7 +1022,11 @@ #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ +#ifdef CONFIG_MPC8536 +#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/ +#else #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#endif #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ @@ -1111,6 +1115,8 @@ #define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 #define SVR_P3041_E 0x821903 +#define SVR_P3060 0x820002 +#define SVR_P3060_E 0x820802 #define SVR_P4040 0x820100 #define SVR_P4040_E 0x820900 #define SVR_P4080 0x820000 @@ -1176,13 +1182,17 @@ struct cpu_type { char name[15]; u32 soc_ver; u32 num_cores; + u32 mask; /* which cpu(s) actually exist */ }; struct cpu_type *identify_cpu(u32 ver); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ - { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \ + .mask = (1 << (nc)) - 1 } +#define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) } #else #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index c47d10d..b27f054 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -31,6 +31,7 @@ LIB = $(obj)libfreescale.o COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o COBJS-$(CONFIG_FSL_VIA) += cds_via.o +COBJS-$(CONFIG_FMAN_ENET) += fman.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o @@ -52,12 +53,22 @@ COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o +# deal with common files for P-series corenet based devices +SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) +SUBLIB := $(addprefix $(obj),$(SUBLIB-y)) + +$(LIB): $(obj).depend $(OBJS) $(SUBLIB) + $(call cmd_link_o_target, $(OBJS) $(SUBLIB)) -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +$(SUBLIB): $(obj).depend + $(MAKE) -C $(dir $(subst $(obj),,$@)) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index db54bc4..50b6e9f 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -61,12 +61,12 @@ get_clock_freq(void) uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ if (pci1_speed == 0) { - return 33000000; + return 33333333; } else if (pci1_speed == 1) { - return 66000000; + return 66666666; } else { /* Really, unknown. Be safe? */ - return 33000000; + return 33333333; } } diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c new file mode 100644 index 0000000..8a55fde --- /dev/null +++ b/board/freescale/common/fman.c @@ -0,0 +1,67 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <libfdt_env.h> +#include <fdt_support.h> + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) The name of an alias that points to the ethernet-phy node (usually inside + * a virtual MDIO node) + * + * ... update that Ethernet node's phy-handle property to point to the + * ethernet-phy node. This is how we link an Ethernet node to its PHY, so each + * PHY in a virtual MDIO node must have an alias. + */ +void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, + const char *alias) +{ + int offset, ph; + const char *path; + + /* Get a path to the node that 'alias' points to */ + path = fdt_get_alias(fdt, alias); + if (path) { + /* Get the offset of that node */ + int off = fdt_path_offset(fdt, path); + if (off > 0) + ph = fdt_create_phandle(fdt, off); + else + return; + } else { + return ; + } + + /* failed to create a phandle */ + if (ph <= 0) + return ; + + offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); + if (offset > 0) + fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); +} diff --git a/board/freescale/p2041rdb/pci.c b/board/freescale/common/fman.h index 1ab4cdf..19ef7c4 100644 --- a/board/freescale/p2041rdb/pci.c +++ b/board/freescale/common/fman.h @@ -1,9 +1,6 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -20,20 +17,10 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> +#ifndef __FMAN_BOARD_HELPER__ +#define __FMAN_BOARD_HELPER__ -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} +void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, + const char *alias); -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} +#endif diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile new file mode 100644 index 0000000..a76f590 --- /dev/null +++ b/board/freescale/common/p_corenet/Makefile @@ -0,0 +1,31 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = libp_corenet.o + +COBJS-y += law.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-y += tlb.o + +include $(TOPDIR)/post/rules.mk diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/common/p_corenet/law.c index 58f23c5..09ef561 100644 --- a/board/freescale/corenet_ds/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -35,7 +35,12 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), #endif +#ifdef PIXIS_BASE_PHYS SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#endif +#ifdef CPLD_BASE_PHYS + SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/common/p_corenet/pci.c index 18a75de..18a75de 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/common/p_corenet/pci.c diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/common/p_corenet/tlb.c index 2ce7004..6a0026a 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -30,24 +30,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), +#ifdef CPLD_BASE + SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), +#endif +#ifdef PIXIS_BASE SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 0), +#endif /* TLB 1 */ /* *I*** - Covers boot page */ @@ -67,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ @@ -78,47 +85,47 @@ struct fsl_e_tlb_entry tlb_table[] = { /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ #ifdef CONFIG_SYS_BMAN_MEM_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_1M, 1), #endif #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_1M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_1M, 1), #endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 69e81a4..7e33007 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -28,12 +28,12 @@ LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o COBJS-y += ddr.o +COBJS-$(CONFIG_P3041DS) += eth_hydra.o +COBJS-$(CONFIG_P4080DS) += eth_p4080.o +COBJS-$(CONFIG_P5020DS) += eth_hydra.o COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o -COBJS-$(CONFIG_PCI) += pci.o -COBJS-y += law.o -COBJS-y += tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index b1e7823..b1eecc4 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -32,10 +32,10 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> - -extern void pci_of_setup(void *blob, bd_t *bd); +#include <fm_eth.h> #include "../common/ngpixis.h" +#include "corenet_ds.h" DECLARE_GLOBAL_DATA_PTR; @@ -237,9 +237,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_liodn(blob); fdt_fixup_dr_usb(blob, bd); -} -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif } diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h new file mode 100644 index 0000000..9cdd47d --- /dev/null +++ b/board/freescale/corenet_ds/corenet_ds.h @@ -0,0 +1,26 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index b937015..3b4dfa3 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -118,53 +118,111 @@ typedef struct { u32 force_2T; } board_specific_parameters_t; -/* ranges for parameters: - * wr_data_delay = 0-6 - * clk adjust = 0-8 - * cpo 2-0x1E (30) - */ - - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][30] = { +const board_specific_parameters_t board_specific_parameters_udimm[][30] = { { /* * memory controller 0 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * mhz| mhz|ranks|adjst| start | |delay | */ { 0, 850, 4, 4, 6, 0xff, 2, 0}, {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, { 0, 850, 2, 5, 6, 0xff, 2, 0}, {851, 950, 2, 5, 7, 0xff, 2, 0}, {951, 1050, 2, 5, 7, 0xff, 2, 0}, {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + {1351, 1666, 2, 5, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, }, { /* * memory controller 1 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * mhz| mhz|ranks|adjst| start | |delay | */ { 0, 850, 4, 4, 6, 0xff, 2, 0}, {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, { 0, 850, 2, 5, 6, 0xff, 2, 0}, {851, 950, 2, 5, 7, 0xff, 2, 0}, {951, 1050, 2, 5, 7, 0xff, 2, 0}, {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + {1351, 1666, 2, 5, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, + } +}; + +const board_specific_parameters_t board_specific_parameters_rdimm[][30] = { + { + /* + * memory controller 0 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | |delay | + */ + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, + { 0, 850, 2, 4, 6, 0xff, 2, 0}, + {851, 950, 2, 4, 7, 0xff, 2, 0}, + {951, 1050, 2, 4, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 8, 0xff, 2, 0}, + {1251, 1350, 2, 4, 8, 0xff, 2, 0}, + {1351, 1666, 2, 4, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, + }, + + { + /* + * memory controller 1 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | |delay | + */ + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, + { 0, 850, 2, 4, 6, 0xff, 2, 0}, + {851, 950, 2, 4, 7, 0xff, 2, 0}, + {951, 1050, 2, 4, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 8, 0xff, 2, 0}, + {1251, 1350, 2, 4, 8, 0xff, 2, 0}, + {1351, 1666, 2, 4, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, } }; @@ -172,13 +230,20 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp = - &(board_specific_parameters[ctrl_num][0]); - u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / - sizeof(board_specific_parameters[0][0]); + const board_specific_parameters_t *pbsp; + u32 num_params; u32 i; ulong ddr_freq; + if (popts->registered_dimm_en) { + pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]); + num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) / + sizeof(board_specific_parameters_rdimm[0][0]); + } else { + pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); + num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / + sizeof(board_specific_parameters_udimm[0][0]); + } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ @@ -223,20 +288,6 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* DHC_EN =1, ODT = 60 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN; - - /* override SPD values. rcw_2 should vary at differnt speed */ - if (pdimm[0].registered_dimm == 1) { - popts->rcw_override = 1; - popts->rcw_1 = 0x000a5a00; - if (ddr_freq <= 800) - popts->rcw_2 = 0x00000000; - else if (ddr_freq <= 1066) - popts->rcw_2 = 0x00100000; - else if (ddr_freq <= 1333) - popts->rcw_2 = 0x00200000; - else - popts->rcw_2 = 0x00300000; - } } phys_size_t initdram(int board_type) diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c new file mode 100644 index 0000000..91b3408 --- /dev/null +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -0,0 +1,553 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Author: Timur Tabi <timur@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the board muxing between the Fman Ethernet MACs and + * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference + * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are + * provided by the standard Freescale four-port SGMII riser card. The 10Gb + * XGMII PHY is provided via the XAUI riser card. Since there is only one + * Fman device on a P3041 and P5020, we only support one SGMII card and one + * RGMII card. + * + * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control + * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is + * always the same (0). The value for SGMII depends on which slot the riser is + * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, + * the value is based on which slot the XAUI is inserted in. + * + * The SERDES configuration is used to determine where the SGMII and XAUI cards + * exist, and also which Fman MACs are routed to which PHYs. So for a given + * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed + * to PHYs dynamically. + * + * + * This file also updates the device tree in three ways: + * + * 1) The status of each virtual MDIO node that is referenced by an Ethernet + * node is set to "okay". + * + * 2) The phy-handle property of each active Ethernet MAC node is set to the + * appropriate PHY node. + * + * 3) The "mux value" for each virtual MDIO node is set to the correct value, + * if necessary. Some virtual MDIO nodes do not have configurable mux + * values, so those values are hard-coded in the DTS. On the HYDRA board, + * the virtual MDIO node for the SGMII card needs to be updated. + * + * For all this to work, the device tree needs to have the following: + * + * 1) An alias for each PHY node that an Ethernet node could be routed to. + * + * 2) An alias for each real and virtual MDIO node that is disabled by default + * and might need to be enabled, and also might need to have its mux-value + * updated. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/fsl_serdes.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <asm/fsl_dtsec.h> + +#include "../common/ngpixis.h" +#include "../common/fman.h" + +#ifdef CONFIG_FMAN_ENET + +#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_SLOT1 0x10 +#define BRDCFG1_EMI1_SEL_SLOT2 0x20 +#define BRDCFG1_EMI1_SEL_SLOT5 0x30 +#define BRDCFG1_EMI1_SEL_SLOT6 0x40 +#define BRDCFG1_EMI1_SEL_SLOT7 0x50 +#define BRDCFG1_EMI1_SEL_RGMII 0x00 +#define BRDCFG1_EMI1_EN 0x08 +#define BRDCFG1_EMI2_SEL_MASK 0x06 +#define BRDCFG1_EMI2_SEL_SLOT1 0x00 +#define BRDCFG1_EMI2_SEL_SLOT2 0x02 + +#define BRDCFG2_REG_GPIO_SEL 0x20 + +/* + * BRDCFG1 mask and value for each MAC + * + * This array contains the BRDCFG1 values (in mask/val format) that route the + * MDIO bus to a particular RGMII or SGMII PHY. + */ +struct { + u8 mask; + u8 val; +} mdio_mux[NUM_FM_PORTS]; + +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 +}; + +/* + * Set the board muxing for a given MAC + * + * The MDIO layer calls this function every time it wants to talk to a PHY. + */ +void hydra_mux_mdio(u8 mask, u8 val) +{ + clrsetbits_8(&pixis->brdcfg1, mask, val); +} + +struct hydra_mdio { + u8 mask; + u8 val; + struct mii_dev *realbus; +}; + +static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct hydra_mdio *priv = bus->priv; + + hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct hydra_mdio *priv = bus->priv; + + hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int hydra_mdio_reset(struct mii_dev *bus) +{ + struct hydra_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) +{ + struct mii_dev *bus = miiphy_get_dev_by_name(name); + struct hydra_mdio *priv = bus->priv; + + priv->mask = mask; + priv->val = val; +} + +static int hydra_mdio_init(char *realbusname, char *fakebusname) +{ + struct hydra_mdio *hmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate Hydra MDIO bus\n"); + return -1; + } + + hmdio = malloc(sizeof(*hmdio)); + if (!hmdio) { + printf("Failed to allocate Hydra private data\n"); + free(bus); + return -1; + } + + bus->read = hydra_mdio_read; + bus->write = hydra_mdio_write; + bus->reset = hydra_mdio_reset; + sprintf(bus->name, fakebusname); + + hmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!hmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(hmdio); + return -1; + } + + bus->priv = hmdio; + + return mdio_register(bus); +} + +/* + * Given an alias or a path for a node, set the status of that node. + * + * If 'alias' is not a valid alias, then it is treated as a full path to the + * node. No error checking is performed. + * + * This function is normally called to set the status for a virtual MDIO node. + */ +static void fdt_set_node_status(void *fdt, const char *alias, + const char *status) +{ + const char *path = fdt_get_alias(fdt, alias); + + if (!path) + path = alias; + + do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); +} + +/* + * Given an alias or a path for a node, set the mux value of that node. + * + * If 'alias' is not a valid alias, then it is treated as a full path to the + * node. No error checking is performed. + * + * This function is normally called to set the fsl,hydra-mdio-muxval property + * of a virtual MDIO node. + */ +static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) +{ + const char *path = fdt_get_alias(fdt, alias); + + if (!path) + path = alias; + + do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", + &mux, sizeof(mux), 1); +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. That + * information is stored in mdio_mux[]. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + * Note that this code would be cleaner if had a function called + * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] + * array. That's because all we're doing is figuring out the PHY address for + * a given Fman MAC and writing it to the device tree. Well, we already did + * the hard work to figure that out in board_eth_init(), so it's silly to + * repeat that here. + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; + char phy[16]; + + if (port == FM1_10GEC1) { + /* XAUI */ + int lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + /* The XAUI PHY is identified by the slot */ + sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + return; + } + + if (mux == BRDCFG1_EMI1_SEL_RGMII) { + /* RGMII */ + /* The RGMII PHY is identified by the MAC connected to it */ + sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* If it's not RGMII or XGMII, it must be SGMII */ + if (mux) { + /* The SGMII PHY is identified by the MAC connected to it */ + sprintf(phy, "phy_sgmii_%x", + CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } +} + +#define PIXIS_SW2_LANE_23_SEL 0x80 +#define PIXIS_SW2_LANE_45_SEL 0x40 +#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 +#define PIXIS_SW2_LANE_67_SEL_5 0x00 +#define PIXIS_SW2_LANE_67_SEL_6 0x20 +#define PIXIS_SW2_LANE_67_SEL_7 0x10 +#define PIXIS_SW2_LANE_8_SEL 0x08 +#define PIXIS_SW2_LANE_1617_SEL 0x04 + +/* + * Initialize the lane_to_slot[] array. + * + * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board + * slots is hard-coded. On the Hydra board, however, the mapping is controlled + * by board switch SW2, so the lane_to_slot[] array needs to be dynamically + * initialized. + */ +static void initialize_lane_to_slot(void) +{ + u8 sw2 = in_8(&PIXIS_SW(2)); + + lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; + lane_to_slot[3] = lane_to_slot[2]; + + lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; + lane_to_slot[5] = lane_to_slot[4]; + + switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { + case PIXIS_SW2_LANE_67_SEL_5: + lane_to_slot[6] = 5; + break; + case PIXIS_SW2_LANE_67_SEL_6: + lane_to_slot[6] = 6; + break; + case PIXIS_SW2_LANE_67_SEL_7: + lane_to_slot[6] = 7; + break; + } + lane_to_slot[7] = lane_to_slot[6]; + + lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; + + lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; + lane_to_slot[17] = lane_to_slot[16]; +} + +#endif /* #ifdef CONFIG_FMAN_ENET */ + +/* + * Configure the status for the virtual MDIO nodes + * + * Rather than create the virtual MDIO nodes from scratch for each active + * virtual MDIO, we expect the DTS to have the nodes defined already, and we + * only enable the ones that are actually active. + * + * We assume that the DTS already hard-codes the status for all the + * virtual MDIO nodes to "disabled", so all we need to do is enable the + * active ones. + * + * For SGMII, we also need to set the mux value in the node. + */ +void fdt_fixup_board_enet(void *fdt) +{ +#ifdef CONFIG_FMAN_ENET + unsigned int i; + int lane; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane >= 0) { + fdt_set_node_status(fdt, "emi1_sgmii", "okay"); + /* Also set the MUX value */ + fdt_set_mdio_mux(fdt, "emi1_sgmii", + mdio_mux[i].val); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_set_node_status(fdt, "emi1_rgmii", "okay"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) + fdt_set_node_status(fdt, "emi2_xgmii", "okay"); +#endif +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + unsigned int i, slot; + int lane; + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ + setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); + + memset(mdio_mux, 0, sizeof(mdio_mux)); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* Register the three virtual MDIO front-ends */ + hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); + hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); + + /* + * Program the DTSEC PHY addresses assuming that they are all SGMII. + * For any DTSEC that's RGMII, we'll override its PHY address later. + * We assume that DTSEC5 is only used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + switch (slot) { + case 1: + /* Always DTSEC5 on Bank 3 */ + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + hydra_mdio_set_mux("HYDRA_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * If DTSEC4 is RGMII, then it's routed via via EC1 to + * the first on-board RGMII port. If DTSEC5 is RGMII, + * then it's routed via via EC2 to the second on-board + * RGMII port. The other DTSECs cannot be routed to + * RGMII. + */ + fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + hydra_mdio_set_mux("HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + slot = lane_to_slot[lane]; + if (slot == 1) { + /* XAUI card is in slot 1 */ + clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, + BRDCFG1_EMI2_SEL_SLOT1); + fm_info_set_phy_address(FM1_10GEC1, + CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + } else { + /* XAUI card is in slot 2 */ + clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, + BRDCFG1_EMI2_SEL_SLOT2); + fm_info_set_phy_address(FM1_10GEC1, + CONFIG_SYS_FM2_10GEC1_PHY_ADDR); + } + } + + fm_info_set_mdio(FM1_10GEC1, + miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c new file mode 100644 index 0000000..d4657f7 --- /dev/null +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -0,0 +1,506 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> + +#include "../common/ngpixis.h" +#include "../common/fman.h" +#include <asm/fsl_dtsec.h> + +#define EMI_NONE 0xffffffff +#define EMI_MASK 0xf0000000 +#define EMI1_RGMII 0x0 +#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ +#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ +#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ +#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ +#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ +#define EMI1_MASK 0xc0000000 +#define EMI2_MASK 0x30000000 + +static int mdio_mux[NUM_FM_PORTS]; + +static char *mdio_names[16] = { + "P4080DS_MDIO0", + "P4080DS_MDIO1", + NULL, + "P4080DS_MDIO3", + "P4080DS_MDIO4", + NULL, NULL, NULL, + "P4080DS_MDIO8", + NULL, NULL, NULL, + "P4080DS_MDIO12", + NULL, NULL, NULL, +}; + +static char *p4080ds_mdio_name_for_muxval(u32 muxval) +{ + return mdio_names[(muxval & EMI_MASK) >> 28]; +} + +struct mii_dev *mii_dev_for_muxval(u32 muxval) +{ + struct mii_dev *bus; + char *name = p4080ds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +int board_phy_config(struct phy_device *phydev) +{ + /* + * If this is the 10G PHY, and we switched it to fiber, + * we need to reset the serdes link for SERDES9 + */ + if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) { + enum srds_prtcl device; + + switch (phydev->addr) { + case 4: + device = XAUI_FM1; + break; + case 0: + device = XAUI_FM2; + break; + default: + device = NONE; + } + + serdes_reset_rx(device); + } + + return 0; +} +#endif + +struct p4080ds_mdio { + u32 muxval; + struct mii_dev *realbus; +}; + +static void p4080ds_mux_mdio(u32 muxval) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); + gpioval |= muxval; + + out_be32(&pgpio->gpdat, gpioval); +} + +static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct p4080ds_mdio *priv = bus->priv; + + p4080ds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct p4080ds_mdio *priv = bus->priv; + + p4080ds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int p4080ds_mdio_reset(struct mii_dev *bus) +{ + struct p4080ds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int p4080ds_mdio_init(char *realbusname, u32 muxval) +{ + struct p4080ds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate P4080DS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate P4080DS private data\n"); + free(bus); + return -1; + } + + bus->read = p4080ds_mdio_read; + bus->write = p4080ds_mdio_write; + bus->reset = p4080ds_mdio_reset; + sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Sets the specified node's status to the value contained in "status" + * If the first character of the specified path is "/" then we use + * alias as a path. Otherwise, we look for an alias of that name + */ +static void fdt_set_node_status(void *fdt, const char *alias, + const char *status) +{ + const char *path = fdt_get_alias(fdt, alias); + + if (!path) + path = alias; + + do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + if (mdio_mux[port] == EMI1_RGMII) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); + + if (mdio_mux[port] == EMI1_SLOT3) { + int idx = port - FM2_DTSEC1 + 5; + char phy[16]; + + sprintf(phy, "phy%d_slot3", idx); + + fdt_set_phy_handle(blob, prop, pa, phy); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + + /* + * P4080DS can be configured in many different ways, supporting a number + * of combinations of ethernet devices and phy types. In order to + * have just one device tree for all of those configurations, we fix up + * the tree here. By default, the device tree configures FM1 and FM2 + * for SGMII, and configures XAUI on both 10G interfaces. So we have + * a number of different variables to track: + * + * 1) Whether the device is configured at all. Whichever devices are + * not enabled should be disabled by setting the "status" property + * to "disabled". + * 2) What the PHY interface is. If this is an RGMII connection, + * we should change the "phy-connection-type" property to + * "rgmii" + * 3) Which PHY is being used. Because the MDIO buses are muxed, + * we need to redirect the "phy-handle" property to point at the + * PHY on the right slot/bus. + */ + + /* We've got six MDIO nodes that may or may not need to exist */ + fdt_set_node_status(fdt, "emi1_slot3", "disabled"); + fdt_set_node_status(fdt, "emi1_slot4", "disabled"); + fdt_set_node_status(fdt, "emi1_slot5", "disabled"); + fdt_set_node_status(fdt, "emi2_slot4", "disabled"); + fdt_set_node_status(fdt, "emi2_slot5", "disabled"); + + for (i = 0; i < NUM_FM_PORTS; i++) { + switch (mdio_mux[i]) { + case EMI1_SLOT3: + fdt_set_node_status(fdt, "emi1_slot3", "okay"); + break; + case EMI1_SLOT4: + fdt_set_node_status(fdt, "emi1_slot4", "okay"); + break; + case EMI1_SLOT5: + fdt_set_node_status(fdt, "emi1_slot5", "okay"); + break; + case EMI2_SLOT4: + fdt_set_node_status(fdt, "emi2_slot4", "okay"); + break; + case EMI2_SLOT5: + fdt_set_node_status(fdt, "emi2_slot5", "okay"); + break; + } + } +} + +enum board_slots { + SLOT1 = 1, + SLOT2, + SLOT3, + SLOT4, + SLOT5, + SLOT6, +}; + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + int i; + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + + u8 lane_to_slot[] = { + SLOT1, /* 0 - Bank 1:A */ + SLOT1, /* 1 - Bank 1:B */ + SLOT2, /* 2 - Bank 1:C */ + SLOT2, /* 3 - Bank 1:D */ + SLOT3, /* 4 - Bank 1:E */ + SLOT3, /* 5 - Bank 1:F */ + SLOT3, /* 6 - Bank 1:G */ + SLOT3, /* 7 - Bank 1:H */ + SLOT6, /* 8 - Bank 1:I */ + SLOT6, /* 9 - Bank 1:J */ + SLOT4, /* 10 - Bank 2:A */ + SLOT4, /* 11 - Bank 2:B */ + SLOT4, /* 12 - Bank 2:C */ + SLOT4, /* 13 - Bank 2:D */ + SLOT5, /* 14 - Bank 3:A */ + SLOT5, /* 15 - Bank 3:B */ + SLOT5, /* 16 - Bank 3:C */ + SLOT5, /* 17 - Bank 3:D */ + }; + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + /* The first 4 GPIOs are outputs to control MDIO bus muxing */ + out_be32(&pgpio->gpdir, EMI_MASK); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* Register the 6 muxing front-ends to the MDIO buses */ + p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); + p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); + p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); + + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + +#if (CONFIG_SYS_NUM_FMAN == 2) + fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); +#endif + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case SLOT4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case SLOT5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + fm_info_set_phy_address(i, 0); + mdio_mux[i] = EMI1_RGMII; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + int idx = i - FM1_10GEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(XAUI_FM1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT4: + mdio_mux[i] = EMI2_SLOT4; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case SLOT5: + mdio_mux[i] = EMI2_SLOT5; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case SLOT4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case SLOT5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + fm_info_set_phy_address(i, 0); + mdio_mux[i] = EMI1_RGMII; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + int idx = i - FM2_10GEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(XAUI_FM2 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT4: + mdio_mux[i] = EMI2_SLOT4; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case SLOT5: + mdio_mux[i] = EMI2_SLOT5; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + default: + break; + } + } +#endif + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index 4f76eab..601c3bf 100644 --- a/board/freescale/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_FSL_DDR2) += ddr.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c new file mode 100644 index 0000000..0209c1e --- /dev/null +++ b/board/freescale/mpc8349emds/ddr.c @@ -0,0 +1,107 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +struct board_specific_parameters { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +const struct board_specific_parameters board_specific_parameters_udimm[][20] = { + { + /* + * memory controller 0 + * lo| hi| num| clk| cpo|wrdata|2T + * mhz| mhz|ranks|adjst| | delay| + */ + { 0, 300, 2, 4, 4, 2, 0}, + {301, 365, 2, 4, 6, 2, 0}, + {366, 450, 2, 4, 7, 2, 0}, + {451, 850, 2, 4, 31, 2, 0}, + { 0, 300, 1, 4, 4, 2, 0}, + {301, 365, 1, 4, 6, 2, 0}, + {366, 450, 1, 4, 7, 2, 0}, + {451, 850, 1, 4, 31, 2, 0} + } +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp; + u32 num_params; + u32 i, dimm_num; + ulong ddr_freq; + + if (ctrl_num != 0) /* we have only one controller */ + return; + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (pdimm[i].n_ranks) + break; + } + if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ + return; + + dimm_num = i; + pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); + num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / + sizeof(board_specific_parameters_udimm[0][0]); + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm[dimm_num].n_ranks == pbsp->n_ranks) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + break; + } + pbsp++; + } + + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + popts->DQS_config = 0; /* only true DQS signal is used on board */ +} diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 365ac37..620540f 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -29,7 +29,11 @@ #include <i2c.h> #include <spi.h> #include <miiphy.h> +#ifdef CONFIG_FSL_DDR2 +#include <asm/fsl_ddr_sdram.h> +#else #include <spd_sdram.h> +#endif #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> @@ -62,7 +66,7 @@ int board_early_init_f (void) phys_size_t initdram (int board_type) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; + phys_size_t msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; @@ -70,24 +74,24 @@ phys_size_t initdram (int board_type) /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); +#ifndef CONFIG_FSL_DDR2 + msize = spd_sdram() * 1024 * 1024; +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + ddr_enable_ecc(msize); +#endif +#else + msize = fsl_ddr_sdram(); +#endif #else - msize = fixed_sdram(); + msize = fixed_sdram() * 1024 * 1024; #endif /* * Initialize SDRAM if it is on local bus. */ sdram_init(); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); + return msize; } #if !defined(CONFIG_SPD_EEPROM) diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 0d3752d..d127137 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -200,6 +200,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char buf[32]; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -222,8 +223,7 @@ int checkboard (void) printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", + strmhz(buf, pci1_speed), pci1_clk_sel ? "sync" : "async"); if (pci_dual) { diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 5ffae47..3bcaac4 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -30,7 +30,6 @@ #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_serdes.h> -#include <spd_sdram.h> #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> @@ -39,8 +38,6 @@ #include "../common/eeprom.h" #include "../common/via.h" -DECLARE_GLOBAL_DATA_PTR; - void local_bus_init(void); int checkboard (void) @@ -123,7 +120,7 @@ void lbc_sdram_init(void) puts("LBC SDRAM: "); print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); + "\n"); /* * Setup SDRAM Base and Option Registers @@ -210,10 +207,6 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ - void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -221,6 +214,7 @@ void pci_init_board(void) u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; + char buf[32]; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); @@ -243,10 +237,9 @@ void pci_init_board(void) law_size_bits(pci_info.io_size), pci_info.law); pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", + strmhz(buf, pci_speed), pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", @@ -268,7 +261,7 @@ void pci_init_board(void) } #endif } else { - printf("PCI: disabled\n"); + printf("PCI1: disabled\n"); } puts("\n"); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 60d1758..48ede98 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -198,6 +198,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char buf[32]; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -220,8 +221,7 @@ int checkboard (void) printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", + strmhz(buf, pci1_speed), pci1_clk_sel ? "sync" : "async"); if (pci_dual) { diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile new file mode 100644 index 0000000..1dcd490 --- /dev/null +++ b/board/freescale/p1010rdb/Makefile @@ -0,0 +1,52 @@ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c new file mode 100644 index 0000000..e5d8423 --- /dev/null +++ b/board/freescale/p1010rdb/ddr.c @@ -0,0 +1,250 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DDR_RAW_TIMING +#define CONFIG_SYS_DRAM_SIZE 1024 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {607, 749, &ddr_cfg_regs_667}, + {0, 0, NULL} +}; + +unsigned long get_sdram_size(void) +{ + struct cpu_type *cpu; + phys_size_t ddr_size; + + cpu = gd->cpu; + /* P1014 and it's derivatives support max 16it DDR width */ + if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + ddr_size = (CONFIG_SYS_DRAM_SIZE / 2); + else + ddr_size = CONFIG_SYS_DRAM_SIZE; + + return ddr_size; +} + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + struct cpu_type *cpu; + +#if defined(CONFIG_SYS_RAMBOOT) + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + cpu = gd->cpu; + /* P1014 and it's derivatives support max 16bit DDR width */ + if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; + ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; + ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; + ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000; + } + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_DDR_RAW_TIMING */ +/* + * Samsung K4B2G0846C-HCF8 + * The following timing are for "downshift" + * i.e. to use CL9 part as CL7 + * otherwise, tAA, tRCD, tRP will be 13500ps + * and tRC will be 49500ps + */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1875, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct cpu_type *cpu; + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + cpu = gd->cpu; + /* P1014 and it's derivatives support max 16it DDR width */ + if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_DDR_RAW_TIMING */ diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c new file mode 100644 index 0000000..3ed77fc --- /dev/null +++ b/board/freescale/p1010rdb/law.c @@ -0,0 +1,35 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#ifndef CONFIG_SDCARD + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c new file mode 100644 index 0000000..03e9da1 --- /dev/null +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -0,0 +1,330 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <mmc.h> +#include <netdev.h> +#include <pci.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_ifc.h> +#include <asm/fsl_pci.h> + +#ifndef CONFIG_SDCARD +#include <hwconfig.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO4_PCIE_RESET_SET 0x08000000 +#define MUX_CPLD_CAN_UART 0x00 +#define MUX_CPLD_TDM 0x01 +#define MUX_CPLD_SPICS0_FLASH 0x00 +#define MUX_CPLD_SPICS0_SLIC 0x02 + +#ifndef CONFIG_SDCARD +struct cpld_data { + u8 cpld_ver; /* cpld revision */ + u8 pcba_ver; /* pcb revision number */ + u8 twindie_ddr3; + u8 res1[6]; + u8 bank_sel; /* NOR Flash bank */ + u8 res2[5]; + u8 usb2_sel; + u8 res3[1]; + u8 porsw_sel; + u8 tdm_can_sel; + u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ + u8 por0; /* POR Options */ + u8 por1; /* POR Options */ + u8 por2; /* POR Options */ + u8 por3; /* POR Options */ +}; + +void cpld_show(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("CPLD: V%x.%x PCBA: V%x.0\n", + in_8(&cpld_data->cpld_ver) & 0xF0, + in_8(&cpld_data->cpld_ver) & 0x0F, + in_8(&cpld_data->pcba_ver) & 0x0F); + +#ifdef CONFIG_DEBUG + printf("twindie_ddr =%x\n", + in_8(&cpld_data->twindie_ddr3)); + printf("bank_sel =%x\n", + in_8(&cpld_data->bank_sel)); + printf("usb2_sel =%x\n", + in_8(&cpld_data->usb2_sel)); + printf("porsw_sel =%x\n", + in_8(&cpld_data->porsw_sel)); + printf("tdm_can_sel =%x\n", + in_8(&cpld_data->tdm_can_sel)); + printf("tdm_can_sel =%x\n", + in_8(&cpld_data->tdm_can_sel)); + printf("spi_cs0_sel =%x\n", + in_8(&cpld_data->spi_cs0_sel)); + printf("bcsr0 =%x\n", + in_8(&cpld_data->bcsr0)); + printf("bcsr1 =%x\n", + in_8(&cpld_data->bcsr1)); + printf("bcsr2 =%x\n", + in_8(&cpld_data->bcsr2)); + printf("bcsr3 =%x\n", + in_8(&cpld_data->bcsr3)); +#endif +} +#endif + +int board_early_init_f(void) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); +#ifndef CONFIG_SDCARD + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); +#endif + /* + * Reset PCIe slots via GPIO4 + */ + setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); + setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); + + return 0; +} + +int board_early_init_r(void) +{ +#ifndef CONFIG_SDCARD + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_16M, 1); + + set_tlb(1, flashbase + 0x1000000, + CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); +#endif + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif /* ifdef CONFIG_PCI */ + +int checkboard(void) +{ + struct cpu_type *cpu; + + cpu = gd->cpu; + printf("Board: %sRDB ", cpu->name); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap)"); +#endif + puts("\n"); + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + struct cpu_type *cpu; + int num = 0; + + cpu = gd->cpu; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + /* P1014 and it's derivatives do not support eTSEC3 */ + if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) { + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; + } +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void fdt_del_flexcan(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,flexcan-v1.0")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_spi_flash(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "spansion,s25sl12801")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_spi_slic(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "zarlink,le88266")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_tdm(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,starlite-tdm")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + struct cpu_type *cpu; + + cpu = gd->cpu; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + FT_FSL_PCI_SETUP; +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); + + /* P1014 and it's derivatives don't support CAN and eTSEC3 */ + if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + fdt_del_flexcan(blob); + fdt_del_node_and_alias(blob, "ethernet2"); + } +#ifndef CONFIG_SDCARD + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { + printf("fdt CAN"); + fdt_del_tdm(blob); + fdt_del_spi_slic(blob); + } +#ifndef CONFIG_SPIFLASH + else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { + printf("fdt TDM"); + fdt_del_flexcan(blob); + fdt_del_spi_flash(blob); + } +#endif +#endif +} +#endif + +#ifndef CONFIG_SDCARD +int misc_init_r(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | + MPC85xx_PMUXCR_CAN1_UART | + MPC85xx_PMUXCR_CAN2_TDM | + MPC85xx_PMUXCR_CAN2_UART); + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + } +#ifndef CONFIG_SPIFLASH + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { + printf("TDM"); + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | + MPC85xx_PMUXCR_CAN1_UART); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | + MPC85xx_PMUXCR_CAN1_TDM); + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + } +#endif + return 0; +} +#endif diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c new file mode 100644 index 0000000..4256bf4 --- /dev/null +++ b/board/freescale/p1010rdb/tlb.c @@ -0,0 +1,98 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SDCARD + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, + CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 3, BOOKE_PAGESZ_16M, 1), +#endif + +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +#endif +#endif + +#ifndef CONFIG_SDCARD + /* *I*G - Board CPLD */ + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +#endif + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 8cfd199..546819c 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -38,6 +38,11 @@ #include <fdt_support.h> #include <netdev.h> #include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> #include "bcsr.h" @@ -143,6 +148,39 @@ unsigned long get_board_ddr_clk(ulong dummy) int board_eth_init(bd_t *bis) { + u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; + ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_pq_mdio_info dtsec_mdio_info; + + /* + * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting + * is not correct. + */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + + fm_info_set_mdio(FM1_DTSEC1, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + fm_info_set_mdio(FM1_DTSEC2, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) + clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); + +#ifdef CONFIG_FMAN_ENET + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); } @@ -158,5 +196,7 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_fman_ethernet(blob); } #endif diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile new file mode 100644 index 0000000..8056af8 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -0,0 +1,52 @@ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c new file mode 100644 index 0000000..f0cbde7 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -0,0 +1,292 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +#ifdef CONFIG_DDR_RAW_TIMING +#if defined(CONFIG_P1020RDB_PROTO) || \ + defined(CONFIG_P1021RDB) || \ + defined(CONFIG_P1020UTM) +/* Micron MT41J256M8_187E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; +#elif defined(CONFIG_P2020RDB) +/* Micron MT41J128M16_15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 64, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1500, + .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ + .tAA_ps = 13500, + .tWR_ps = 15000, + .tRCD_ps = 13500, + .tRRD_ps = 6000, + .tRP_ps = 13500, + .tRAS_ps = 36000, + .tRC_ps = 49500, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 30000, +}; +#elif defined(CONFIG_P1020MBG) +/* Micron MT41J512M8_187E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 1073741824u, + .capacity = 2147483648u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; +#elif defined(CONFIG_P1020RDB) +/* + * Samsung K4B2G0846C-HCF8 + * The following timing are for "downshift" + * i.e. to use CL9 part as CL7 + * otherwise, tAA, tRCD, tRP will be 13500ps + * and tRC will be 49500ps + */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1875, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; +#elif defined(CONFIG_P1024RDB) || \ + defined(CONFIG_P1025RDB) +/* + * Samsung K4B2G0846C-HCH9 + * The following timing are for "downshift" + * i.e. to use CL9 part as CL7 + * otherwise, tAA, tRCD, tRP will be 13500ps + * and tRC will be 49500ps + */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1500, + .caslat_X = 0x3e << 4, /* 5,6,7,8,9 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 6000, + .tRP_ps = 13125, + .tRAS_ps = 36000, + .tRC_ps = 49125, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 30000, +}; +#else +#error Missing raw timing data for this board +#endif + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif /* CONFIG_DDR_RAW_TIMING */ + +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + size_t ddr_size; + fsl_ddr_cfg_regs_t ddr_cfg_regs = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, +#endif + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + }; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return ddr_size; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + if (pdimm->primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm->primary_sdram_width == 32) + popts->data_bus_width = 1; + else + printf("Error in DDR bus width configuration!\n"); + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/freescale/p2041rdb/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 127a478..5ff6ea6 100644 --- a/board/freescale/p2041rdb/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,12 +25,14 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), - SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_VSC7385_ENET + SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c new file mode 100644 index 0000000..4671128 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -0,0 +1,449 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <hwconfig.h> +#include <pci.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/io.h> +#include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> +#include <asm/mp.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <vsc7385.h> +#include <ioports.h> +#include <asm/fsl_serdes.h> +#include <netdev.h> + +#ifdef CONFIG_QE + +#define GPIO_GETH_SW_PORT 1 +#define GPIO_GETH_SW_PIN 29 +#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN)) + +#define GPIO_SLIC_PORT 1 +#define GPIO_SLIC_PIN 30 +#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) + + +#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) +#define PCA_IOPORT_I2C_ADDR 0x23 +#define PCA_IOPORT_OUTPUT_CMD 0x2 +#define PCA_IOPORT_CFG_CMD 0x6 +#define PCA_IOPORT_QE_PIN_ENABLE 0xf8 +#define PCA_IOPORT_QE_TDM_ENABLE 0xf6 +#endif + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GPIO */ + {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ +#if 0 + {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ +#endif + {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ + {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ + {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ + +#ifdef CONFIG_P1025RDB + /* QE_MUX_MDC */ + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ + + /* QE_MUX_MDIO */ + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ + + /* UCC_1_MII */ + {0, 23, 2, 0, 2}, /* CLK12 */ + {0, 24, 2, 0, 1}, /* CLK9 */ + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ + {0, 17, 2, 0, 2}, /* ENET1_CRS */ + {0, 16, 2, 0, 2}, /* ENET1_COL */ + + /* UCC_5_RMII */ + {1, 11, 2, 0, 1}, /* CLK13 */ + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ +#endif + + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + +struct cpld_data { + u8 cpld_rev_major; + u8 pcba_rev; + u8 wd_cfg; + u8 rst_bps_sw; + u8 load_default_n; + u8 rst_bps_wd; + u8 bypass_enable; + u8 bps_led; + u8 status_led; /* offset: 0x8 */ + u8 fxo_led; /* offset: 0x9 */ + u8 fxs_led; /* offset: 0xa */ + u8 rev4[2]; + u8 system_rst; /* offset: 0xd */ + u8 bps_out; + u8 rev5[3]; + u8 cpld_rev_minor; +}; + +#define CPLD_WD_CFG 0x03 +#define CPLD_RST_BSW 0x00 +#define CPLD_RST_BWD 0x00 +#define CPLD_BYPASS_EN 0x03 +#define CPLD_STATUS_LED 0x01 +#define CPLD_FXO_LED 0x01 +#define CPLD_FXS_LED 0x0F +#define CPLD_SYS_RST 0x00 + +void board_cpld_init(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); + out_8(&cpld_data->status_led, CPLD_STATUS_LED); + out_8(&cpld_data->fxo_led, CPLD_FXO_LED); + out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + out_8(&cpld_data->system_rst, CPLD_SYS_RST); +} + +void board_gpio_init(void) +{ +#ifdef CONFIG_QE + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + + /* Enable VSC7385 switch */ + setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); + + /* Enable SLIC */ + setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); +#else + + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + + /* + * GPIO10 DDR Reset, open drain + * GPIO7 LOAD_DEFAULT_N Input + * GPIO11 WDI (watchdog input) + * GPIO12 Ethernet Switch Reset + * GPIO13 SLIC Reset + */ + + setbits_be32(&pgpio->gpdir, 0x02130000); +#ifndef CONFIG_SYS_RAMBOOT + /* init DDR3 reset signal */ + setbits_be32(&pgpio->gpdir, 0x00200000); + setbits_be32(&pgpio->gpodr, 0x00200000); + clrbits_be32(&pgpio->gpdat, 0x00200000); + udelay(1000); + setbits_be32(&pgpio->gpdat, 0x00200000); + udelay(1000); + clrbits_be32(&pgpio->gpdir, 0x00200000); +#endif + +#ifdef CONFIG_VSC7385_ENET + /* reset VSC7385 Switch */ + setbits_be32(&pgpio->gpdir, 0x00080000); + setbits_be32(&pgpio->gpdat, 0x00080000); +#endif + +#ifdef CONFIG_SLIC + /* reset SLIC */ + setbits_be32(&pgpio->gpdir, 0x00040000); + setbits_be32(&pgpio->gpdat, 0x00040000); +#endif +#endif +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); + + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); + + board_gpio_init(); + board_cpld_init(); + + return 0; +} + +int checkboard(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 in, out, io_config, val; + + printf("Board: %s ", CONFIG_BOARDNAME); + +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + + printf("CPLD: V%d.%d PCBA: V%d.0\n", + in_8(&cpld_data->cpld_rev_major) & 0x0F, + in_8(&cpld_data->cpld_rev_minor) & 0x0F, + in_8(&cpld_data->pcba_rev) & 0x0F); + + /* Initialize i2c early for rom_loc and flash bank information */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || + i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + val = (in & io_config) | (out & (~io_config)); + + puts("rom_loc: "); + if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { + puts("sd"); +#ifdef __SW_BOOT_SPI + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { + puts("spi"); +#endif +#ifdef __SW_BOOT_NAND + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) { + puts("nand"); +#endif +#ifdef __SW_BOOT_PCIE + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) { + puts("pcie"); +#endif + } else { + if (val & 0x2) + puts("nor lower bank"); + else + puts("nor upper bank"); + } + puts("\n"); + + if (val & 0x1) { + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + puts("SD/MMC : 8-bit Mode\n"); + puts("eSPI : Disabled\n"); + } else { + puts("SD/MMC : 4-bit Mode\n"); + puts("eSPI : Enabled\n"); + } + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + ccsr_gur_t *gur __attribute__((unused)) = + (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; +#ifdef CONFIG_VSC7385_ENET + char *tmp; + unsigned int vscfw_addr; +#endif + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + printf("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + +#ifdef CONFIG_VSC7385_ENET + /* If a VSC7385 microcode image is present, then upload it. */ + if ((tmp = getenv("vscfw_addr")) != NULL) { + vscfw_addr = simple_strtoul(tmp, NULL, 16); + printf("uploading VSC7385 microcode from %x\n", vscfw_addr); + if (vsc7385_upload_firmware((void *) vscfw_addr, + CONFIG_VSC7385_IMAGE_SIZE)) + puts("Failure uploading VSC7385 microcode.\n"); + } else + puts("No address specified for VSC7385 microcode.\n"); +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + +#if defined(CONFIG_UEC_ETH) + /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); + + uec_standard_init(bis); +#endif + + return pci_eth_init(bis); +} + +#if defined(CONFIG_QE) && \ + (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)) +static void fdt_board_fixup_qe_pins(void *blob) +{ + unsigned int oldbus; + u8 val8; + int node; + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + if (hwconfig("qe")) { + /* For QE and eLBC pins multiplexing, + * there is a PCA9555 device on P1025RDB. + * It control the multiplex pins' functions, + * and setting the PCA9555 can switch the + * function between QE and eLBC. + */ + oldbus = i2c_get_bus_num(); + i2c_set_bus_num(0); + if (hwconfig("tdm")) + val8 = PCA_IOPORT_QE_TDM_ENABLE; + else + val8 = PCA_IOPORT_QE_PIN_ENABLE; + i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD, + 1, &val8, 1); + i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD, + 1, &val8, 1); + i2c_set_bus_num(oldbus); + /* if run QE TDM, Set ABSWP to implement + * conversion of addresses in the eLBC. + */ + if (hwconfig("tdm")) { + set_lbc_or(2, CONFIG_PMC_OR_PRELIM); + set_lbc_br(2, CONFIG_PMC_BR_PRELIM); + setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + } + } else { + node = fdt_path_offset(blob, "/qe"); + if (node >= 0) + fdt_del_node(blob, node); + } + + return; +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + FT_FSL_PCI_SETUP; + +#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) + fdt_board_fixup_qe_pins(blob); +#endif +#endif + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c new file mode 100644 index 0000000..6d22463 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -0,0 +1,114 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_NAND_SPL + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI memory 1.5G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O effective: 192K */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + +#ifdef CONFIG_VSC7385_ENET + /* *I*G - VSC7385 Switch */ + SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif + +#ifdef CONFIG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +#endif + +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC/eSPI/NAND boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), + +#ifdef CONFIG_P1020MBG + /* 2G DDR on P1020MBG, map the second 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_1G, 1), +#endif +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile index 65f348f..8d4da3a 100644 --- a/board/freescale/p2041rdb/Makefile +++ b/board/freescale/p2041rdb/Makefile @@ -29,9 +29,7 @@ LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o COBJS-y += cpld.o COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_PCI) += pci.o +COBJS-y += eth.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index 8e1f46e..a4bcc18 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -53,7 +53,11 @@ void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); */ void __cpld_set_altbank(void) { + u8 reg5 = CPLD_READ(sw_ctl_on); + + CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); CPLD_WRITE(fbank_sel, 1); + CPLD_WRITE(system_rst, 1); } void cpld_set_altbank(void) __attribute__((weak, alias("__cpld_set_altbank"))); @@ -61,12 +65,12 @@ void cpld_set_altbank(void) /** * Set the boot bank to the default bank */ -void __cpld_clear_altbank(void) +void __cpld_set_defbank(void) { - CPLD_WRITE(fbank_sel, 0); + CPLD_WRITE(system_rst_default, 1); } -void cpld_clear_altbank(void) - __attribute__((weak, alias("__cpld_clear_altbank"))); +void cpld_set_defbank(void) + __attribute__((weak, alias("__cpld_set_defbank"))); #ifdef DEBUG static void cpld_dump_regs(void) @@ -75,7 +79,6 @@ static void cpld_dump_regs(void) printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); - printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); @@ -92,7 +95,6 @@ static void cpld_dump_regs(void) int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; - unsigned int i; if (argc <= 1) return cmd_usage(cmdtp); @@ -101,16 +103,7 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strcmp(argv[2], "altbank") == 0) cpld_set_altbank(); else - cpld_clear_altbank(); - - cpld_reset(); - } else if (strcmp(argv[1], "watchdog") == 0) { - static char *period[8] = {"1ms", "10ms", "30ms", "disable", - "100ms", "1s", "10s", "60s"}; - for (i = 0; i < ARRAY_SIZE(period); i++) { - if (strcmp(argv[2], period[i]) == 0) - CPLD_WRITE(wd_cfg, i); - } + cpld_set_defbank(); } else if (strcmp(argv[1], "lane_mux") == 0) { u32 lane = simple_strtoul(argv[2], NULL, 16); u8 val = (u8)simple_strtoul(argv[3], NULL, 16); @@ -154,17 +147,15 @@ U_BOOT_CMD( "Reset the board or pin mulexing selection using the CPLD sequencer", "reset - hard reset to default bank\n" "cpld_cmd reset altbank - reset to alternate bank\n" - "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" - " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" - " lane 6: 0 -> slot1 (Default)\n" - " 1 -> SGMII\n" - " lane a: 0 -> slot2 (Default)\n" - " 1 -> AURORA\n" - " lane c: 0 -> slot2 (Default)\n" - " 1 -> SATA0\n" - " lane d: 0 -> slot2 (Default)\n" - " 1 -> SATA1\n" + " lane 6: 0 -> slot1\n" + " 1 -> SGMII (Default)\n" + " lane a: 0 -> slot2\n" + " 1 -> AURORA (Default)\n" + " lane c: 0 -> slot2\n" + " 1 -> SATA0 (Default)\n" + " lane d: 0 -> slot2\n" + " 1 -> SATA1 (Default)\n" #ifdef DEBUG "cpld_cmd dump - display the CPLD registers\n" #endif diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h index 3b24cb0..2e3e7b1 100644 --- a/board/freescale/p2041rdb/cpld.h +++ b/board/freescale/p2041rdb/cpld.h @@ -19,7 +19,7 @@ typedef struct cpld_data { u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ u8 pcba_ver; /* 0x2 - PCBA Revision Register */ u8 system_rst; /* 0x3 - system reset register */ - u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */ + u8 res0; /* 0x4 - not used */ u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ u8 por_cfg; /* 0x6 - POR Control Register */ u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ @@ -29,6 +29,8 @@ typedef struct cpld_data { u8 fbank_sel; /* 0xb - Flash bank selection */ u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ u8 sw[1]; /* 0xd - SW2 Status */ + u8 system_rst_default; /* 0xe - system reset to default register */ + u8 sysclk_sw1; /* 0xf - sysclk configuration register */ } __attribute__ ((packed)) cpld_data_t; #define SERDES_MUX_LANE_6_MASK 0x2 @@ -39,6 +41,9 @@ typedef struct cpld_data { #define SERDES_MUX_LANE_C_SHIFT 2 #define SERDES_MUX_LANE_D_MASK 0x8 #define SERDES_MUX_LANE_D_SHIFT 3 +#define CPLD_SWITCH_BANK_ENABLE 0x40 +#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */ +#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */ /* Pointer to the CPLD register set */ #define cpld ((cpld_data_t *)CPLD_BASE) diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index e9c699c..3637093 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -37,7 +37,10 @@ const board_specific_parameters_t board_specific_parameters[] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 1017, 1116, 2, 4, 6, 0xff, 2, 0}, + { 0, 750, 2, 3, 5, 0xff, 2, 0}, + { 751, 1250, 2, 4, 6, 0xff, 2, 0}, + { 1251, 1350, 2, 5, 7, 0xff, 2, 0}, + { 1351, 1666, 2, 5, 8, 0xff, 2, 0}, }; void fsl_ddr_board_options(memctl_options_t *popts, diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c new file mode 100644 index 0000000..0a1dfa7 --- /dev/null +++ b/board/freescale/p2041rdb/eth.c @@ -0,0 +1,225 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs + * are provided by the three on-board PHY or by the standard Freescale + * four-port SGMII riser card. We need to change the phy-handle in the + * kernel dts file to point to the correct PHY according to serdes mux + * and serdes protocol selection. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/fsl_serdes.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <asm/fsl_dtsec.h> + +#include "cpld.h" +#include "../common/fman.h" + +#ifdef CONFIG_FMAN_ENET +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 +}; + +static int riser_phy_addr[] = { + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* + * Initialize the lane_to_slot[] array. + * + * On the P2040RDB board the mapping is controlled by CPLD register. + */ +static void initialize_lane_to_slot(void) +{ + u8 mux = CPLD_READ(serdes_mux); + + lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; + lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; + lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; + lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + + /* The RGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_RGMII) { + sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* The SGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_SGMII) { + int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); + u8 slot; + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + sprintf(phy, "phy_sgmii_%x", + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + (port - FM1_DTSEC1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } else { + sprintf(phy, "phy_sgmii_%x", + CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + + (port - FM1_DTSEC1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } + + if (intf == PHY_INTERFACE_MODE_XGMII) { + /* XAUI */ + int lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + /* The XAUI PHY is identified by the slot */ + sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + unsigned int i, slot; + int lane; + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* + * Program the three on-board SGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (slot) + fm_info_set_phy_address(i, riser_phy_addr[i]); + break; + case PHY_INTERFACE_MODE_RGMII: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + break; + } + + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + slot = lane_to_slot[lane]; + if (slot) + fm_info_set_phy_address(FM1_10GEC1, + CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + } + + fm_info_set_mdio(FM1_10GEC1, + miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 52269d3..6461bd7 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -32,6 +32,7 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> +#include <fm_eth.h> extern void pci_of_setup(void *blob, bd_t *bd); @@ -129,6 +130,20 @@ int board_early_init_r(void) return 0; } +unsigned long get_board_sys_clk(unsigned long dummy) +{ + u8 sysclk_conf = CPLD_READ(sysclk_sw1); + + switch (sysclk_conf & 0x7) { + case CPLD_SYSCLK_83: + return 83333333; + case CPLD_SYSCLK_100: + return 100000000; + default: + return 66666666; + } +} + static const char *serdes_clock_to_string(u32 clock) { switch (clock) { @@ -200,4 +215,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_liodn(blob); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif } diff --git a/board/freescale/p2041rdb/tlb.c b/board/freescale/p2041rdb/tlb.c deleted file mode 100644 index 43f28ed..0000000 --- a/board/freescale/p2041rdb/tlb.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_1M, 1), -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); @@ -568,6 +568,20 @@ MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freesca MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND +P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB +P1010RDB_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SECURE_BOOT +P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT +P1010RDB_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SECURE_BOOT +P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND +P1010RDB_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT +P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND +P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT +P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD +P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH +P1010RDB_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT +P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD +P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH +P1010RDB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD @@ -575,6 +589,10 @@ P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH +P1020MBG-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG +P1020MBG-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,36BIT +P1020MBG-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD +P1020MBG-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD @@ -582,10 +600,40 @@ P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH +P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB +P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,NAND +P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SDCARD +P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,SPIFLASH +P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT +P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,NAND +P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SDCARD +P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB,36BIT,SPIFLASH +P1020UTM-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM +P1020UTM-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,SDCARD +P1020UTM-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT +P1020UTM-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD +P1021RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB +P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,NAND +P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD +P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH +P1021RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT +P1021RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,NAND +P1021RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD +P1021RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND +P1024RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB +P1024RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,36BIT +P1024RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,NAND +P1024RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SDCARD +P1024RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SPIFLASH +P1025RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB +P1025RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,36BIT +P1025RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,NAND +P1025RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SDCARD +P1025RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SPIFLASH P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD @@ -605,19 +653,30 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH +P2020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB +P2020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,NAND +P2020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SDCARD +P2020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SPIFLASH +P2020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT +P2020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,NAND +P2020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD +P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH P2041RDB powerpc mpc85xx p2041rdb freescale P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS powerpc mpc85xx corenet_ds freescale P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 mpq101 powerpc mpc85xx mpq101 mercury - mpq101 stxgp3 powerpc mpc85xx stxgp3 stx diff --git a/common/Makefile b/common/Makefile index 2edbd71..371a0d9 100644 --- a/common/Makefile +++ b/common/Makefile @@ -162,7 +162,13 @@ COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o # others -COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o +ifdef CONFIG_DDR_SPD +SPD := y +endif +ifdef CONFIG_SPD_EEPROM +SPD := y +endif +COBJS-$(SPD) += ddr_spd.o COBJS-$(CONFIG_HWCONFIG) += hwconfig.o COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o COBJS-y += flash.o diff --git a/common/cmd_mp.c b/common/cmd_mp.c index f19bf41..b115b59 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -32,9 +32,8 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return cmd_usage(cmdtp); cpuid = simple_strtoul(argv[1], NULL, 10); - if (cpuid >= cpu_numcores()) { - printf ("Core num: %lu is out of range[0..%d]\n", - cpuid, cpu_numcores() - 1); + if (!is_core_valid(cpuid)) { + printf ("Core num: %lu is not valid\n", cpuid); return 1; } diff --git a/common/fdt_support.c b/common/fdt_support.c index 19b2ef6..46aa842 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1196,13 +1196,13 @@ int fdt_alloc_phandle(void *blob) } /* - * fdt_create_phandle: Create a phandle property for the given node + * fdt_set_phandle: Create a phandle property for the given node * * @fdt: ptr to device tree * @nodeoffset: node to update * @phandle: phandle value to set (must be unique) -*/ -int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle) + */ +int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle) { int ret; @@ -1235,6 +1235,26 @@ int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle) return ret; } +/* + * fdt_create_phandle: Create a phandle property for the given node + * + * @fdt: ptr to device tree + * @nodeoffset: node to update + */ +int fdt_create_phandle(void *fdt, int nodeoffset) +{ + /* see if there is a phandle already */ + int phandle = fdt_get_phandle(fdt, nodeoffset); + + /* if we got 0, means no phandle so create one */ + if (phandle == 0) { + phandle = fdt_alloc_phandle(fdt); + fdt_set_phandle(fdt, nodeoffset, phandle); + } + + return phandle; +} + #if defined(CONFIG_VIDEO) int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf) { diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index c1ee0a6..abfb7f1 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -170,3 +170,55 @@ Single slot system Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf + + +Table for ODT for DDR2 +====================== +Two slots system ++-----------------------+----------+---------------+-----------------------------+-----------------------------+ +| Configuration | |DRAM controller| Slot 1 | Slot 2 | ++-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ +| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | ++ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ +| | | | | | Write | Read | Write | Read | Write | Read | Write | Read | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off | +| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | | +| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off | +|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | | +|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +|Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ +| Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | | ++-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ + +Single slot system ++-------------+------------+---------------+-----------------------------+ +| | |DRAM controller| Rank 1 | Rank 2 | +|Configuration| Write/Read |-------+-------+-------+------+-------+------+ +| | | Write | Read | Write | Read | Write | Read | ++-------------+------------+-------+-------+-------+------+-------+------+ +| | R1 | off | 75 | 150 | off | off | off | +| Dual Rank |------------+-------+-------+-------+------+-------+------+ +| | R2 | off | 75 | 150 | off | off | off | ++-------------+------------+-------+-------+-------+------+-------+------+ +| Single Rank | R1 | off | 75 | 150 | off | ++-------------+------------+-------+-------+-------+------+ + +Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf + diff --git a/doc/README.p1_p2_rdb_pc b/doc/README.p1_p2_rdb_pc new file mode 100644 index 0000000..4437731 --- /dev/null +++ b/doc/README.p1_p2_rdb_pc @@ -0,0 +1,46 @@ +Overview +-------- +P1_P2_RDB_PC represents a set of boards including + P1020MSBG-PC + P1020RDB-PC + P1020UTM-PC + P1021RDB-PC + P1024RDB + P1025RDB + P2020RDB-PC + +They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC +has 64-bit DDR. All others have 32-bit DDR. + +Key features on these boards include: + * DDR3 + * NOR flash + * NAND flash (on RDB's only) + * SPI flash (on RDB's only) + * SDHC/MMC card slot + * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) + * PCIE slot and mini-PCIE slots + +As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM +is used to store SPD data. In case of absent or corrupted SPD, falling back +to timing data embedded in the source code will be used. Raw timing data is +extracted from DDR chip datasheet. Different speeds of DDR are supported with +this approach. ODT option is forced to fit this set of boards, again because +they don't have regular DIMMs. + +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification +for writing timing. + +VSC firmware Address is defined by default in config file for eTSEC1. + +SD width is based off DIP switch. DIP switch is detected on the +board by reading i2c bus and setting the appropriate mux values. + +Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have +pins multiplexing. QE function needs to be disabled to access Nor Flash and +CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" +in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to +enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below + +'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. +'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index b6a7886..dae2442 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -43,6 +43,7 @@ COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o +COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c new file mode 100644 index 0000000..b3f3c3c --- /dev/null +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -0,0 +1,850 @@ +/* Integrated Flash Controller NAND Machine Driver + * + * Copyright (c) 2011 Freescale Semiconductor, Inc + * + * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/fsl_ifc.h> + +#define MAX_BANKS 4 +#define ERR_BYTE 0xFF /* Value returned for read bytes + when read failed */ +#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC + NAND Machine */ + +struct fsl_ifc_ctrl; + +/* mtd information per set */ +struct fsl_ifc_mtd { + struct mtd_info mtd; + struct nand_chip chip; + struct fsl_ifc_ctrl *ctrl; + + struct device *dev; + int bank; /* Chip select bank number */ + unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ + u8 __iomem *vbase; /* Chip select base virtual address */ +}; + +/* overview of the fsl ifc controller */ +struct fsl_ifc_ctrl { + struct nand_hw_control controller; + struct fsl_ifc_mtd *chips[MAX_BANKS]; + + /* device info */ + struct fsl_ifc *regs; + uint8_t __iomem *addr; /* Address of assigned IFC buffer */ + unsigned int cs_nand; /* On which chipsel NAND is connected */ + unsigned int page; /* Last page written to / read from */ + unsigned int read_bytes; /* Number of bytes read during command */ + unsigned int column; /* Saved column from SEQIN */ + unsigned int index; /* Pointer to next byte to 'read' */ + unsigned int status; /* status read from NEESR after last op */ + unsigned int oob; /* Non zero if operating on OOB data */ + unsigned int eccread; /* Non zero for a full-page ECC read */ +}; + +static struct fsl_ifc_ctrl *ifc_ctrl; + +/* 512-byte page with 4-bit ECC, 8-bit */ +static struct nand_ecclayout oob_512_8bit_ecc4 = { + .eccbytes = 8, + .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = { {0, 5}, {6, 2} }, +}; + +/* 512-byte page with 4-bit ECC, 16-bit */ +static struct nand_ecclayout oob_512_16bit_ecc4 = { + .eccbytes = 8, + .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = { {2, 6}, }, +}; + +/* 2048-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_2048_ecc4 = { + .eccbytes = 32, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + }, + .oobfree = { {2, 6}, {40, 24} }, +}; + +/* 4096-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_4096_ecc4 = { + .eccbytes = 64, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + }, + .oobfree = { {2, 6}, {72, 56} }, +}; + +/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_4096_ecc8 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 82} }, +}; + + +/* + * Generic flash bbt descriptors + */ +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 2, /* 0 on 8-bit small page */ + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 2, /* 0 on 8-bit small page */ + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +/* + * Set up the IFC hardware block and page address fields, and the ifc nand + * structure addr field to point to the correct IFC buffer in memory + */ +static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + struct fsl_ifc *ifc = ctrl->regs; + int buf_num; + + ctrl->page = page_addr; + + /* Program ROW0/COL0 */ + out_be32(&ifc->ifc_nand.row0, page_addr); + out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); + + buf_num = page_addr & priv->bufnum_mask; + + ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); + ctrl->index = column; + + /* for OOB data point to the second half of the buffer */ + if (oob) + ctrl->index += mtd->writesize; +} + +static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, + unsigned int bufnum) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2); + u32 __iomem *main = (u32 *)addr; + u8 __iomem *oob = addr + mtd->writesize; + int i; + + for (i = 0; i < mtd->writesize / 4; i++) { + if (__raw_readl(&main[i]) != 0xffffffff) + return 0; + } + + for (i = 0; i < chip->ecc.layout->eccbytes; i++) { + int pos = chip->ecc.layout->eccpos[i]; + + if (__raw_readb(&oob[pos]) != 0xff) + return 0; + } + + return 1; +} + +/* returns nonzero if entire page is blank */ +static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, + u32 *eccstat, unsigned int bufnum) +{ + u32 reg = eccstat[bufnum / 4]; + int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; + + if (errors == 15) { /* uncorrectable */ + /* Blank pages fail hw ECC checks */ + if (is_blank(mtd, ctrl, bufnum)) + return 1; + + /* + * We disable ECCER reporting in hardware due to + * erratum IFC-A002770 -- so report it now if we + * see an uncorrectable error in ECCSTAT. + */ + ctrl->status |= IFC_NAND_EVTER_STAT_ECCER; + } else if (errors > 0) { + mtd->ecc_stats.corrected += errors; + } + + return 0; +} + +/* + * execute IFC NAND command and wait for it to complete + */ +static int fsl_ifc_run_command(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + struct fsl_ifc *ifc = ctrl->regs; + long long end_tick; + u32 eccstat[4]; + int i; + + /* set the chip select for NAND Transaction */ + out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + + /* start read/write seq */ + out_be32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); + + /* wait for NAND Machine complete flag or timeout */ + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + + while (end_tick > get_ticks()) { + ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + + if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) + break; + } + + out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); + + if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) + printf("%s: Flash Time Out Error\n", __func__); + if (ctrl->status & IFC_NAND_EVTER_STAT_WPER) + printf("%s: Write Protect Error\n", __func__); + + if (ctrl->eccread) { + int bufperpage = mtd->writesize / 512; + int bufnum = (ctrl->page & priv->bufnum_mask) * bufperpage; + int bufnum_end = bufnum + bufperpage - 1; + + for (i = bufnum / 4; i <= bufnum_end / 4; i++) + eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + + for (i = bufnum; i <= bufnum_end; i++) { + if (check_read_ecc(mtd, ctrl, eccstat, i)) + break; + } + + ctrl->eccread = 0; + } + + /* returns 0 on success otherwise non-zero) */ + return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; +} + +static void fsl_ifc_do_read(struct nand_chip *chip, + int oob, + struct mtd_info *mtd) +{ + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + struct fsl_ifc *ifc = ctrl->regs; + + /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ + if (mtd->writesize > 512) { + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + + out_be32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + } else { + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); + + if (oob) + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); + else + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + } +} + +/* cmdfunc send commands to the IFC NAND Machine */ +static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + struct fsl_ifc *ifc = ctrl->regs; + + /* clear the read buffer */ + ctrl->read_bytes = 0; + if (command != NAND_CMD_PAGEPROG) + ctrl->index = 0; + + switch (command) { + /* READ0 read the entire buffer to use hardware ECC. */ + case NAND_CMD_READ0: { + out_be32(&ifc->ifc_nand.nand_fbcr, 0); + set_addr(mtd, 0, page_addr, 0); + + ctrl->read_bytes = mtd->writesize + mtd->oobsize; + ctrl->index += column; + + if (chip->ecc.mode == NAND_ECC_HW) + ctrl->eccread = 1; + + fsl_ifc_do_read(chip, 0, mtd); + fsl_ifc_run_command(mtd); + return; + } + + /* READOOB reads only the OOB because no ECC is performed. */ + case NAND_CMD_READOOB: + out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); + set_addr(mtd, column, page_addr, 1); + + ctrl->read_bytes = mtd->writesize + mtd->oobsize; + + fsl_ifc_do_read(chip, 1, mtd); + fsl_ifc_run_command(mtd); + + return; + + /* READID must read all possible bytes while CEB is active */ + case NAND_CMD_READID: + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + /* 4 bytes for manuf, device and exts */ + out_be32(&ifc->ifc_nand.nand_fbcr, 4); + ctrl->read_bytes = 4; + + set_addr(mtd, 0, 0, 0); + fsl_ifc_run_command(mtd); + return; + + /* ERASE1 stores the block and page address */ + case NAND_CMD_ERASE1: + set_addr(mtd, 0, page_addr, 0); + return; + + /* ERASE2 uses the block and page address from ERASE1 */ + case NAND_CMD_ERASE2: + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); + + out_be32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); + + out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ctrl->read_bytes = 0; + fsl_ifc_run_command(mtd); + return; + + /* SEQIN sets up the addr buffer and all registers except the length */ + case NAND_CMD_SEQIN: { + u32 nand_fcr0; + ctrl->column = column; + ctrl->oob = 0; + + if (mtd->writesize > 512) { + nand_fcr0 = + (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); + + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, 0); + } else { + nand_fcr0 = ((NAND_CMD_PAGEPROG << + IFC_NAND_FCR0_CMD1_SHIFT) | + (NAND_CMD_SEQIN << + IFC_NAND_FCR0_CMD2_SHIFT)); + + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT)); + + if (column >= mtd->writesize) { + /* OOB area --> READOOB */ + column -= mtd->writesize; + nand_fcr0 |= NAND_CMD_READOOB << + IFC_NAND_FCR0_CMD0_SHIFT; + ctrl->oob = 1; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + nand_fcr0 |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; + } else { + /* Second 256 bytes --> READ1 */ + nand_fcr0 |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; + } + } + + out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); + set_addr(mtd, column, page_addr, ctrl->oob); + return; + } + + /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ + case NAND_CMD_PAGEPROG: + if (ctrl->oob) + out_be32(&ifc->ifc_nand.nand_fbcr, ctrl->index); + else + out_be32(&ifc->ifc_nand.nand_fbcr, 0); + + fsl_ifc_run_command(mtd); + return; + + case NAND_CMD_STATUS: + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); + out_be32(&ifc->ifc_nand.nand_fbcr, 1); + set_addr(mtd, 0, 0, 0); + ctrl->read_bytes = 1; + + fsl_ifc_run_command(mtd); + + /* Chip sometimes reporting write protect even when it's not */ + out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); + return; + + case NAND_CMD_RESET: + out_be32(&ifc->ifc_nand.nand_fir0, + IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); + fsl_ifc_run_command(mtd); + return; + + default: + printf("%s: error, unsupported command 0x%x.\n", + __func__, command); + } +} + +/* + * Write buf to the IFC NAND Controller Data Buffer + */ +static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + unsigned int bufsize = mtd->writesize + mtd->oobsize; + + if (len <= 0) { + printf("%s of %d bytes", __func__, len); + ctrl->status = 0; + return; + } + + if ((unsigned int)len > bufsize - ctrl->index) { + printf("%s beyond end of buffer " + "(%d requested, %u available)\n", + __func__, len, bufsize - ctrl->index); + len = bufsize - ctrl->index; + } + + memcpy_toio(&ctrl->addr[ctrl->index], buf, len); + ctrl->index += len; +} + +/* + * read a byte from either the IFC hardware buffer if it has any data left + * otherwise issue a command to read a single byte. + */ +static u8 fsl_ifc_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + + /* If there are still bytes in the IFC buffer, then use the + * next byte. */ + if (ctrl->index < ctrl->read_bytes) + return in_8(&ctrl->addr[ctrl->index++]); + + printf("%s beyond end of buffer\n", __func__); + return ERR_BYTE; +} + +/* + * Read two bytes from the IFC hardware buffer + * read function for 16-bit buswith + */ +static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + uint16_t data; + + /* + * If there are still bytes in the IFC buffer, then use the + * next byte. + */ + if (ctrl->index < ctrl->read_bytes) { + data = in_be16((uint16_t *)&ctrl-> + addr[ctrl->index]); + ctrl->index += 2; + return (uint8_t)data; + } + + printf("%s beyond end of buffer\n", __func__); + return ERR_BYTE; +} + +/* + * Read from the IFC Controller Data Buffer + */ +static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + int avail; + + if (len < 0) + return; + + avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); + memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); + ctrl->index += avail; + + if (len > avail) + printf("%s beyond end of buffer " + "(%d requested, %d available)\n", + __func__, len, avail); +} + +/* + * Verify buffer against the IFC Controller Data Buffer + */ +static int fsl_ifc_verify_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + int i; + + if (len < 0) { + printf("%s of %d bytes", __func__, len); + return -EINVAL; + } + + if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { + printf("%s beyond end of buffer " + "(%d requested, %u available)\n", + __func__, len, ctrl->read_bytes - ctrl->index); + + ctrl->index = ctrl->read_bytes; + return -EINVAL; + } + + for (i = 0; i < len; i++) + if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) + break; + + ctrl->index += len; + return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; +} + +/* This function is called after Program and Erase Operations to + * check for success or failure. + */ +static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + struct fsl_ifc *ifc = ctrl->regs; + u32 nand_fsr; + + if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) + return NAND_STATUS_FAIL; + + /* Use READ_STATUS command, but wait for the device to be ready */ + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD0_SHIFT); + out_be32(&ifc->ifc_nand.nand_fbcr, 1); + set_addr(mtd, 0, 0, 0); + ctrl->read_bytes = 1; + + fsl_ifc_run_command(mtd); + + if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) + return NAND_STATUS_FAIL; + + nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); + + /* Chip sometimes reporting write protect even when it's not */ + nand_fsr = nand_fsr | NAND_STATUS_WP; + return nand_fsr; +} + +static int fsl_ifc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, int page) +{ + struct fsl_ifc_mtd *priv = chip->priv; + struct fsl_ifc_ctrl *ctrl = priv->ctrl; + + fsl_ifc_read_buf(mtd, buf, mtd->writesize); + fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) + mtd->ecc_stats.failed++; + + return 0; +} + +/* ECC will be calculated automatically, and errors will be detected in + * waitfunc. + */ +static void fsl_ifc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + fsl_ifc_write_buf(mtd, buf, mtd->writesize); + fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); +} + +static void fsl_ifc_ctrl_init(void) +{ + ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL); + if (!ifc_ctrl) + return; + + ifc_ctrl->regs = IFC_BASE_ADDR; + + /* clear event registers */ + out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); + out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); + + /* Enable error and event for any detected errors */ + out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); + + out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); +} + +static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) +{ +} + +int board_nand_init(struct nand_chip *nand) +{ + struct fsl_ifc_mtd *priv; + struct nand_ecclayout *layout; + uint32_t cspr = 0, csor = 0; + + if (!ifc_ctrl) { + fsl_ifc_ctrl_init(); + if (!ifc_ctrl) + return -1; + } + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ctrl = ifc_ctrl; + priv->vbase = nand->IO_ADDR_R; + + /* Find which chip select it is connected to. + */ + for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { + phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R); + + cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); + csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); + + if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && + (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) { + ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT; + break; + } + } + + if (priv->bank >= MAX_BANKS) { + printf("%s: address did not match any " + "chip selects\n", __func__); + return -ENODEV; + } + + ifc_ctrl->chips[priv->bank] = priv; + + /* fill in nand_chip structure */ + /* set up function call table */ + + nand->write_buf = fsl_ifc_write_buf; + nand->read_buf = fsl_ifc_read_buf; + nand->verify_buf = fsl_ifc_verify_buf; + nand->select_chip = fsl_ifc_select_chip; + nand->cmdfunc = fsl_ifc_cmdfunc; + nand->waitfunc = fsl_ifc_wait; + + /* set up nand options */ + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; + + /* set up nand options */ + nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | + NAND_USE_FLASH_BBT; + + if (cspr & CSPR_PORT_SIZE_16) { + nand->read_byte = fsl_ifc_read_byte16; + nand->options |= NAND_BUSWIDTH_16; + } else { + nand->read_byte = fsl_ifc_read_byte; + } + + nand->controller = &ifc_ctrl->controller; + nand->priv = priv; + + nand->ecc.read_page = fsl_ifc_read_page; + nand->ecc.write_page = fsl_ifc_write_page; + + /* Hardware generates ECC per 512 Bytes */ + nand->ecc.size = 512; + nand->ecc.bytes = 8; + + switch (csor & CSOR_NAND_PGS_MASK) { + case CSOR_NAND_PGS_512: + if (nand->options & NAND_BUSWIDTH_16) { + layout = &oob_512_16bit_ecc4; + } else { + layout = &oob_512_8bit_ecc4; + + /* Avoid conflict with bad block marker */ + bbt_main_descr.offs = 0; + bbt_mirror_descr.offs = 0; + } + + priv->bufnum_mask = 15; + break; + + case CSOR_NAND_PGS_2K: + layout = &oob_2048_ecc4; + priv->bufnum_mask = 3; + break; + + case CSOR_NAND_PGS_4K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_4096_ecc4; + } else { + layout = &oob_4096_ecc8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 1; + break; + + default: + printf("ifc nand: bad csor %#x: bad page size\n", csor); + return -ENODEV; + } + + /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ + if (csor & CSOR_NAND_ECC_DEC_EN) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = layout; + } else { + nand->ecc.mode = NAND_ECC_SOFT; + } + + return 0; +} diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 34b4322..1f94360 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -81,6 +81,7 @@ COBJS-$(CONFIG_TIGON3) += bcm570x_autoneg.o COBJS-$(CONFIG_TIGON3) += 5701rls.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o +COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile new file mode 100644 index 0000000..072b178 --- /dev/null +++ b/drivers/net/fm/Makefile @@ -0,0 +1,62 @@ +# +# Copyright 2009-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libfm.o + +ifdef CONFIG_FMAN_ENET +COBJS-y += dtsec.o +COBJS-y += eth.o +COBJS-y += fm.o +COBJS-y += init.o +COBJS-y += tgec.o +COBJS-y += tgec_phy.o + +# SoC specific SERDES support +COBJS-$(CONFIG_P1017) += p1023.o +COBJS-$(CONFIG_P1023) += p1023.o +# The P204x, P304x, and P5020 are the same +COBJS-$(CONFIG_PPC_P2040) += p5020.o +COBJS-$(CONFIG_PPC_P2041) += p5020.o +COBJS-$(CONFIG_PPC_P3041) += p5020.o +COBJS-$(CONFIG_PPC_P3060) += p3060.o +COBJS-$(CONFIG_PPC_P4080) += p4080.o +COBJS-$(CONFIG_PPC_P5020) += p5020.o +endif + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c new file mode 100644 index 0000000..a77ee20 --- /dev/null +++ b/drivers/net/fm/dtsec.c @@ -0,0 +1,181 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/fsl_enet.h> +#include <asm/fsl_dtsec.h> +#include <fsl_mdio.h> +#include <phy.h> + +#include "fm.h" + +#define RCTRL_INIT (RCTRL_GRS | RCTRL_UPROM) +#define TCTRL_INIT TCTRL_GTS +#define MACCFG1_INIT MACCFG1_SOFT_RST + +#define MACCFG2_INIT (MACCFG2_PRE_LEN(0x7) | MACCFG2_LEN_CHECK | \ + MACCFG2_PAD_CRC | MACCFG2_FULL_DUPLEX | \ + MACCFG2_IF_MODE_NIBBLE) + +/* MAXFRM - maximum frame length register */ +#define MAXFRM_MASK 0x00003fff + +static void dtsec_init_mac(struct fsl_enet_mac *mac) +{ + struct dtsec *regs = mac->base; + + /* soft reset */ + out_be32(®s->maccfg1, MACCFG1_SOFT_RST); + udelay(1000); + + /* clear soft reset, Rx/Tx MAC disable */ + out_be32(®s->maccfg1, 0); + + /* graceful stop rx */ + out_be32(®s->rctrl, RCTRL_INIT); + udelay(1000); + + /* graceful stop tx */ + out_be32(®s->tctrl, TCTRL_INIT); + udelay(1000); + + /* disable all interrupts */ + out_be32(®s->imask, IMASK_MASK_ALL); + + /* clear all events */ + out_be32(®s->ievent, IEVENT_CLEAR_ALL); + + /* set the max Rx length */ + out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); + + /* set the ecntrl to reset value */ + out_be32(®s->ecntrl, ECNTRL_DEFAULT); + + /* + * Rx length check, no strip CRC for Rx, pad and append CRC for Tx, + * full duplex + */ + out_be32(®s->maccfg2, MACCFG2_INIT); +} + +static void dtsec_enable_mac(struct fsl_enet_mac *mac) +{ + struct dtsec *regs = mac->base; + + /* enable Rx/Tx MAC */ + setbits_be32(®s->maccfg1, MACCFG1_RXTX_EN); + + /* clear the graceful Rx stop */ + clrbits_be32(®s->rctrl, RCTRL_GRS); + + /* clear the graceful Tx stop */ + clrbits_be32(®s->tctrl, TCTRL_GTS); +} + +static void dtsec_disable_mac(struct fsl_enet_mac *mac) +{ + struct dtsec *regs = mac->base; + + /* graceful Rx stop */ + setbits_be32(®s->rctrl, RCTRL_GRS); + + /* graceful Tx stop */ + setbits_be32(®s->tctrl, TCTRL_GTS); + + /* disable Rx/Tx MAC */ + clrbits_be32(®s->maccfg1, MACCFG1_RXTX_EN); +} + +static void dtsec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) +{ + struct dtsec *regs = mac->base; + u32 mac_addr1, mac_addr2; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MACSTNADDR1 of 0xCDAB7856, MACSTNADDR2 of 0x34120000 + */ + mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \ + (mac_addr[3] << 8) | (mac_addr[2]); + out_be32(®s->macstnaddr1, mac_addr1); + + mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; + out_be32(®s->macstnaddr2, mac_addr2); +} + +static void dtsec_set_interface_mode(struct fsl_enet_mac *mac, + phy_interface_t type, int speed) +{ + struct dtsec *regs = mac->base; + u32 ecntrl, maccfg2; + + /* clear all bits relative with interface mode */ + ecntrl = in_be32(®s->ecntrl); + ecntrl &= ~(ECNTRL_TBIM | ECNTRL_GMIIM | ECNTRL_RPM | + ECNTRL_R100M | ECNTRL_SGMIIM); + + maccfg2 = in_be32(®s->maccfg2); + maccfg2 &= ~MACCFG2_IF_MODE_MASK; + + if (speed == SPEED_1000) + maccfg2 |= MACCFG2_IF_MODE_BYTE; + else + maccfg2 |= MACCFG2_IF_MODE_NIBBLE; + + /* set interface mode */ + switch (type) { + case PHY_INTERFACE_MODE_GMII: + ecntrl |= ECNTRL_GMIIM; + break; + case PHY_INTERFACE_MODE_RGMII: + ecntrl |= (ECNTRL_GMIIM | ECNTRL_RPM); + if (speed == SPEED_100) + ecntrl |= ECNTRL_R100M; + break; + case PHY_INTERFACE_MODE_RMII: + if (speed == SPEED_100) + ecntrl |= ECNTRL_R100M; + break; + case PHY_INTERFACE_MODE_SGMII: + ecntrl |= (ECNTRL_SGMIIM | ECNTRL_TBIM); + if (speed == SPEED_100) + ecntrl |= ECNTRL_R100M; + break; + default: + break; + } + + out_be32(®s->ecntrl, ecntrl); + out_be32(®s->maccfg2, maccfg2); +} + +void init_dtsec(struct fsl_enet_mac *mac, void *base, + void *phyregs, int max_rx_len) +{ + mac->base = base; + mac->phyregs = NULL; + mac->max_rx_len = max_rx_len; + mac->init_mac = dtsec_init_mac; + mac->enable_mac = dtsec_enable_mac; + mac->disable_mac = dtsec_disable_mac; + mac->set_mac_addr = dtsec_set_mac_addr; + mac->set_if_mode = dtsec_set_interface_mode; +} diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c new file mode 100644 index 0000000..308d610 --- /dev/null +++ b/drivers/net/fm/eth.c @@ -0,0 +1,670 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <net.h> +#include <hwconfig.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> +#include <asm/fsl_tgec.h> + +#include "fm.h" + +static struct eth_device *devlist[NUM_FM_PORTS]; +static int num_controllers; + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) + +#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \ + TBIANA_FULL_DUPLEX) + +#define TBIANA_SGMII_ACK 0x4001 + +#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \ + TBICR_FULL_DUPLEX | TBICR_SPEED1_SET) + +/* Configure the TBI for SGMII operation */ +void dtsec_configure_serdes(struct fm_eth *priv) +{ + struct dtsec *regs = priv->mac->base; + struct tsec_mii_mng *phyregs = priv->mac->phyregs; + + /* + * Access TBI PHY registers at given TSEC register offset as + * opposed to the register offset used for external PHY accesses + */ + tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON, + TBICON_CLK_SELECT); + tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA, + TBIANA_SGMII_ACK); + tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, + TBI_CR, TBICR_SETTINGS); +} + +static void dtsec_init_phy(struct eth_device *dev) +{ + struct fm_eth *fm_eth = dev->priv; + struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; + + /* Assign a Physical address to the TBI */ + out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); + + if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) + dtsec_configure_serdes(fm_eth); +} + +static int tgec_is_fibre(struct eth_device *dev) +{ + struct fm_eth *fm = dev->priv; + char phyopt[20]; + + sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1); + + return hwconfig_arg_cmp(phyopt, "xfi"); +} +#endif + +static u16 muram_readw(u16 *addr) +{ + u32 base = (u32)addr & ~0x3; + u32 val32 = *(u32 *)base; + int byte_pos; + u16 ret; + + byte_pos = (u32)addr & 0x3; + if (byte_pos) + ret = (u16)(val32 & 0x0000ffff); + else + ret = (u16)((val32 & 0xffff0000) >> 16); + + return ret; +} + +static void muram_writew(u16 *addr, u16 val) +{ + u32 base = (u32)addr & ~0x3; + u32 org32 = *(u32 *)base; + u32 val32; + int byte_pos; + + byte_pos = (u32)addr & 0x3; + if (byte_pos) + val32 = (org32 & 0xffff0000) | val; + else + val32 = (org32 & 0x0000ffff) | ((u32)val << 16); + + *(u32 *)base = val32; +} + +static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) +{ + int timeout = 1000000; + + clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN); + + /* wait until the rx port is not busy */ + while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--) + ; +} + +static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port) +{ + /* set BMI to independent mode, Rx port disable */ + out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM); + /* clear FOF in IM case */ + out_be32(&rx_port->fmbm_rim, 0); + /* Rx frame next engine -RISC */ + out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX); + /* Rx command attribute - no order, MR[3] = 1 */ + clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK); + setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4)); + /* enable Rx statistic counters */ + out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN); + /* disable Rx performance counters */ + out_be32(&rx_port->fmbm_rpc, 0); +} + +static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port) +{ + int timeout = 1000000; + + clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN); + + /* wait until the tx port is not busy */ + while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--) + ; +} + +static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port) +{ + /* set BMI to independent mode, Tx port disable */ + out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM); + /* Tx frame next engine -RISC */ + out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX); + out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX); + /* Tx command attribute - no order, MR[3] = 1 */ + clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK); + setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4)); + /* enable Tx statistic counters */ + out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN); + /* disable Tx performance counters */ + out_be32(&tx_port->fmbm_tpc, 0); +} + +static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + u32 pram_page_offset; + void *rx_bd_ring_base; + void *rx_buf_pool; + struct fm_port_bd *rxbd; + struct fm_port_qd *rxqd; + struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port; + int i; + + /* alloc global parameter ram at MURAM */ + pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, + FM_PRAM_SIZE, FM_PRAM_ALIGN); + fm_eth->rx_pram = pram; + + /* parameter page offset to MURAM */ + pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); + + /* enable global mode- snooping data buffers and BDs */ + pram->mode = PRAM_MODE_GLOBAL; + + /* init the Rx queue descriptor pionter */ + pram->rxqd_ptr = pram_page_offset + 0x20; + + /* set the max receive buffer length, power of 2 */ + muram_writew(&pram->mrblr, MAX_RXBUF_LOG2); + + /* alloc Rx buffer descriptors from main memory */ + rx_bd_ring_base = malloc(sizeof(struct fm_port_bd) + * RX_BD_RING_SIZE); + if (!rx_bd_ring_base) + return 0; + memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd) + * RX_BD_RING_SIZE); + + /* alloc Rx buffer from main memory */ + rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); + if (!rx_buf_pool) + return 0; + memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); + + /* save them to fm_eth */ + fm_eth->rx_bd_ring = rx_bd_ring_base; + fm_eth->cur_rxbd = rx_bd_ring_base; + fm_eth->rx_buf = rx_buf_pool; + + /* init Rx BDs ring */ + rxbd = (struct fm_port_bd *)rx_bd_ring_base; + for (i = 0; i < RX_BD_RING_SIZE; i++) { + rxbd->status = RxBD_EMPTY; + rxbd->len = 0; + rxbd->buf_ptr_hi = 0; + rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN; + rxbd++; + } + + /* set the Rx queue descriptor */ + rxqd = &pram->rxqd; + muram_writew(&rxqd->gen, 0); + muram_writew(&rxqd->bd_ring_base_hi, 0); + rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base; + muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd) + * RX_BD_RING_SIZE); + muram_writew(&rxqd->offset_in, 0); + muram_writew(&rxqd->offset_out, 0); + + /* set IM parameter ram pointer to Rx Frame Queue ID */ + out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset); + + return 1; +} + +static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + u32 pram_page_offset; + void *tx_bd_ring_base; + struct fm_port_bd *txbd; + struct fm_port_qd *txqd; + struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port; + int i; + + /* alloc global parameter ram at MURAM */ + pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, + FM_PRAM_SIZE, FM_PRAM_ALIGN); + fm_eth->tx_pram = pram; + + /* parameter page offset to MURAM */ + pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); + + /* enable global mode- snooping data buffers and BDs */ + pram->mode = PRAM_MODE_GLOBAL; + + /* init the Tx queue descriptor pionter */ + pram->txqd_ptr = pram_page_offset + 0x40; + + /* alloc Tx buffer descriptors from main memory */ + tx_bd_ring_base = malloc(sizeof(struct fm_port_bd) + * TX_BD_RING_SIZE); + if (!tx_bd_ring_base) + return 0; + memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd) + * TX_BD_RING_SIZE); + /* save it to fm_eth */ + fm_eth->tx_bd_ring = tx_bd_ring_base; + fm_eth->cur_txbd = tx_bd_ring_base; + + /* init Tx BDs ring */ + txbd = (struct fm_port_bd *)tx_bd_ring_base; + for (i = 0; i < TX_BD_RING_SIZE; i++) { + txbd->status = TxBD_LAST; + txbd->len = 0; + txbd->buf_ptr_hi = 0; + txbd->buf_ptr_lo = 0; + } + + /* set the Tx queue decriptor */ + txqd = &pram->txqd; + muram_writew(&txqd->bd_ring_base_hi, 0); + txqd->bd_ring_base_lo = (u32)tx_bd_ring_base; + muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd) + * TX_BD_RING_SIZE); + muram_writew(&txqd->offset_in, 0); + muram_writew(&txqd->offset_out, 0); + + /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */ + out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset); + + return 1; +} + +static int fm_eth_init(struct fm_eth *fm_eth) +{ + + if (!fm_eth_rx_port_parameter_init(fm_eth)) + return 0; + + if (!fm_eth_tx_port_parameter_init(fm_eth)) + return 0; + + return 1; +} + +static int fm_eth_startup(struct fm_eth *fm_eth) +{ + struct fsl_enet_mac *mac; + mac = fm_eth->mac; + + /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */ + if (!fm_eth_init(fm_eth)) + return 0; + /* setup the MAC controller */ + mac->init_mac(mac); + + /* For some reason we need to set SPEED_100 */ + if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode) + mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); + + /* init bmi rx port, IM mode and disable */ + bmi_rx_port_init(fm_eth->rx_port); + /* init bmi tx port, IM mode and disable */ + bmi_tx_port_init(fm_eth->tx_port); + + return 1; +} + +static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + + pram = fm_eth->tx_pram; + /* graceful stop transmission of frames */ + pram->mode |= PRAM_MODE_GRACEFUL_STOP; + sync(); +} + +static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) +{ + struct fm_port_global_pram *pram; + + pram = fm_eth->tx_pram; + /* re-enable transmission of frames */ + pram->mode &= ~PRAM_MODE_GRACEFUL_STOP; + sync(); +} + +static int fm_eth_open(struct eth_device *dev, bd_t *bd) +{ + struct fm_eth *fm_eth; + struct fsl_enet_mac *mac; + + fm_eth = (struct fm_eth *)dev->priv; + mac = fm_eth->mac; + + /* setup the MAC address */ + if (dev->enetaddr[0] & 0x01) { + printf("%s: MacAddress is multcast address\n", __func__); + return 1; + } + mac->set_mac_addr(mac, dev->enetaddr); + + /* enable bmi Rx port */ + setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN); + /* enable MAC rx/tx port */ + mac->enable_mac(mac); + /* enable bmi Tx port */ + setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN); + /* re-enable transmission of frame */ + fmc_tx_port_graceful_stop_disable(fm_eth); + +#ifdef CONFIG_PHYLIB + phy_startup(fm_eth->phydev); +#else + fm_eth->phydev->speed = SPEED_1000; + fm_eth->phydev->link = 1; + fm_eth->phydev->duplex = DUPLEX_FULL; +#endif + + /* set the MAC-PHY mode */ + mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed); + + if (!fm_eth->phydev->link) + printf("%s: No link.\n", fm_eth->phydev->dev->name); + + return fm_eth->phydev->link ? 0 : -1; +} + +static void fm_eth_halt(struct eth_device *dev) +{ + struct fm_eth *fm_eth; + struct fsl_enet_mac *mac; + + fm_eth = (struct fm_eth *)dev->priv; + mac = fm_eth->mac; + + /* graceful stop the transmission of frames */ + fmc_tx_port_graceful_stop_enable(fm_eth); + /* disable bmi Tx port */ + bmi_tx_port_disable(fm_eth->tx_port); + /* disable MAC rx/tx port */ + mac->disable_mac(mac); + /* disable bmi Rx port */ + bmi_rx_port_disable(fm_eth->rx_port); + + phy_shutdown(fm_eth->phydev); +} + +static int fm_eth_send(struct eth_device *dev, volatile void *buf, int len) +{ + struct fm_eth *fm_eth; + struct fm_port_global_pram *pram; + struct fm_port_bd *txbd, *txbd_base; + u16 offset_in; + int i; + + fm_eth = (struct fm_eth *)dev->priv; + pram = fm_eth->tx_pram; + txbd = fm_eth->cur_txbd; + + /* find one empty TxBD */ + for (i = 0; txbd->status & TxBD_READY; i++) { + udelay(100); + if (i > 0x1000) { + printf("%s: Tx buffer not ready\n", dev->name); + return 0; + } + } + /* setup TxBD */ + txbd->buf_ptr_hi = 0; + txbd->buf_ptr_lo = (u32)buf; + txbd->len = len; + sync(); + txbd->status = TxBD_READY | TxBD_LAST; + sync(); + + /* update TxQD, let RISC to send the packet */ + offset_in = muram_readw(&pram->txqd.offset_in); + offset_in += sizeof(struct fm_port_bd); + if (offset_in >= muram_readw(&pram->txqd.bd_ring_size)) + offset_in = 0; + muram_writew(&pram->txqd.offset_in, offset_in); + sync(); + + /* wait for buffer to be transmitted */ + for (i = 0; txbd->status & TxBD_READY; i++) { + udelay(100); + if (i > 0x10000) { + printf("%s: Tx error\n", dev->name); + return 0; + } + } + + /* advance the TxBD */ + txbd++; + txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring; + if (txbd >= (txbd_base + TX_BD_RING_SIZE)) + txbd = txbd_base; + /* update current txbd */ + fm_eth->cur_txbd = (void *)txbd; + + return 1; +} + +static int fm_eth_recv(struct eth_device *dev) +{ + struct fm_eth *fm_eth; + struct fm_port_global_pram *pram; + struct fm_port_bd *rxbd, *rxbd_base; + u16 status, len; + u8 *data; + u16 offset_out; + + fm_eth = (struct fm_eth *)dev->priv; + pram = fm_eth->rx_pram; + rxbd = fm_eth->cur_rxbd; + status = rxbd->status; + + while (!(status & RxBD_EMPTY)) { + if (!(status & RxBD_ERROR)) { + data = (u8 *)rxbd->buf_ptr_lo; + len = rxbd->len; + NetReceive(data, len); + } else { + printf("%s: Rx error\n", dev->name); + return 0; + } + + /* clear the RxBDs */ + rxbd->status = RxBD_EMPTY; + rxbd->len = 0; + sync(); + + /* advance RxBD */ + rxbd++; + rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring; + if (rxbd >= (rxbd_base + RX_BD_RING_SIZE)) + rxbd = rxbd_base; + /* read next status */ + status = rxbd->status; + + /* update RxQD */ + offset_out = muram_readw(&pram->rxqd.offset_out); + offset_out += sizeof(struct fm_port_bd); + if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size)) + offset_out = 0; + muram_writew(&pram->rxqd.offset_out, offset_out); + sync(); + } + fm_eth->cur_rxbd = (void *)rxbd; + + return 1; +} + +static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) +{ + struct fsl_enet_mac *mac; + int num; + void *base, *phyregs = NULL; + + num = fm_eth->num; + + /* Get the mac registers base address */ + if (fm_eth->type == FM_ETH_1G_E) { + base = ®->mac_1g[num].fm_dtesc; + } else { + base = ®->mac_10g[num].fm_10gec; + phyregs = ®->mac_10g[num].fm_10gec_mdio; + } + + /* alloc mac controller */ + mac = malloc(sizeof(struct fsl_enet_mac)); + if (!mac) + return 0; + memset(mac, 0, sizeof(struct fsl_enet_mac)); + + /* save the mac to fm_eth struct */ + fm_eth->mac = mac; + + if (fm_eth->type == FM_ETH_1G_E) + init_dtsec(mac, base, NULL, MAX_RXBUF_LEN); + else + init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); + + return 1; +} + +static int init_phy(struct eth_device *dev) +{ + struct fm_eth *fm_eth = dev->priv; + struct phy_device *phydev = NULL; + u32 supported; + +#ifdef CONFIG_PHYLIB + if (fm_eth->type == FM_ETH_1G_E) + dtsec_init_phy(dev); + + if (fm_eth->bus) { + phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev, + fm_eth->enet_if); + } + + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + + if (fm_eth->type == FM_ETH_1G_E) { + supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full); + } else { + supported = SUPPORTED_10000baseT_Full; + + if (tgec_is_fibre(dev)) + phydev->port = PORT_FIBRE; + } + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + + fm_eth->phydev = phydev; + + phy_config(phydev); +#endif + + return 0; +} + +int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) +{ + struct eth_device *dev; + struct fm_eth *fm_eth; + int i, num = info->num; + + /* alloc eth device */ + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) + return 0; + memset(dev, 0, sizeof(struct eth_device)); + + /* alloc the FMan ethernet private struct */ + fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth)); + if (!fm_eth) + return 0; + memset(fm_eth, 0, sizeof(struct fm_eth)); + + /* save off some things we need from the info struct */ + fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */ + fm_eth->num = num; + fm_eth->type = info->type; + + fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi; + fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi; + + /* set the ethernet max receive length */ + fm_eth->max_rx_len = MAX_RXBUF_LEN; + + /* init global mac structure */ + if (!fm_eth_init_mac(fm_eth, reg)) + return 0; + + /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */ + if (fm_eth->type == FM_ETH_1G_E) + sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1); + else + sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1); + + devlist[num_controllers++] = dev; + dev->iobase = 0; + dev->priv = (void *)fm_eth; + dev->init = fm_eth_open; + dev->halt = fm_eth_halt; + dev->send = fm_eth_send; + dev->recv = fm_eth_recv; + fm_eth->dev = dev; + fm_eth->bus = info->bus; + fm_eth->phyaddr = info->phy_addr; + fm_eth->enet_if = info->enet_if; + + /* startup the FM im */ + if (!fm_eth_startup(fm_eth)) + return 0; + + if (init_phy(dev)) + return 0; + + /* clear the ethernet address */ + for (i = 0; i < 6; i++) + dev->enetaddr[i] = 0; + eth_register(dev); + + return 1; +} diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c new file mode 100644 index 0000000..23ef14b --- /dev/null +++ b/drivers/net/fm/fm.c @@ -0,0 +1,432 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> + +#include "fm.h" +#include "../../qe/qe.h" /* For struct qe_firmware */ + +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include <nand.h> +#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) +#include <spi_flash.h> +#elif defined(CONFIG_SYS_QE_FW_IN_MMC) +#include <mmc.h> +#endif + +struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; + +u32 fm_muram_base(int fm_idx) +{ + return muram[fm_idx].base; +} + +u32 fm_muram_alloc(int fm_idx, u32 size, u32 align) +{ + u32 ret; + u32 align_mask, off; + u32 save; + + align_mask = align - 1; + save = muram[fm_idx].alloc; + + off = save & align_mask; + if (off != 0) + muram[fm_idx].alloc += (align - off); + off = size & align_mask; + if (off != 0) + size += (align - off); + if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) { + muram[fm_idx].alloc = save; + printf("%s: run out of ram.\n", __func__); + } + + ret = muram[fm_idx].alloc; + muram[fm_idx].alloc += size; + memset((void *)ret, 0, size); + + return ret; +} + +static void fm_init_muram(int fm_idx, void *reg) +{ + u32 base = (u32)reg; + + muram[fm_idx].base = base; + muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE; + muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE; +} + +/* + * fm_upload_ucode - Fman microcode upload worker function + * + * This function does the actual uploading of an Fman microcode + * to an Fman. + */ +static void fm_upload_ucode(int fm_idx, struct fm_imem *imem, + u32 *ucode, unsigned int size) +{ + unsigned int i; + unsigned int timeout = 1000000; + + /* enable address auto increase */ + out_be32(&imem->iadd, IRAM_IADD_AIE); + /* write microcode to IRAM */ + for (i = 0; i < size / 4; i++) + out_be32(&imem->idata, ucode[i]); + + /* verify if the writing is over */ + out_be32(&imem->iadd, 0); + while ((in_be32(&imem->idata) != ucode[0]) && --timeout) + ; + if (!timeout) + printf("Fman%u: microcode upload timeout\n", fm_idx + 1); + + /* enable microcode from IRAM */ + out_be32(&imem->iready, IRAM_READY); +} + +/* + * Upload an Fman firmware + * + * This function is similar to qe_upload_firmware(), exception that it uploads + * a microcode to the Fman instead of the QE. + * + * Because the process for uploading a microcode to the Fman is similar for + * that of the QE, the QE firmware binary format is used for Fman microcode. + * It should be possible to unify these two functions, but for now we keep them + * separate. + */ +static int fman_upload_firmware(int fm_idx, + struct fm_imem *fm_imem, + const struct qe_firmware *firmware) +{ + unsigned int i; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; + + if (!firmware) { + printf("Fman%u: Invalid address for firmware\n", fm_idx + 1); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1, + firmware); + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1, + hdr->version); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count != 1)) { + printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Fman%u: Invalid length in firmware header\n", + fm_idx + 1); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) { + printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1); + return -EIO; + } + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) { + u32 ucode_size; + u32 *code; + printf("Fman%u: Uploading microcode version %u.%u.%u\n", + fm_idx + 1, ucode->major, ucode->minor, + ucode->revision); + code = (void *)firmware + ucode->code_offset; + ucode_size = sizeof(u32) * ucode->count; + fm_upload_ucode(fm_idx, fm_imem, code, ucode_size); + } + } + + return 0; +} + +static u32 fm_assign_risc(int port_id) +{ + u32 risc_sel, val; + risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1; + val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK; + val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel); + + return val; +} + +static void fm_init_fpm(struct fm_fpm *fpm) +{ + int i, port_id; + u32 val; + + setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC | + FMFPEE_CER | FMFPEE_DER); + + /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */ + + /* offline/parser port */ + for (i = 0; i < MAX_NUM_OH_PORT; i++) { + port_id = OH_PORT_ID_BASE + i; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + } + /* Rx 1G port */ + for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) { + port_id = RX_PORT_1G_BASE + i; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + } + /* Tx 1G port */ + for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) { + port_id = TX_PORT_1G_BASE + i; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + } + /* Rx 10G port */ + port_id = RX_PORT_10G_BASE; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + /* Tx 10G port */ + port_id = TX_PORT_10G_BASE; + val = fm_assign_risc(port_id); + out_be32(&fpm->fpmprc, val); + + /* disable the dispatch limit in IM case */ + out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE); + /* clear events */ + out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT); + + /* clear risc events */ + for (i = 0; i < 4; i++) + out_be32(&fpm->fpmcev[i], 0xffffffff); + + /* clear error */ + out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC); +} + +static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi) +{ + int blk, i, port_id; + u32 val, offset, base; + + /* alloc free buffer pool in MURAM */ + base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN); + if (!base) { + printf("%s: no muram for free buffer pool\n", __func__); + return -ENOMEM; + } + offset = base - fm_muram_base(fm_idx); + + /* Need 128KB total free buffer pool size */ + val = offset / 256; + blk = FM_FREE_POOL_SIZE / 256; + /* in IM, we must not begin from offset 0 in MURAM */ + val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT); + out_be32(&bmi->fmbm_cfg1, val); + + /* disable all BMI interrupt */ + out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL); + + /* clear all events */ + out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL); + + /* + * set port parameters - FMBM_PP_x + * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1 + * max dma 10G Rx/Tx=3, others is 1 + * set port FIFO size - FMBM_PFS_x + * 4KB for all Rx and Tx ports + */ + /* offline/parser port */ + for (i = 0; i < MAX_NUM_OH_PORT; i++) { + port_id = OH_PORT_ID_BASE + i - 1; + /* max tasks=1, max dma=1, no extra */ + out_be32(&bmi->fmbm_pp[port_id], 0); + /* port FIFO size - 256 bytes, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], 0); + } + /* Rx 1G port */ + for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) { + port_id = RX_PORT_1G_BASE + i - 1; + /* max tasks=4, max dma=1, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + } + /* Tx 1G port FIFO size - 4KB, no extra */ + for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) { + port_id = TX_PORT_1G_BASE + i - 1; + /* max tasks=4, max dma=1, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + } + /* Rx 10G port */ + port_id = RX_PORT_10G_BASE - 1; + /* max tasks=12, max dma=3, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + + /* Tx 10G port */ + port_id = TX_PORT_10G_BASE - 1; + /* max tasks=12, max dma=3, no extra */ + out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3)); + /* FIFO size - 4KB, no extra */ + out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf)); + + /* initialize internal buffers data base (linked list) */ + out_be32(&bmi->fmbm_init, FMBM_INIT_START); + + return 0; +} + +static void fm_init_qmi(struct fm_qmi_common *qmi) +{ + /* disable enqueue and dequeue of QMI */ + clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN); + + /* disable all error interrupts */ + out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL); + /* clear all error events */ + out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL); + + /* disable all interrupts */ + out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL); + /* clear all interrupts */ + out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL); +} + +/* Init common part of FM, index is fm num# like fm as above */ +int fm_init_common(int index, struct ccsr_fman *reg) +{ + int rc; + char env_addr[32]; +#if defined(CONFIG_SYS_FMAN_FW_ADDR) + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; +#elif defined(CONFIG_SYS_QE_FW_IN_NAND) + size_t fw_length = CONFIG_SYS_FMAN_FW_LENGTH; + void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); + + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)addr); + if (rc == -EUCLEAN) { + printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", + CONFIG_SYS_QE_FW_IN_NAND, rc); + } +#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) + struct spi_flash *ucode_flash; + void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); + int ret = 0; + + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!ucode_flash) + printf("SF: probe for ucode failed\n"); + else { + ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FW_IN_SPIFLASH, + CONFIG_SYS_FMAN_FW_LENGTH, addr); + if (ret) + printf("SF: read for ucode failed\n"); + spi_flash_free(ucode_flash); + } +#elif defined(CONFIG_SYS_QE_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512; + u32 n; + u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) + printf("\nMMC cannot find device for ucode\n"); + else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + n = mmc->block_dev.block_read(dev, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#endif + + /* Upload the Fman microcode if it's present */ + rc = fman_upload_firmware(index, ®->fm_imem, addr); + if (rc) + return rc; + sprintf(env_addr, "0x%lx", (long unsigned int)addr); + setenv("fman_ucode", env_addr); + + fm_init_muram(index, ®->muram); + fm_init_qmi(®->fm_qmi_common); + fm_init_fpm(®->fm_fpm); + + /* clear DMA status */ + setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL); + + /* set DMA mode */ + setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER); + + return fm_init_bmi(index, ®->fm_bmi_common); +} diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h new file mode 100644 index 0000000..228df33 --- /dev/null +++ b/drivers/net/fm/fm.h @@ -0,0 +1,155 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FM_H__ +#define __FM_H__ + +#include <common.h> +#include <fm_eth.h> +#include <asm/fsl_enet.h> +#include <asm/fsl_fman.h> + +/* Port ID */ +#define OH_PORT_ID_BASE 0x01 +#define MAX_NUM_OH_PORT 7 +#define RX_PORT_1G_BASE 0x08 +#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define RX_PORT_10G_BASE 0x10 +#define TX_PORT_1G_BASE 0x28 +#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define TX_PORT_10G_BASE 0x30 + +struct fm_muram { + u32 base; + u32 top; + u32 size; + u32 alloc; +}; +#define FM_MURAM_RES_SIZE 0x01000 + +/* Rx/Tx buffer descriptor */ +struct fm_port_bd { + u16 status; + u16 len; + u32 res0; + u16 res1; + u16 buf_ptr_hi; + u32 buf_ptr_lo; +}; + +/* Common BD flags */ +#define BD_LAST 0x0800 + +/* Rx BD status flags */ +#define RxBD_EMPTY 0x8000 +#define RxBD_LAST BD_LAST +#define RxBD_FIRST 0x0400 +#define RxBD_PHYS_ERR 0x0008 +#define RxBD_SIZE_ERR 0x0004 +#define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR) + +/* Tx BD status flags */ +#define TxBD_READY 0x8000 +#define TxBD_LAST BD_LAST + +/* Rx/Tx queue descriptor */ +struct fm_port_qd { + u16 gen; + u16 bd_ring_base_hi; + u32 bd_ring_base_lo; + u16 bd_ring_size; + u16 offset_in; + u16 offset_out; + u16 res0; + u32 res1[0x4]; +}; + +/* IM global parameter RAM */ +struct fm_port_global_pram { + u32 mode; /* independent mode register */ + u32 rxqd_ptr; /* Rx queue descriptor pointer */ + u32 txqd_ptr; /* Tx queue descriptor pointer */ + u16 mrblr; /* max Rx buffer length */ + u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */ + u32 res0[0x4]; + struct fm_port_qd rxqd; /* Rx queue descriptor */ + struct fm_port_qd txqd; /* Tx queue descriptor */ + u32 res1[0x28]; +}; + +#define FM_PRAM_SIZE sizeof(struct fm_port_global_pram) +#define FM_PRAM_ALIGN 256 +#define PRAM_MODE_GLOBAL 0x20000000 +#define PRAM_MODE_GRACEFUL_STOP 0x00800000 + +#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */ +#else +#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */ +#endif +#define FM_FREE_POOL_ALIGN 256 + +u32 fm_muram_alloc(int fm_idx, u32 size, u32 align); +u32 fm_muram_base(int fm_idx); +int fm_init_common(int index, struct ccsr_fman *reg); +int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); +phy_interface_t fman_port_enet_if(enum fm_port port); +void fman_disable_port(enum fm_port port); + +struct fsl_enet_mac { + void *base; /* MAC controller registers base address */ + void *phyregs; + int max_rx_len; + void (*init_mac)(struct fsl_enet_mac *mac); + void (*enable_mac)(struct fsl_enet_mac *mac); + void (*disable_mac)(struct fsl_enet_mac *mac); + void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr); + void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type, + int speed); +}; + +/* Fman ethernet private struct */ +struct fm_eth { + int fm_index; /* Fman index */ + u32 num; /* 0..n-1 for give type */ + struct fm_bmi_tx_port *tx_port; + struct fm_bmi_rx_port *rx_port; + enum fm_eth_type type; /* 1G or 10G ethernet */ + phy_interface_t enet_if; + struct fsl_enet_mac *mac; /* MAC controller */ + struct mii_dev *bus; + struct phy_device *phydev; + int phyaddr; + struct eth_device *dev; + int max_rx_len; + struct fm_port_global_pram *rx_pram; /* Rx parameter table */ + struct fm_port_global_pram *tx_pram; /* Tx parameter table */ + void *rx_bd_ring; /* Rx BD ring base */ + void *cur_rxbd; /* current Rx BD */ + void *rx_buf; /* Rx buffer base */ + void *tx_bd_ring; /* Tx BD ring base */ + void *cur_txbd; /* current Tx BD */ +}; + +#define RX_BD_RING_SIZE 8 +#define TX_BD_RING_SIZE 8 +#define MAX_RXBUF_LOG2 11 +#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) + +#endif /* __FM_H__ */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c new file mode 100644 index 0000000..512d7dd --- /dev/null +++ b/drivers/net/fm/init.c @@ -0,0 +1,216 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> + +#include "fm.h" + +struct fm_eth_info fm_info[] = { +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1) + FM_DTSEC_INFO_INITIALIZER(1, 1), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2) + FM_DTSEC_INFO_INITIALIZER(1, 2), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3) + FM_DTSEC_INFO_INITIALIZER(1, 3), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4) + FM_DTSEC_INFO_INITIALIZER(1, 4), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5) + FM_DTSEC_INFO_INITIALIZER(1, 5), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1) + FM_DTSEC_INFO_INITIALIZER(2, 1), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2) + FM_DTSEC_INFO_INITIALIZER(2, 2), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3) + FM_DTSEC_INFO_INITIALIZER(2, 3), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) + FM_DTSEC_INFO_INITIALIZER(2, 4), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 1) + FM_TGEC_INFO_INITIALIZER(1, 1), +#endif +#if (CONFIG_SYS_NUM_FM2_10GEC >= 1) + FM_TGEC_INFO_INITIALIZER(2, 1), +#endif +}; + +int fm_standard_init(bd_t *bis) +{ + int i; + struct ccsr_fman *reg; + + reg = (void *)CONFIG_SYS_FSL_FM1_ADDR; + if (fm_init_common(0, reg)) + return 0; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if ((fm_info[i].enabled) && (fm_info[i].index == 1)) + fm_eth_initialize(reg, &fm_info[i]); + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + reg = (void *)CONFIG_SYS_FSL_FM2_ADDR; + if (fm_init_common(1, reg)) + return 0; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if ((fm_info[i].enabled) && (fm_info[i].index == 2)) + fm_eth_initialize(reg, &fm_info[i]); + } +#endif + + return 1; +} + +/* simple linear search to map from port to array index */ +static int fm_port_to_index(enum fm_port port) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if (fm_info[i].port == port) + return i; + } + + return -1; +} + +/* + * Determine if an interface is actually active based on HW config + * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if + * the interface is not active based on HW cfg of the SoC + */ +void fman_enet_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + phy_interface_t enet_if; + + enet_if = fman_port_enet_if(fm_info[i].port); + if (enet_if != PHY_INTERFACE_MODE_NONE) { + fm_info[i].enabled = 1; + fm_info[i].enet_if = enet_if; + } else { + fm_info[i].enabled = 0; + } + } + + return ; +} + +void fm_disable_port(enum fm_port port) +{ + int i = fm_port_to_index(port); + + fm_info[i].enabled = 0; + fman_disable_port(port); +} + +void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].bus = bus; +} + +void fm_info_set_phy_address(enum fm_port port, int address) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return; + + fm_info[i].phy_addr = address; +} + +/* + * Returns the type of the data interface between the given MAC and its PHY. + * This is typically determined by the RCW. + */ +phy_interface_t fm_info_get_enet_if(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return PHY_INTERFACE_MODE_NONE; + + if (fm_info[i].enabled) + return fm_info[i].enet_if; + + return PHY_INTERFACE_MODE_NONE; +} + +static void +__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + return ; +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) + __attribute__((weak, alias("__def_board_ft_fman_fixup_port"))); + +static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) +{ + int off, ph; + phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; + + off = fdt_node_offset_by_compat_reg(blob, prop, paddr); + + if (info->enabled) { + fdt_fixup_phy_connection(blob, off, info->enet_if); + board_ft_fman_fixup_port(blob, prop, paddr, info->port, off); + return ; + } + + /* board code might have caused offset to change */ + off = fdt_node_offset_by_compat_reg(blob, prop, paddr); + + /* disable both the mac node and the node that has a handle to it */ + fdt_setprop_string(blob, off, "status", "disabled"); + + ph = fdt_get_phandle(blob, off); + do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), + "status", "disabled", strlen("disabled") + 1, 1); +} + +void fdt_fixup_fman_ethernet(void *blob) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + if (fm_info[i].type == FM_ETH_1G_E) + ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac"); + else + ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac"); + } +} diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c new file mode 100644 index 0000000..b17dc40 --- /dev/null +++ b/drivers/net/fm/p1023.c @@ -0,0 +1,74 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1, + [FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + + return port_to_devdisr[port] & devdisr; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + /* DTSEC1 can be SGMII, RGMII or RMII */ + if (port == FM1_DTSEC1) { + if (is_serdes_configured(SGMII_FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) { + if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC) + return PHY_INTERFACE_MODE_RGMII; + else + return PHY_INTERFACE_MODE_RMII; + } + } + + /* DTSEC2 only supports SGMII or RGMII */ + if (port == FM1_DTSEC2) { + if (is_serdes_configured(SGMII_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_SGMII; + if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS) + return PHY_INTERFACE_MODE_RGMII; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/p3060.c b/drivers/net/fm/p3060.c new file mode 100644 index 0000000..b25bca7 --- /dev/null +++ b/drivers/net/fm/p3060.c @@ -0,0 +1,109 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + /* handle RGMII/MII first */ + if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) == + FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) == + FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII)) + return PHY_INTERFACE_MODE_MII; + + if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) == + FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) == + FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII)) + return PHY_INTERFACE_MODE_MII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c new file mode 100644 index 0000000..791caab --- /dev/null +++ b/drivers/net/fm/p4080.c @@ -0,0 +1,100 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, + [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) + return PHY_INTERFACE_MODE_XGMII; + + /* handle RGMII first */ + if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) + return PHY_INTERFACE_MODE_RGMII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c new file mode 100644 index 0000000..69c27d2 --- /dev/null +++ b/drivers/net/fm/p5020.c @@ -0,0 +1,91 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + /* handle RGMII first */ + if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII)) + return PHY_INTERFACE_MODE_MII; + + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII)) + return PHY_INTERFACE_MODE_MII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c new file mode 100644 index 0000000..6c1d471 --- /dev/null +++ b/drivers/net/fm/tgec.c @@ -0,0 +1,119 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* MAXFRM - maximum frame length */ +#define MAXFRM_MASK 0x0000ffff + +#include <common.h> +#include <phy.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/fsl_enet.h> +#include <asm/fsl_tgec.h> + +#include "fm.h" + +#define TGEC_CMD_CFG_INIT (TGEC_CMD_CFG_NO_LEN_CHK | \ + TGEC_CMD_CFG_RX_ER_DISC | \ + TGEC_CMD_CFG_STAT_CLR | \ + TGEC_CMD_CFG_PAUSE_IGNORE | \ + TGEC_CMD_CFG_CRC_FWD) +#define TGEC_CMD_CFG_FINAL (TGEC_CMD_CFG_NO_LEN_CHK | \ + TGEC_CMD_CFG_RX_ER_DISC | \ + TGEC_CMD_CFG_PAUSE_IGNORE | \ + TGEC_CMD_CFG_CRC_FWD) + +static void tgec_init_mac(struct fsl_enet_mac *mac) +{ + struct tgec *regs = mac->base; + + /* mask all interrupt */ + out_be32(®s->imask, IMASK_MASK_ALL); + + /* clear all events */ + out_be32(®s->ievent, IEVENT_CLEAR_ALL); + + /* set the max receive length */ + out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); + + /* + * 1588 disable, insert second mac disable payload length check + * disable, normal operation, any rx error frame is discarded, clear + * counters, pause frame ignore, no promiscuous, LAN mode Rx CRC no + * strip, Tx CRC append, Rx disable and Tx disable + */ + out_be32(®s->command_config, TGEC_CMD_CFG_INIT); + udelay(1000); + out_be32(®s->command_config, TGEC_CMD_CFG_FINAL); + + /* multicast frame reception for the hash entry disable */ + out_be32(®s->hashtable_ctrl, 0); +} + +static void tgec_enable_mac(struct fsl_enet_mac *mac) +{ + struct tgec *regs = mac->base; + + setbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN); +} + +static void tgec_disable_mac(struct fsl_enet_mac *mac) +{ + struct tgec *regs = mac->base; + + clrbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN); +} + +static void tgec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) +{ + struct tgec *regs = mac->base; + u32 mac_addr0, mac_addr1; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB + */ + mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0]); + out_be32(®s->mac_addr_0, mac_addr0); + + mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; + out_be32(®s->mac_addr_1, mac_addr1); +} + +static void tgec_set_interface_mode(struct fsl_enet_mac *mac, + phy_interface_t type, int speed) +{ + /* nothing right now */ + return; +} + +void init_tgec(struct fsl_enet_mac *mac, void *base, + void *phyregs, int max_rx_len) +{ + mac->base = base; + mac->phyregs = phyregs; + mac->max_rx_len = max_rx_len; + mac->init_mac = tgec_init_mac; + mac->enable_mac = tgec_enable_mac; + mac->disable_mac = tgec_disable_mac; + mac->set_mac_addr = tgec_set_mac_addr; + mac->set_if_mode = tgec_set_interface_mode; +} diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c new file mode 100644 index 0000000..2d349ad --- /dev/null +++ b/drivers/net/fm/tgec_phy.c @@ -0,0 +1,139 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Andy Fleming <afleming@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * Some part is taken from tsec.c + */ +#include <common.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/io.h> +#include <asm/fsl_tgec.h> +#include <fm_eth.h> + +/* + * Write value to the PHY for this device to the register at regnum, waiting + * until the write is done before it returns. All PHY configuration has to be + * done through the TSEC1 MIIM regs + */ +int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value) +{ + u32 mdio_ctl; + u32 stat_val; + struct tgec_mdio_controller *regs = bus->priv; + + if (dev_addr == MDIO_DEVAD_NONE) + return 0; + + /* Wait till the bus is free */ + stat_val = MDIO_STAT_CLKDIV(100); + out_be32(®s->mdio_stat, stat_val); + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the port and dev addr */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + out_be32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Write the value to the register */ + out_be32(®s->mdio_data, MDIO_DATA(value)); + + /* Wait till the MDIO write is complete */ + while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + return 0; +} + +/* + * Reads from register regnum in the PHY for device dev, returning the value. + * Clears miimcom first. All PHY configuration has to be done through the + * TSEC1 MIIM regs + */ +int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum) +{ + u32 mdio_ctl; + u32 stat_val; + struct tgec_mdio_controller *regs = bus->priv; + + if (dev_addr == MDIO_DEVAD_NONE) + return 0xffff; + + stat_val = MDIO_STAT_CLKDIV(100); + out_be32(®s->mdio_stat, stat_val); + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the Port and Device Addrs */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + out_be32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Initiate the read */ + mdio_ctl |= MDIO_CTL_READ; + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Wait till the MDIO write is complete */ + while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + /* Return all Fs if nothing was there */ + if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) + return 0xffff; + + return in_be32(®s->mdio_data) & 0xffff; +} + +int tgec_mdio_reset(struct mii_dev *bus) +{ + return 0; +} + +int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FM TGEC MDIO bus\n"); + return -1; + } + + bus->read = tgec_mdio_read; + bus->write = tgec_mdio_write; + bus->reset = tgec_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = info->regs; + + return mdio_register(bus); +} diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 6e0043a..5a65d92 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB * @@ -26,6 +26,7 @@ #include <usb.h> #include <asm/io.h> #include <usb/ehci-fsl.h> +#include <hwconfig.h> #include "ehci.h" #include "ehci-core.h" @@ -39,6 +40,11 @@ int ehci_hcd_init(void) { struct usb_ehci *ehci; + char usb_phy[5]; + const char *phy_type = NULL; + size_t len; + + usb_phy[0] = '\0'; ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); @@ -52,10 +58,37 @@ int ehci_hcd_init(void) out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ - if (!strcmp(getenv("usb_phy_type"), "utmi")) - out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + if (hwconfig_sub("usb1", "phy_type")) + phy_type = hwconfig_subarg("usb1", "phy_type", &len); else + phy_type = getenv("usb_phy_type"); + + if (!phy_type) { +#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY + /* if none specified assume internal UTMI */ + strcpy(usb_phy, "utmi"); + phy_type = usb_phy; +#else + printf("WARNING: USB phy type not defined !!\n"); + return -1; +#endif + } + + if (!strcmp(phy_type, "utmi")) { +#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) + setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); + setbits_be32(&ehci->control, UTMI_PHY_EN); + udelay(1000); /* delay required for PHY Clk to appear */ +#endif + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + } else { +#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) + clrbits_be32(&ehci->control, UTMI_PHY_EN); + setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); + udelay(1000); /* delay required for PHY Clk to appear */ +#endif out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); + } /* Enable interface. */ setbits_be32(&ehci->control, USB_EN); diff --git a/include/common.h b/include/common.h index d244bd4..bcc00e8 100644 --- a/include/common.h +++ b/include/common.h @@ -485,7 +485,22 @@ void ddr_enable_ecc(unsigned int dram_size); #endif /* $(CPU)/cpu.c */ +static inline int cpumask_next(int cpu, unsigned int mask) +{ + for (cpu++; !((1 << cpu) & mask); cpu++) + ; + + return cpu; +} + +#define for_each_cpu(iter, cpu, num_cpus, mask) \ + for (iter = 0, cpu = cpumask_next(-1, mask); \ + iter < num_cpus; \ + iter++, cpu = cpumask_next(cpu, mask)) \ + int cpu_numcores (void); +u32 cpu_mask (void); +int is_core_valid (unsigned int); int probecpu (void); int checkcpu (void); int checkicache (void); @@ -565,10 +580,12 @@ ulong get_PERCLK3(void); ulong get_bus_freq (ulong); int get_serial_clock(void); +#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) +ulong get_ddr_freq(ulong); +#endif #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); -ulong get_ddr_freq (ulong); #endif #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 45b6b5f..da2b11d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -78,6 +78,22 @@ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* + * define CONFIG_FSL_DDR2 to use unified DDR driver + * undefine it to use old spd_sdram.c + */ +#define CONFIG_FSL_DDR2 +#ifdef CONFIG_FSL_DDR2 +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x51 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#endif + +/* * 32-bit data path mode. * * Please note that using this mode for devices with the real density of 64-bit diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 783ed51..f3d325a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -127,22 +127,11 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index e1d933e..fc0edac 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -89,15 +89,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 5918e64..ae19036 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -62,14 +62,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b25fb55..6b03d27 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -74,14 +74,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c9a0f60..aca77ff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -77,14 +77,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 4c580a3..93d4c3e 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -62,14 +62,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index f55ef9d..e03fea3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -86,15 +86,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f7df7f0..cf0ea47 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -71,14 +71,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index fa626bb..dd7278c 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -105,20 +105,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR - /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bb8fb66..6067e60 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -112,22 +112,11 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h new file mode 100644 index 0000000..ca6178a --- /dev/null +++ b/include/configs/P1010RDB.h @@ -0,0 +1,776 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P010 RDB board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + +#ifdef CONFIG_P1010RDB +#define CONFIG_P1010 +#define CONFIG_NAND_FSL_IFC +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_NAND /* NAND Boot */ +#define CONFIG_RAMBOOT_NAND +#define CONFIG_NAND_U_BOOT +#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL +#else +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#endif /* CONFIG_NAND_SPL */ +#endif + + +#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ +#define CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI + +#define CONFIG_E1000 /* E1000 pci Ethernet card*/ + +/* + * PCI Windows + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "PCIe Slot" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ + +#ifndef CONFIG_SDCARD +#define CONFIG_MISC_INIT_R +#endif + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS 0x52 + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#ifndef __ASSEMBLY__ +extern unsigned long get_sdram_size(void); +#endif +#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +/* DDR3 Controller Settings */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x04401010 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 + +/* settings for DDR3 at 667MT/s */ +#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 +#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 +#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_667 0x00441210 +#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* Don't relocate CCSRBAR while in NAND_SPL */ +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* + * Memory map + * + * 0x0000_0000 0x3fff_ffff DDR 1G cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * + * Localbus non-cacheable + * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable + * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* In case of SD card boot, IFC interface is not available because of muxing */ +#ifdef CONFIG_SDCARD +#define CONFIG_SYS_NO_FLASH +#else +/* + * IFC Definitions + */ +/* NOR Flash on IFC */ +#define CONFIG_SYS_FLASH_BASE 0xee000000 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5) +#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ + FTIM1_NOR_TRAD_NOR(0x0f) +#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWP(0x1c) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* CFI for NOR Flash */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ + | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ + | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ + | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ + FTIM0_NAND_TWP(0x0C) | \ + FTIM0_NAND_TWCHT(0x04) | \ + FTIM0_NAND_TWH(0x05) +#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ + FTIM1_NAND_TWBE(0x1d) | \ + FTIM1_NAND_TRR(0x07) | \ + FTIM1_NAND_TRP(0x0c) +#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ + FTIM2_NAND_TREH(0x05) | \ + FTIM2_NAND_TWHRE(0x0f) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NOR/NAND */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT) +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +/* NAND boot: 8K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x2000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffb00000 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull +#else +#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#endif + +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 +#endif /* CONFIG_SDCARD */ + +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ + defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C EEPROM */ +#undef CONFIG_ID_EEPROM +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* RTC */ +#define CONFIG_RTC_PT7C4338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_I2C + +/* + * SPI interface will not be available in case of NAND boot SPI CS0 will be + * used for SLIC + */ +#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT) +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + +#endif /* CONFIG_TSEC_ENET */ + + +/* SATA */ +#define CONFIG_FSL_SATA +#define CONFIG_LIBATA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_CMD_SATA +#define CONFIG_LBA48 +#endif /* #ifdef CONFIG_FSL_SATA */ + +/* SD interface will only be available in case of SD boot */ +#ifdef CONFIG_SDCARD +#define CONFIG_MMC +#define CONFIG_DEF_HWCONFIG esdhc +#endif + +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif +#endif + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ + || defined(CONFIG_FSL_SATA) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_HOSTNAME P1010RDB +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1010rdb.dtb\0" \ + "bdev=sda1\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ + "othbootargs=ramdisk_size=600000\0" \ + "usbfatboot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "fatload usb 0:2 $loadaddr $bootfile;" \ + "fatload usb 0:2 $fdtaddr $fdtfile;" \ + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a118975..a3cccf4 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -64,18 +64,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x7fffffff -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 95f3a2c..9386674 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -99,15 +99,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of addresses in the LBC */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */ -/* physical addr of CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM @@ -534,9 +525,9 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET +#define CONFIG_PHY_MARVELL #endif -#define CONFIG_SYS_FMAN_FW #ifndef CONFIG_NAND /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index df88b79..043515d 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -148,24 +148,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif - /* CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ - /* CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ @@ -594,6 +581,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #endif +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -601,7 +591,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE -#define CONFIG_HAS_FSL_DR_USB +#endif #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 90fe7c4..f6b788e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -118,18 +118,8 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 638dbe7..c7f0761 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -102,7 +102,10 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_SYS_CLK_FREQ 66666666 +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* * These can be toggled for performance analysis, otherwise use default. @@ -138,20 +141,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif -/* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -419,7 +408,6 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME /* Default address of microcode for the Linux Fman driver */ -#define CONFIG_SYS_FMAN_FW #if defined(CONFIG_SPIFLASH) /* * env is stored at 0x100000, sector size is 0x10000, ucode is stored after @@ -443,6 +431,9 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS #endif #ifdef CONFIG_PCI @@ -486,6 +477,8 @@ #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 + #define CONFIG_SYS_TBIPA_VALUE 8 #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC1" diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index d9e8f51..e4d1fe5 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -28,7 +28,12 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P3041 +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_NAND_FSL_ELBC #define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 49f7c53..4a2e475 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -27,6 +27,11 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P4080 +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_PCIE3 + #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index dd8d442..618d1a4 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -28,8 +28,14 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P5020 +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_NAND_FSL_ELBC #define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 #define CONFIG_PCIE4 +#define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 72559c0..b5612d6 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -94,20 +94,6 @@ #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." #endif -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ /* DDR Setup */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index b336723..fe6b728 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -130,18 +130,12 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x10000000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ -#else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xA0000000 +#else +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#endif +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * DDR Setup diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index adf9906..4bbca88 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -56,7 +56,6 @@ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ @@ -144,19 +143,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -212,7 +198,6 @@ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -243,8 +228,6 @@ #endif /* Nand Flash */ -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) -#define CONFIG_NAND_FSL_ELBC #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -285,11 +268,10 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif -#endif /* CONFIG_NAND_FSL_ELBC */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ -#endif +#endif /* CONFIG_NAND_FSL_ELBC */ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 @@ -487,7 +469,6 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME /* Default address of microcode for the Linux Fman driver */ -#define CONFIG_SYS_FMAN_FW #if defined(CONFIG_SPIFLASH) /* * env is stored at 0x100000, sector size is 0x10000, ucode is stored after @@ -511,6 +492,9 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS #endif #ifdef CONFIG_PCI @@ -580,6 +564,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -597,8 +582,6 @@ #define CONFIG_CMD_EXT2 #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -708,4 +691,8 @@ #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h index e76ca73..f0ed4d1 100644 --- a/include/configs/mpq101.h +++ b/include/configs/mpq101.h @@ -64,20 +64,8 @@ #define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_CCSRBAR 0xe0000000 - -#ifdef CONFIG_PHYS_64BIT -# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull -#else -# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#endif - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h new file mode 100644 index 0000000..b9b89cf --- /dev/null +++ b/include/configs/p1_p2_rdb_pc.h @@ -0,0 +1,984 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * QorIQ RDB boards configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + +#if defined(CONFIG_P1020MBG) +#define CONFIG_BOARDNAME "P1020MBG" +#define CONFIG_P1020 +#define CONFIG_VSC7385_ENET +#define CONFIG_SLIC +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xe4 +#define __SW_BOOT_SD 0x54 +#endif + +#if defined(CONFIG_P1020UTM) +#define CONFIG_BOARDNAME "P1020UTM" +#define CONFIG_P1020 +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xe0 +#define __SW_BOOT_SD 0x50 +#endif + +#if defined(CONFIG_P1020RDB) +#define CONFIG_BOARDNAME "P1020RDB" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P1020 +#define CONFIG_SPI_FLASH +#define CONFIG_VSC7385_ENET +#define CONFIG_SLIC +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0x5c +#define __SW_BOOT_SPI 0x1c +#define __SW_BOOT_SD 0x9c +#define __SW_BOOT_NAND 0xec +#define __SW_BOOT_PCIE 0x6c +#endif + +#if defined(CONFIG_P1021RDB) +#define CONFIG_BOARDNAME "P1021RDB" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P1021 +#define CONFIG_QE +#define CONFIG_SPI_FLASH +#define CONFIG_VSC7385_ENET +#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of + addresses in the LBC */ +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0x5c +#define __SW_BOOT_SPI 0x1c +#define __SW_BOOT_SD 0x9c +#define __SW_BOOT_NAND 0xec +#define __SW_BOOT_PCIE 0x6c +#endif + +#if defined(CONFIG_P1024RDB) +#define CONFIG_BOARDNAME "P1024RDB" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P1024 +#define CONFIG_SLIC +#define CONFIG_SPI_FLASH +#define __SW_BOOT_MASK 0xf3 +#define __SW_BOOT_NOR 0x00 +#define __SW_BOOT_SPI 0x08 +#define __SW_BOOT_SD 0x04 +#define __SW_BOOT_NAND 0x0c +#endif + +#if defined(CONFIG_P1025RDB) +#define CONFIG_BOARDNAME "P1025RDB" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P1025 +#define CONFIG_QE +#define CONFIG_SLIC +#define CONFIG_SPI_FLASH + +#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of + addresses in the LBC */ +#define __SW_BOOT_MASK 0xf3 +#define __SW_BOOT_NOR 0x00 +#define __SW_BOOT_SPI 0x08 +#define __SW_BOOT_SD 0x04 +#define __SW_BOOT_NAND 0x0c +#endif + +#if defined(CONFIG_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB" +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_P2020 +#define CONFIG_SPI_FLASH +#define CONFIG_VSC7385_ENET +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xc8 +#define __SW_BOOT_SPI 0x28 +#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_NAND 0xe8 +#define __SW_BOOT_PCIE 0xa8 +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC) +#define CONFIG_NAND_U_BOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL +#else +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#endif /* CONFIG_NAND_SPL */ +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 +#define CONFIG_MPC85xx + +#define CONFIG_MP + +#define CONFIG_FSL_ELBC +#define CONFIG_PCI +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_CMD_SATA +#define CONFIG_SATA_SIL3114 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LIBATA +#define CONFIG_LBA48 + +#if defined(CONFIG_P2020RDB) +#define CONFIG_SYS_CLK_FREQ 100000000 +#else +#define CONFIG_SYS_CLK_FREQ 66666666 +#endif +#define CONFIG_DDR_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS +#endif + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_DDR_RAW_TIMING +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS 0x52 +#define CONFIG_FSL_DDR_INTERACTIVE + +#ifdef CONFIG_P1020MBG +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#else +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#endif +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* Default settings for DDR3 */ +#ifdef CONFIG_P2020RDB +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330104 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF +#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 +#define CONFIG_SYS_DDR_MODE_1 0x00421422 +#define CONFIG_SYS_DDR_MODE_2 0x04000000 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300100 + +#else +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 + +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_MODE_1 0x40461520 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable + * 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable + * 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional) + * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable + * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + + +/* + * Local Bus Definitions + */ +#if defined(CONFIG_P1020MBG) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 +#elif defined(CONFIG_P1020UTM) +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ +#define CONFIG_SYS_FLASH_BASE 0xee000000 +#else +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ +#define CONFIG_SYS_FLASH_BASE 0xef000000 +#endif + + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ + | BR_PS_16 | BR_V) + +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* Nand Flash */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) + +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) +#endif /* CONFIG_NAND_FSL_ELBC */ + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +/* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +/* Size of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ + +#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#endif +/* CPLD config size: 1Mb */ +#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ + BR_PS_8 | BR_V) +#define CONFIG_CPLD_OR_PRELIM (0xfff009f7) + +#define CONFIG_SYS_PMC_BASE 0xff980000 +#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE +#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ + BR_PS_8 | BR_V) +#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif +#endif +#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ + + +/* Vsc7385 switch */ +#ifdef CONFIG_VSC7385_ENET +#define CONFIG_SYS_VSC7385_BASE 0xffb00000 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#else +#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#endif + +#define CONFIG_SYS_VSC7385_BR_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ + OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM + +/* The size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#endif + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_64BIT_STRTOUL + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ + +/* + * I2C2 EEPROM + */ +#undef CONFIG_ID_EEPROM + +#define CONFIG_RTC_PT7C4338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 + +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#if defined(CONFIG_SPI_FLASH) +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +#if defined(CONFIG_PCI) +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + + +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT + +/* video */ +#define CONFIG_VIDEO +#ifdef CONFIG_VIDEO +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif /* CONFIG_TSEC_ENET */ + +#ifdef CONFIG_QE +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_LENGTH 0x10000 +#endif /* CONFIG_QE */ + +#ifdef CONFIG_P1025RDB +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) + +#undef CONFIG_UEC_ETH +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* ETH1 */ +#define CONFIG_HAS_ETH0 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH1 */ + +#define CONFIG_UEC_ETH5 /* ETH5 */ +#define CONFIG_HAS_ETH1 + +#ifdef CONFIG_UEC_ETH5 +#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ +#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ +#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ +#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH5 */ +#endif /* CONFIG_P1025RDB */ + +/* + * Environment + */ +#ifdef CONFIG_SYS_RAMBOOT +#ifdef CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +/* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif +#endif + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ + || defined(CONFIG_FSL_SATA) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#ifdef __SW_BOOT_NOR +#define __NOR_RST_CMD \ +norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ +i2c mw 18 3 __SW_BOOT_MASK 1; reset +#endif +#ifdef __SW_BOOT_SPI +#define __SPI_RST_CMD \ +spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ +i2c mw 18 3 __SW_BOOT_MASK 1; reset +#endif +#ifdef __SW_BOOT_SD +#define __SD_RST_CMD \ +sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ +i2c mw 18 3 __SW_BOOT_MASK 1; reset +#endif +#ifdef __SW_BOOT_NAND +#define __NAND_RST_CMD \ +nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ +i2c mw 18 3 __SW_BOOT_MASK 1; reset +#endif +#ifdef __SW_BOOT_PCIE +#define __PCIE_RST_CMD \ +pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ +i2c mw 18 3 __SW_BOOT_MASK 1; reset +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"netdev=eth0\0" \ +"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ +"loadaddr=1000000\0" \ +"bootfile=uImage\0" \ +"tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ +"consoledev=ttyS0\0" \ +"ramdiskaddr=2000000\0" \ +"ramdiskfile=rootfs.ext2.gz.uboot\0" \ +"fdtaddr=c00000\0" \ +"bdev=sda1\0" \ +"jffs2nor=mtdblock3\0" \ +"norbootaddr=ef080000\0" \ +"norfdtaddr=ef040000\0" \ +"jffs2nand=mtdblock9\0" \ +"nandbootaddr=100000\0" \ +"nandfdtaddr=80000\0" \ +"ramdisk_size=120000\0" \ +"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ +"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ +MK_STR(__NOR_RST_CMD)"\0" \ +MK_STR(__SPI_RST_CMD)"\0" \ +MK_STR(__SD_RST_CMD)"\0" \ +MK_STR(__NAND_RST_CMD)"\0" \ +MK_STR(__PCIE_RST_CMD)"\0" + +#define CONFIG_NFSBOOTCOMMAND \ +"setenv bootargs root=/dev/nfs rw " \ +"nfsroot=$serverip:$rootpath " \ +"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_HDBOOT \ +"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ +"console=$consoledev,$baudrate $othbootargs;" \ +"usb start;" \ +"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ +"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ +"bootm $loadaddr - $fdtaddr" + +#define CONFIG_USB_FAT_BOOT \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"usb start;" \ +"fatload usb 0:2 $loadaddr $bootfile;" \ +"fatload usb 0:2 $fdtaddr $fdtfile;" \ +"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_USB_EXT2_BOOT \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"usb start;" \ +"ext2load usb 0:4 $loadaddr $bootfile;" \ +"ext2load usb 0:4 $fdtaddr $fdtfile;" \ +"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_NORBOOT \ +"setenv bootargs root=/dev/$jffs2nor rw " \ +"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ +"bootm $norbootaddr - $norfdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ +"setenv bootargs root=/dev/ram rw " \ +"console=$consoledev,$baudrate $othbootargs " \ +"ramdisk_size=$ramdisk_size;" \ +"tftp $ramdiskaddr $ramdiskfile;" \ +"tftp $loadaddr $bootfile;" \ +"tftp $fdtaddr $fdtfile;" \ +"bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 7bf9fc7..4ec323e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -103,14 +103,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 435b148..e0af0d2 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -92,20 +92,6 @@ #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." #endif -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ /* DDR Setup */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5f2fb1e..af62aea 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -91,14 +91,8 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00C00000 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xE0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index fc3881d..66738d5 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -109,12 +109,9 @@ #ifdef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xfdf00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 141da26..a421ba4 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -121,12 +121,10 @@ #ifdef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_FSL_DDR1 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index b6b391f..42517c9 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -78,14 +78,8 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index a74766d..202f209 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -96,14 +96,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 6588867..0c2e7ed 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -93,14 +93,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics diff --git a/include/fdt_support.h b/include/fdt_support.h index 863024f..8f06aac 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -89,7 +89,8 @@ u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); -int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle); +int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle); +int fdt_create_phandle(void *fdt, int nodeoffset); int fdt_add_edid(void *blob, const char *compat, unsigned char *buf); int fdt_verify_alias_address(void *fdt, int anode, const char *alias, diff --git a/include/fm_eth.h b/include/fm_eth.h new file mode 100644 index 0000000..c7c6882 --- /dev/null +++ b/include/fm_eth.h @@ -0,0 +1,115 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FM_ETH_H__ +#define __FM_ETH_H__ + +#include <common.h> +#include <asm/types.h> +#include <asm/fsl_enet.h> + +enum fm_port { + FM1_DTSEC1, + FM1_DTSEC2, + FM1_DTSEC3, + FM1_DTSEC4, + FM1_DTSEC5, + FM1_10GEC1, + FM2_DTSEC1, + FM2_DTSEC2, + FM2_DTSEC3, + FM2_DTSEC4, + FM2_10GEC1, + NUM_FM_PORTS, +}; + +enum fm_eth_type { + FM_ETH_1G_E, + FM_ETH_10G_E, +}; + +#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) + +#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" +#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" + +/* Fman ethernet info struct */ +#define FM_ETH_INFO_INITIALIZER(idx, pregs) \ + .fm = idx, \ + .phy_regs = (void *)pregs, \ + .enet_if = PHY_INTERFACE_MODE_NONE, \ + +#define FM_DTSEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_1G_E, \ + .port = FM##idx##_DTSEC##n, \ + .rx_port_id = RX_PORT_1G_BASE + n - 1, \ + .tx_port_id = TX_PORT_1G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, mac_1g[n-1]),\ +} + +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, mac_10g[n-1]),\ +} + +struct fm_eth_info { + u8 enabled; + u8 fm; + u8 num; + u8 phy_addr; + int index; + u16 rx_port_id; + u16 tx_port_id; + enum fm_port port; + enum fm_eth_type type; + void *phy_regs; + phy_interface_t enet_if; + u32 compat_offset; + struct mii_dev *bus; +}; + +struct tgec_mdio_info { + struct tgec_mdio_controller *regs; + char *name; +}; + +int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info); +int fm_standard_init(bd_t *bis); +void fman_enet_init(void); +void fdt_fixup_fman_ethernet(void *fdt); +phy_interface_t fm_info_get_enet_if(enum fm_port port); +void fm_info_set_phy_address(enum fm_port port, int address); +void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); +void fm_disable_port(enum fm_port port); + +#endif diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 2495b99..11d8985 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,4 +26,46 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ +/* + * Define default values for some CCSR macros to make header files cleaner* + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +#ifndef CONFIG_SYS_IMMR +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#endif + #endif /* __MPC85xx_H__ */ diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile new file mode 100644 index 0000000..8d240ea --- /dev/null +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -0,0 +1,141 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +CONFIG_SYS_TEXT_BASE_SPL := 0xff800000 +PAD_TO := 0xff802000 + +include $(TOPDIR)/config.mk + +nandobj := $(OBJTREE)/nand_spl/ + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \ + $(LDFLAGS_FINAL) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o ticks.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(nandobj)board/$(BOARDDIR) + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_ifc.c: + @rm -f $(obj)nand_boot_fsl_ifc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \ + $(obj)nand_boot_fsl_ifc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S + +$(obj)ticks.S: + @rm -f $(obj)ticks.S + ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c new file mode 100644 index 0000000..16eeb61 --- /dev/null +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -0,0 +1,130 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <mpc85xx.h> +#include <asm/io.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_law.h> + +#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } + +unsigned long ddr_freq_mhz; + +void sdram_init(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + + if (ddr_freq_mhz < 700) { + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); + out_be32(&ddr->ddr_wrlvl_cntl, + CONFIG_SYS_DDR_WRLVL_CONTROL_667); + } else { + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); + out_be32(&ddr->ddr_wrlvl_cntl, + CONFIG_SYS_DDR_WRLVL_CONTROL_800); + } + + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + + /* mimic 500us delay, with busy isync() loop */ + udelay(100); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + + set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, ddr_ratio; + unsigned long bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* Initialize the DDR3 */ + sdram_init(); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile new file mode 100644 index 0000000..475cc49 --- /dev/null +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -0,0 +1,137 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 +PAD_TO := 0xff801000 + +include $(TOPDIR)/config.mk + +nandobj := $(OBJTREE)/nand_spl/ + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ + $(LDFLAGS) $(LDFLAGS_FINAL) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(nandobj)board/$(BOARDDIR) + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c new file mode 100644 index 0000000..b9796ea --- /dev/null +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -0,0 +1,134 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> + +#define udelay(x) {int i, j; \ + for (i = 0; i < x; i++) \ + for (j = 0; j < 10000; j++) \ + ; } + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +void sdram_init(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); +#endif + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL); + + /* Set, but do not enable the memory */ + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + + set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifndef CONFIG_QE + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + +#ifndef CONFIG_QE + /* init DDR3 reset signal */ + out_be32(&pgpio->gpdir, 0x02000000); + out_be32(&pgpio->gpodr, 0x00200000); + out_be32(&pgpio->gpdat, 0x00000000); + udelay(1000); + out_be32(&pgpio->gpdat, 0x00200000); + udelay(1000); + out_be32(&pgpio->gpdir, 0x00000000); +#endif + + /* Initialize the DDR3 */ + sdram_init(); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/nand_spl/nand_boot_fsl_ifc.c b/nand_spl/nand_boot_fsl_ifc.c new file mode 100644 index 0000000..44972c5 --- /dev/null +++ b/nand_spl/nand_boot_fsl_ifc.c @@ -0,0 +1,271 @@ +/* + * NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine + * + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_ifc.h> +#include <linux/mtd/nand.h> + +static inline int is_blank(uchar *addr, int page_size) +{ + int i; + + for (i = 0; i < page_size; i++) { + if (__raw_readb(&addr[i]) != 0xff) + return 0; + } + + /* + * For the SPL, don't worry about uncorrectable errors + * where the main area is all FFs but shouldn't be. + */ + return 1; +} + +/* returns nonzero if entire page is blank */ +static inline int check_read_ecc(uchar *buf, u32 *eccstat, + unsigned int bufnum, int page_size) +{ + u32 reg = eccstat[bufnum / 4]; + int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; + + if (errors == 15) { /* uncorrectable */ + /* Blank pages fail hw ECC checks */ + if (is_blank(buf, page_size)) + return 1; + + puts("ecc error\n"); + for (;;) + ; + } + + return 0; +} + +static inline void nand_wait(uchar *buf, int bufnum, int page_size) +{ + struct fsl_ifc *ifc = IFC_BASE_ADDR; + u32 status; + u32 eccstat[4]; + int bufperpage = page_size / 512; + int bufnum_end, i; + + bufnum *= bufperpage; + bufnum_end = bufnum + bufperpage - 1; + + do { + status = in_be32(&ifc->ifc_nand.nand_evter_stat); + } while (!(status & IFC_NAND_EVTER_STAT_OPC)); + + if (status & IFC_NAND_EVTER_STAT_FTOER) { + puts("flash time out error\n"); + for (;;) + ; + } + + for (i = bufnum / 4; i <= bufnum_end / 4; i++) + eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + + for (i = bufnum; i <= bufnum_end; i++) { + if (check_read_ecc(buf, eccstat, i, page_size)) + break; + } + + out_be32(&ifc->ifc_nand.nand_evter_stat, status); +} + +static inline int bad_block(uchar *marker, int port_size) +{ + if (port_size == 8) + return __raw_readb(marker) != 0xff; + else + return __raw_readw((u16 *)marker) != 0xffff; +} + +static void nand_load(unsigned int offs, int uboot_size, uchar *dst) +{ + struct fsl_ifc *ifc = IFC_BASE_ADDR; + uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; + int page_size; + int port_size; + int pages_per_blk; + int blk_size; + int bad_marker = 0; + int bufnum_mask, bufnum; + + int csor, cspr; + int pos = 0; + int j = 0; + + int sram_addr; + int pg_no; + + /* Get NAND Flash configuration */ + csor = CONFIG_SYS_NAND_CSOR; + cspr = CONFIG_SYS_NAND_CSPR; + + if (!(csor & CSOR_NAND_ECC_DEC_EN)) { + /* soft ECC in SPL is unimplemented */ + puts("WARNING: soft ECC not checked in SPL\n"); + } else { + u32 hwcsor; + + /* make sure board is configured with ECC on boot */ + hwcsor = in_be32(&ifc->csor_cs[0].csor); + if (!(hwcsor & CSOR_NAND_ECC_DEC_EN)) + puts("WARNING: ECC not checked in SPL, " + "check board cfg\n"); + } + + port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; + + if (csor & CSOR_NAND_PGS_4K) { + page_size = 4096; + bufnum_mask = 1; + } else if (csor & CSOR_NAND_PGS_2K) { + page_size = 2048; + bufnum_mask = 3; + } else { + page_size = 512; + bufnum_mask = 15; + + if (port_size == 8) + bad_marker = 5; + } + + pages_per_blk = + 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); + + blk_size = pages_per_blk * page_size; + + /* Open Full SRAM mapping for spare are access */ + out_be32(&ifc->ifc_nand.ncfgr, 0x0); + + /* Clear Boot events */ + out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + + /* Program FIR/FCR for Large/Small page */ + if (page_size > 512) { + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + + out_be32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + } else { + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + } + + /* Program FBCR = 0 for full page read */ + out_be32(&ifc->ifc_nand.nand_fbcr, 0); + + /* Read and copy u-boot on SDRAM from NAND device, In parallel + * check for Bad block if found skip it and read continue to + * next Block + */ + while (pos < uboot_size) { + int i = 0; + do { + pg_no = offs / page_size; + bufnum = pg_no & bufnum_mask; + sram_addr = bufnum * page_size * 2; + + out_be32(&ifc->ifc_nand.row0, pg_no); + out_be32(&ifc->ifc_nand.col0, 0); + /* start read */ + out_be32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); + + /* wait for read to complete */ + nand_wait(&buf[sram_addr], bufnum, page_size); + + /* + * If either of the first two pages are marked bad, + * continue to the next block. + */ + if (i++ < 2 && + bad_block(&buf[sram_addr + page_size + bad_marker], + port_size)) { + puts("skipping\n"); + offs = (offs + blk_size) & ~(blk_size - 1); + pos &= ~(blk_size - 1); + break; + } + + for (j = 0; j < page_size; j++) + dst[pos + j] = __raw_readb(&buf[sram_addr + j]); + + pos += page_size; + offs += page_size; + } while ((offs & (blk_size - 1)) && (pos < uboot_size)); + } +} + +/* + * Main entrypoint for NAND Boot. It's necessary that SDRAM is already + * configured and available since this code loads the main U-boot image + * from NAND into SDRAM and starts from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + /* + * Load U-Boot image from NAND into RAM + */ + nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + +#ifdef CONFIG_NAND_ENV_DST + nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST); + +#ifdef CONFIG_ENV_OFFSET_REDUND + nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); +#endif +#endif + + /* + * Jump to U-Boot image + */ + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot(); +} |