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| author | Ye.Li <B37916@freescale.com> | 2014-08-13 16:44:48 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-08-15 11:07:18 +0800 |
| commit | 01996acd7788c831fc06872c59af99f3bd6f6b03 (patch) | |
| tree | c27452e185444a6d34cd5563c9b06398c335a0a8 | |
| parent | c3e9e81a4c6ae7306c273cbe4b5d96ef44222711 (diff) | |
| download | u-boot-imx-01996acd7788c831fc06872c59af99f3bd6f6b03.zip u-boot-imx-01996acd7788c831fc06872c59af99f3bd6f6b03.tar.gz u-boot-imx-01996acd7788c831fc06872c59af99f3bd6f6b03.tar.bz2 | |
ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before reset
u-boot v2014 upstream codes have a problem in pfd reset (s_init function)
that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by
using dynamical cpu type checking and introducing two cpu types:
MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform.
Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk
of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock
source, do not reset this PFD to avoid system hang.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index fa1d6e6..50c867c 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -734,10 +734,11 @@ enum boot_device get_boot_device(void) void s_init(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int is_6q = is_cpu_type(MXC_CPU_MX6Q); + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int is_6sx = is_cpu_type(MXC_CPU_MX6SX); u32 mask480; u32 mask528; + u32 reg, periph1, periph2; /* Don't reset PFD for MX6SX */ if (is_6sx) @@ -753,15 +754,23 @@ void s_init(void) ANATOP_PFD_CLKGATE_MASK(1) | ANATOP_PFD_CLKGATE_MASK(2) | ANATOP_PFD_CLKGATE_MASK(3); - mask528 = ANATOP_PFD_CLKGATE_MASK(0) | - ANATOP_PFD_CLKGATE_MASK(1) | + mask528 = ANATOP_PFD_CLKGATE_MASK(1) | ANATOP_PFD_CLKGATE_MASK(3); - /* - * Don't reset PFD2 on DL/S - */ - if (is_6q) + reg = readl(&ccm->cbcmr); + periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); + periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); + + /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ + if ((periph2 != 0x2) && (periph1 != 0x2)) + mask528 |= ANATOP_PFD_CLKGATE_MASK(0); + + if ((periph2 != 0x1) && (periph1 != 0x1) && + (periph2 != 0x3) && (periph1 != 0x3)) mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); writel(mask528, &anatop->pfd_528_set); writel(mask480, &anatop->pfd_480_clr); |