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| author | Simon Glass <sjg@chromium.org> | 2012-04-05 11:55:15 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:39 +0200 |
| commit | d376e8d2283fc82d7366bc9c0e96110e3e5665e9 (patch) | |
| tree | bfc829ac93830fc29b71b7eee075efddfceb27a3 | |
| parent | e31c1e50ac8d85ede3f62c438034397ba54734d7 (diff) | |
| download | u-boot-imx-d376e8d2283fc82d7366bc9c0e96110e3e5665e9.zip u-boot-imx-d376e8d2283fc82d7366bc9c0e96110e3e5665e9.tar.gz u-boot-imx-d376e8d2283fc82d7366bc9c0e96110e3e5665e9.tar.bz2 | |
tegra: fdt: Add EMC data for Tegra2 Seaboard
This adds timings for T20 and T25 Seaboards, using the bindings found here:
http://patchwork.ozlabs.org/patch/132928/
We supply both full speed options for normal running, and half speed options
for testing / development.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
| -rw-r--r-- | board/nvidia/dts/tegra2-seaboard.dts | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts index 6ba3ec4..08ada8c 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -89,4 +89,41 @@ i2c@7000c500 { clock-frequency = <100000>; }; + + emc@7000f400 { + emc-table@190000 { + reg = < 190000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 190000 >; + nvidia,emc-registers = < 0x0000000c 0x00000026 + 0x00000009 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x0000059f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000b 0x000000c8 + 0x00000003 0x00000007 0x00000004 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xa06204ae + 0x007dc010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + emc-table@380000 { + reg = < 380000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 380000 >; + nvidia,emc-registers = < 0x00000017 0x0000004b + 0x00000012 0x00000006 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000b5f + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe044048b + 0x007d8010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + }; }; |