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authorIan Campbell <ijc@hellion.org.uk>2012-01-12 06:10:22 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-02-12 10:11:27 +0100
commit3f8435516b1c27c7fdf75ace1de1391d119c65c4 (patch)
tree61daea49bdd803d2b08325d04a1a388e3003af15
parent3d3206f1d44c73bcc4ad9fd8c201cd9fcfa07be7 (diff)
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kirkwood_spi: correct access to irq_mask register
Problem appears to have been present since day one but masked because alignment aborts were not enabled. ca4b55800ed7 "arm, arm926ejs: always do cpu critical inits" turned on alignment aborts and uncovered this latent problem. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Jason Cooper <u-boot@lakedaemon.net> Tested-By: Holger Brunck <holger.brunck@keymile.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
-rw-r--r--drivers/spi/kirkwood_spi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index dfe542d..db8ba8b 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -66,7 +66,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
debug("data = 0x%08x \n", data);
writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
- writel(KWSPI_IRQMASK, spireg->irq_mask);
+ writel(KWSPI_IRQMASK, &spireg->irq_mask);
/* program mpp registers to select SPI_CSn */
if (cs) {