Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

16 files changed, 994 insertions, 166 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 5a5b9bd..07541bd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -146,6 +146,7 @@ Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
 	dlvision        PPC405EP
+	dlvision-10g	PPC405EP
 	gdppc440etx	PPC440EP/GR
 	intip		PPC460EX
 	io		PPC405EP
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2e218de..a33ca2f 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -172,6 +172,9 @@ typedef	struct	global_data {
 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
 	unsigned long kbd_status;
 #endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
 #if defined(CONFIG_WD_MAX_RATE)
 	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
 #endif
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd233..86a3ec8 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,8 +26,9 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
 
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
 
 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
@@ -36,8 +37,29 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
 int board_early_init_f(void)
 {
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->fpga_state[k] = 0;
+
 	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
 	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
@@ -66,10 +88,18 @@ int board_early_init_f(void)
 
 	/*
 	 * wait for fpga-done
-	 * fail ungraceful if fpga is not configuring properly
 	 */
-	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
-		;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!(in_le16((void *)LATCH2_BASE)
+			& CONFIG_SYS_FPGA_DONE(k))) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
 
 	/*
 	 * setup io-latches for boot (stop reset)
@@ -78,15 +108,25 @@ int board_early_init_f(void)
 	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 
-	/*
-	 * wait for fpga out of reset
-	 * fail ungraceful if fpga is not working properly
-	 */
-	while (1) {
-		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
-		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
-			REFLECTION_TESTPATTERN_INV)
-			break;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			out_le16(&fpga->reflection_low,
+				REFLECTION_TESTPATTERN);
+			if (in_le16(&fpga->reflection_high) ==
+				REFLECTION_TESTPATTERN_INV)
+				break;
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
 	}
 
 	return 0;
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index ed31207..169418c 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS-$(CONFIG_IO) += io.o
 COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
 
 COBJS   := $(BOARD).o $(COBJS-y)
 SOBJS   =
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 0000000..df7fb14
--- /dev/null
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+enum {
+	UNITTYPE_VIDEO_USER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+	HWVER_101 = 0,
+	HWVER_110 = 1,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_156250 = 2,
+};
+
+enum {
+	RAM_NONE = 0,
+	RAM_DDR2_32 = 1,
+	RAM_DDR2_64 = 2,
+};
+
+static void print_fpga_info(unsigned dev)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_rs232;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+	int fpga_state = get_fpga_state(dev);
+
+	printf("FPGA%d: ", dev);
+
+	hardware_version = versions & 0x000f;
+
+	if (fpga_state
+	    && !((hardware_version == HWVER_101)
+		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+		puts("not available\n");
+		print_fpga_state(dev);
+		return;
+	}
+
+	unit_type = (versions >> 4) & 0x000f;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features >> 13) & 0x0003;
+	feature_rs232 = fpga_features & (1<<11);
+	feature_audio = (fpga_features >> 9) & 0x0003;
+	feature_sysclock = (fpga_features >> 7) & 0x0003;
+	feature_ramconfig = (fpga_features >> 5) & 0x0003;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features >> 2) & 0x0003;
+	feature_video_channels = fpga_features & 0x0003;
+
+	switch (unit_type) {
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel Userside");
+		break;
+
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel Userside");
+		break;
+
+	case UNITTYPE_VIDEO_SERVER:
+		printf("Videochannel Serverside");
+		break;
+
+	case UNITTYPE_MAIN_SERVER:
+		printf("Mainchannel Serverside");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_101:
+		printf(" HW-Ver 1.01\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	switch (feature_sysclock) {
+	case SYSCLK_156250:
+		printf(", clock 156.25 MHz");
+		break;
+
+	default:
+		printf(", clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_ramconfig) {
+	case RAM_NONE:
+		printf("no RAM");
+		break;
+
+	case RAM_DDR2_32:
+		printf("RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR2_64:
+		printf("RAM 64 bit DDR2");
+		break;
+
+	default:
+		printf("RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+		feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	unsigned k;
+	char *s = getenv("serial#");
+
+	printf("Board: ");
+
+	printf("DLVision 10G");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		print_fpga_info(k);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
+		if (!get_fpga_state(k)
+		    || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
+			osd_probe(k);
+
+	return 0;
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 80877b6..0974019 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -29,7 +29,7 @@
 
 #include <miiphy.h>
 
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
 
 #define PHYREG_CONTROL				0
 #define PHYREG_PAGE_ADDRESS			22
@@ -37,13 +37,6 @@
 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
 
 enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_FEATURES = 0x0004,
-	REG_FPGA_VERSION = 0x0006,
-	REG_QUAD_SERDES_RESET = 0x0012,
-};
-
-enum {
 	UNITTYPE_CCD_SWITCH = 1,
 };
 
@@ -94,10 +87,11 @@ err_out:
  */
 int checkboard(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_channels;
@@ -166,6 +160,7 @@ int checkboard(void)
  */
 int last_stage_init(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	unsigned int k;
 
 	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
@@ -175,7 +170,7 @@ int last_stage_init(void)
 		configure_gbit_phy(k);
 
 	/* take fpga serdes blocks out of reset */
-	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+	out_le16(&fpga->quad_serdes_reset, 0);
 
 	return 0;
 }
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ecd6cb2..20770e4 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -27,14 +27,9 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
-#include "../common/fpga.h"
-#include "../common/osd.h"
+#include <gdsys_fpga.h>
 
-enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_VERSION = 0x0004,
-	REG_FPGA_FEATURES = 0x0006,
-};
+#include "../common/osd.h"
 
 enum {
 	UNITTYPE_MAIN_SERVER = 0,
@@ -74,10 +69,11 @@ enum {
  */
 int checkboard(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_compression;
@@ -214,7 +210,7 @@ int checkboard(void)
 
 int last_stage_init(void)
 {
-	return osd_probe();
+	return osd_probe(0);
 }
 
 /*
@@ -222,15 +218,15 @@ int last_stage_init(void)
  */
 void fpga_gpio_set(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
 }
 
 void fpga_gpio_clear(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
 }
 
 int fpga_gpio_get(int pin)
 {
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 2257037..4c7fc99 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -31,6 +31,7 @@ LIB	= $(obj)lib$(VENDOR).o
 
 COBJS-$(CONFIG_IO) += miiphybb.o
 COBJS-$(CONFIG_IOCON) += osd.o
+COBJS-$(CONFIG_DLVISION_10G) += osd.o
 
 COBJS   := $(COBJS-y)
 SOBJS   =
diff --git a/board/gdsys/common/fpga.h b/board/gdsys/common/fpga.h
deleted file mode 100644
index c1434e7..0000000
--- a/board/gdsys/common/fpga.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _FPGA_H_
-#define _FPGA_H_
-
-static inline u16 fpga_get_reg(unsigned reg)
-{
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
-}
-
-static inline void fpga_set_reg(unsigned reg, u16 val)
-{
-	return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
-}
-
-#endif
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 239c870..4d8c046 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -25,10 +25,16 @@
 #include <i2c.h>
 #include <asm/io.h>
 
-#include "fpga.h"
+#include <gdsys_fpga.h>
 
 #define CH7301_I2C_ADDR 0x75
 
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
 #define PIXCLK_640_480_60 25180000
 
 #define BASE_WIDTH 32
@@ -36,17 +42,6 @@
 #define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
 
 enum {
-	REG_CONTROL = 0x0010,
-	REG_MPC3W_CONTROL = 0x001a,
-	REG_VIDEOCONTROL = 0x0042,
-	REG_OSDVERSION = 0x0100,
-	REG_OSDFEATURES = 0x0102,
-	REG_OSDCONTROL = 0x0104,
-	REG_XY_SIZE = 0x0106,
-	REG_VIDEOMEM = 0x0800,
-};
-
-enum {
 	CH7301_CM = 0x1c,		/* Clock Mode Register */
 	CH7301_IC = 0x1d,		/* Input Clock Register */
 	CH7301_GPIO = 0x1e,		/* GPIO Control Register */
@@ -67,6 +62,41 @@ enum {
 	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
 };
 
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	ihs_i2c_t *i2c = &fpga->i2c;
+
+	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+		;
+	out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
+	out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	ihs_i2c_t *i2c = &fpga->i2c;
+	unsigned int ctr = 0;
+
+	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+		;
+	out_le16(&fpga->extended_interrupt, 1 << 14);
+	out_le16(&i2c->write_mailbox_ext, reg);
+	out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
+	while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
+		udelay(100000);
+		if (ctr++ > 5) {
+			printf("iic receive timeout\n");
+			break;
+		}
+	}
+	return in_le16(&i2c->read_mailbox_ext) >> 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
 static void mpc92469ac_calc_parameters(unsigned int fout,
 	unsigned int *post_div, unsigned int *feedback_div)
 {
@@ -92,8 +122,9 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
 	*feedback_div = m;
 }
 
-static void mpc92469ac_set(unsigned int fout)
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
 	unsigned int n;
 	unsigned int m;
 	unsigned int bitval = 0;
@@ -114,17 +145,85 @@ static void mpc92469ac_set(unsigned int fout)
 		break;
 	}
 
-	fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+	out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
 }
+#endif
 
-static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+#ifdef CONFIG_SYS_ICS8N3QV01
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+	unsigned int *_mint, unsigned int *_mfrac,
+	unsigned int *_n)
 {
+	unsigned int n;
+	unsigned int foutiic;
+	unsigned int fvcoiic;
+	unsigned int mint;
+	unsigned long long mfrac;
+
+	n = 2550000000U / fout;
+	if ((n & 1) && (n > 5))
+		n -= 1;
+
+	foutiic = fout - (fout / 10000);
+	fvcoiic = foutiic * n;
+
+	mint = fvcoiic / 114285000;
+	if ((mint < 17) || (mint > 63))
+		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+		/ 114285000LL;
+
+	*_mint = mint;
+	*_mfrac = mfrac;
+	*_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int mint;
+	unsigned int mfrac;
+	u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+	ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
+
+	reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+	reg0 |= (mint & 0x1f) << 1;
+	reg0 |= (mfrac >> 17) & 0x01;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+	reg4 = mfrac >> 9;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+	reg8 = mfrac >> 1;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+	reg12 = mfrac << 7;
+	reg12 |= n & 0x7f;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+	reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+	reg18 |= 0x20;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+	reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+	reg20 |= mint & (1 << 5);
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+	u16 *data, size_t charcount)
+{
+	ihs_fpga_t *fpga =
+		(ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
 	unsigned int k;
 
 	for (k = 0; k < charcount; ++k) {
 		if (offset + k >= BUFSIZE)
 			return -1;
-		fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+		out_le16(&fpga->videomem + offset + k, data[k]);
 	}
 
 	return charcount;
@@ -132,46 +231,59 @@ static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
 
 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	unsigned x;
-	unsigned y;
-	unsigned charcount;
-	unsigned len;
-	u8 color;
-	unsigned int k;
-	u16 buf[BUFSIZE];
-	char *text;
-
-	if (argc < 5) {
-		return cmd_usage(cmdtp);
+	unsigned screen;
+
+	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned charcount;
+		unsigned len;
+		u8 color;
+		unsigned int k;
+		u16 buf[BUFSIZE];
+		char *text;
+		int res;
+
+		if (argc < 5) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		color = simple_strtoul(argv[3], NULL, 16);
+		text = argv[4];
+		charcount = strlen(text);
+		len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+		for (k = 0; k < len; ++k)
+			buf[k] = (text[k] << 8) | color;
+
+		res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
+		if (res < 0)
+			return res;
 	}
 
-	x = simple_strtoul(argv[1], NULL, 16);
-	y = simple_strtoul(argv[2], NULL, 16);
-	color = simple_strtoul(argv[3], NULL, 16);
-	text = argv[4];
-	charcount = strlen(text);
-	len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
-
-	for (k = 0; k < len; ++k)
-		buf[k] = (text[k] << 8) | color;
-
-	return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+	return 0;
 }
 
-int osd_probe(void)
+int osd_probe(unsigned screen)
 {
-	u8 value;
-	u16 version = fpga_get_reg(REG_OSDVERSION);
-	u16 features = fpga_get_reg(REG_OSDFEATURES);
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	ihs_osd_t *osd = &fpga->osd;
+	u16 version = in_le16(&osd->version);
+	u16 features = in_le16(&osd->features);
 	unsigned width;
 	unsigned height;
+	u8 value;
 
 	width = ((features & 0x3f00) >> 8) + 1;
 	height = (features & 0x001f) + 1;
 
-	printf("OSD:   Digital-OSD version %01d.%02d, %d" "x%d characters\n",
-		version/100, version%100, width, height);
+	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+		screen, version/100, version%100, width, height);
 
+#ifdef CONFIG_SYS_CH7301
 	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
 	if (value != 0x17) {
 		printf("       Probing CH7301 failed, DID %02x\n", value);
@@ -182,51 +294,86 @@ int osd_probe(void)
 	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
 	i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
 	i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+	mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
 
-	mpc92469ac_set(PIXCLK_640_480_60);
-	fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
-	fpga_set_reg(REG_OSDCONTROL, 0x0049);
+#ifdef CONFIG_SYS_ICS8N3QV01
+	ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#endif
 
-	fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+#ifdef CONFIG_SYS_SIL1178
+	value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+	if (value != 0x06) {
+		printf("       Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+		return -1;
+	}
+	/* magic initialization sequence adapted from datasheet */
+	fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+#endif
+
+	out_le16(&fpga->videocontrol, 0x0002);
+	out_le16(&osd->control, 0x0049);
+
+	out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
 
 	return 0;
 }
 
 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	unsigned x;
-	unsigned y;
-	unsigned k;
-	u16 buffer[BASE_WIDTH];
-	char *rp;
-	u16 *wp = buffer;
-	unsigned count = (argc > 4) ?  simple_strtoul(argv[4], NULL, 16) : 1;
-
-	if ((argc < 4) || (strlen(argv[3]) % 4)) {
-		return cmd_usage(cmdtp);
-	}
-
-	x = simple_strtoul(argv[1], NULL, 16);
-	y = simple_strtoul(argv[2], NULL, 16);
-	rp = argv[3];
-
-
-	while (*rp) {
-		char substr[5];
-
-		memcpy(substr, rp, 4);
-		substr[4] = 0;
-		*wp = simple_strtoul(substr, NULL, 16);
-
-		rp += 4;
-		wp++;
-		if (wp - buffer > BASE_WIDTH)
-			break;
-	}
-
-	for (k = 0; k < count; ++k) {
-		unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
-		osd_write_videomem(offset, buffer, wp - buffer);
+	unsigned screen;
+
+	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned k;
+		u16 buffer[BASE_WIDTH];
+		char *rp;
+		u16 *wp = buffer;
+		unsigned count = (argc > 4) ?
+			simple_strtoul(argv[4], NULL, 16) : 1;
+
+		if ((argc < 4) || (strlen(argv[3]) % 4)) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		rp = argv[3];
+
+
+		while (*rp) {
+			char substr[5];
+
+			memcpy(substr, rp, 4);
+			substr[4] = 0;
+			*wp = simple_strtoul(substr, NULL, 16);
+
+			rp += 4;
+			wp++;
+			if (wp - buffer > BASE_WIDTH)
+				break;
+		}
+
+		for (k = 0; k < count; ++k) {
+			unsigned offset =
+				y * BASE_WIDTH + x + k * (wp - buffer);
+			osd_write_videomem(screen, offset, buffer,
+				wp - buffer);
+		}
 	}
 
 	return 0;
diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h
index 4431cbc..c59d9c3 100644
--- a/board/gdsys/common/osd.h
+++ b/board/gdsys/common/osd.h
@@ -24,6 +24,6 @@
 #ifndef _OSD_H_
 #define _OSD_H_
 
-int osd_probe(void);
+int osd_probe(unsigned screen);
 
 #endif
diff --git a/boards.cfg b/boards.cfg
index c977528..59d4a41 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -717,6 +717,7 @@ VOM405                       powerpc     ppc4xx      vom405              esd
 WUH405                       powerpc     ppc4xx      wuh405              esd
 devconcenter                 powerpc     ppc4xx      intip               gdsys          -           intip:DEVCONCENTER
 dlvision                     powerpc     ppc4xx      -                   gdsys
+dlvision-10g                 powerpc     ppc4xx      405ep               gdsys
 gdppc440etx                  powerpc     ppc4xx      -                   gdsys
 intip                        powerpc     ppc4xx      intip               gdsys          -           intip:INTIB
 io                           powerpc     ppc4xx      405ep               gdsys
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
new file mode 100644
index 0000000..f7609d7
--- /dev/null
+++ b/include/configs/dlvision-10g.h
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_DLVISION_10G	1	/*  on a DLVision-10G board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		dlvsion-10g
+#define CONFIG_IDENT_STRING	" dlvision-10g 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
+#define CONFIG_SYS_FPGA1_BASE		0x7f200000
+#define CONFIG_SYS_LATCH_BASE		0x7f300000
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+	(k ? 0x2000 : 0x1000)
+
+#define CONFIG_SYS_FPGA_COUNT		2
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffcf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(7)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(2)		|	\
+				 EBC_BXAP_WBF_ENCODE(2)		|	\
+				 EBC_BXAP_TH_ENCODE(4)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+				 EBC_BXCR_BS_64MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (FPGA0) */
+#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 2 (FPGA1) */
+#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(6)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(4)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(1)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(2)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/io.h b/include/configs/io.h
index a66c704..9d2a87d 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -229,13 +229,15 @@
 #define CONFIG_SYS_EBC_PB1CR		0x7f318000
 
 /* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02025080
 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 #define CONFIG_SYS_EBC_PB2CR		0x7f11a000
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x3ffe
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5e61b11..9fcc643 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -131,6 +131,12 @@ int fpga_gpio_get(int pin);
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
 /*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
+/*
  * FLASH organization
  */
 #define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
@@ -231,13 +237,15 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_EBC_PB1AP		0x92015480
 #define CONFIG_SYS_EBC_PB1CR		0xFB858000
 
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02825080
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x00fe
+#define CONFIG_SYS_FPGA_COUNT		1
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
@@ -249,4 +257,11 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_LATCH1_RESET		0xffff
 #define CONFIG_SYS_LATCH1_BOOT		0xffff
 
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
 #endif	/* __CONFIG_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
new file mode 100644
index 0000000..1fccd27
--- /dev/null
+++ b/include/gdsys_fpga.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GDSYS_FPGA_H
+#define __GDSYS_FPGA_H
+
+enum {
+	FPGA_STATE_DONE_FAILED = 1 << 0,
+	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+};
+
+int get_fpga_state(unsigned dev);
+void print_fpga_state(unsigned dev);
+
+typedef struct ihs_gpio {
+	u16 read;
+	u16 clear;
+	u16 set;
+} ihs_gpio_t;
+
+typedef struct ihs_i2c {
+	u16 write_mailbox;
+	u16 write_mailbox_ext;
+	u16 read_mailbox;
+	u16 read_mailbox_ext;
+} ihs_i2c_t;
+
+typedef struct ihs_osd {
+	u16 version;
+	u16 features;
+	u16 control;
+	u16 xy_size;
+} ihs_osd_t;
+
+#ifdef CONFIG_IO
+typedef struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[5];	/* 0x0008 */
+	u16 quad_serdes_reset;	/* 0x0012 */
+	u16 reserved_1[8181];	/* 0x0014 */
+	u16 reflection_high;	/* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
+#ifdef CONFIG_IOCON
+typedef struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[6];	/* 0x0008 */
+	ihs_gpio_t gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_1[19];	/* 0x001c */
+	u16 videocontrol;	/* 0x0042 */
+	u16 reserved_2[93];	/* 0x0044 */
+	u16 reflection_high;	/* 0x00fe */
+	ihs_osd_t osd;		/* 0x0100 */
+	u16 reserved_3[892];	/* 0x0108 */
+	u16 videomem;		/* 0x0800 */
+} ihs_fpga_t;
+#endif
+
+#ifdef CONFIG_DLVISION_10G
+typedef struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[10];	/* 0x0008 */
+	u16 extended_interrupt; /* 0x001c */
+	u16 reserved_1[9];	/* 0x001e */
+	ihs_i2c_t i2c;		/* 0x0030 */
+	u16 reserved_2[35];	/* 0x0038 */
+	u16 reflection_high;	/* 0x007e */
+	u16 reserved_3[15];	/* 0x0080 */
+	u16 videocontrol;	/* 0x009e */
+	u16 reserved_4[176];	/* 0x00a0 */
+	ihs_osd_t osd;		/* 0x0200 */
+	u16 reserved_5[764];	/* 0x0208 */
+	u16 videomem;		/* 0x0800 */
+} ihs_fpga_t;
+#endif
+
+#endif