Add (some) definitions for the MPC85xx local bus controller

Patch by Murray Jensen, 08 Jul 2005

2 files changed, 38 insertions, 0 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 48d30f6..27ce62c 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add (some) definitions for the MPC85xx local bus controller
+  Patch by Murray Jensen, 08 Jul 2005
+
 * Add CPM2 I/O pin functions for MPC85xx processors
   Patch by Murray Jensen, 08 Jul 2005
 
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 60b6c61..a4d99b2 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -25,4 +25,39 @@
 #define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
 #define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
 
+/*
+ * Local Bus Controller - memory controller registers
+ */
+#define BRx_V		0x00000001	/* Bank Valid			*/
+#define BRx_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select	*/
+#define BRx_MS_SDRAM	0x00000000	/* SDRAM Machine Select		*/
+#define BRx_MS_UPMA	0x00000080	/* U.P.M.A Machine Select	*/
+#define BRx_MS_UPMB	0x000000a0	/* U.P.M.B Machine Select	*/
+#define BRx_MS_UPMC	0x000000c0	/* U.P.M.C Machine Select	*/
+#define BRx_PS_8	0x00000800	/*  8 bit port size		*/
+#define BRx_PS_32	0x00001800	/* 32 bit port size		*/
+#define BRx_BA_MSK	0xffff8000	/* Base Address Mask		*/
+
+#define ORxG_EAD	0x00000001	/* External addr latch delay	*/
+#define ORxG_EHTR	0x00000002	/* Extended hold time on read	*/
+#define ORxG_TRLX	0x00000004	/* Timing relaxed		*/
+#define ORxG_SETA	0x00000008	/* External address termination	*/
+#define ORxG_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states	*/
+#define ORxG_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states	*/
+#define ORxG_XACS	0x00000100	/* Extra addr to CS setup	*/
+#define ORxG_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later*/
+#define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
+
+#define ORxU_BI		0x00000100	/* Burst Inhibit		*/
+#define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
+
+#define MxMR_OP_NORM	0x00000000	/* Normal Operation		*/
+#define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
+#define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
+#define MxMR_BSEL	0x80000000	/* Bus Select			*/
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
+
 #endif	/* __MPC85xx_H__ */