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| author | Kumar Gala <galak@kernel.crashing.org> | 2006-01-12 19:53:39 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2006-01-12 19:53:39 -0600 |
| commit | b443f7b628bf9e9ba9cd93589c1fea8b908edd22 (patch) | |
| tree | 793245b970d33b892d251558e494c236e5dd842e | |
| parent | 06508f1c9b35ed16f42b3dfe99f9b1182b4ec82e (diff) | |
| parent | 86902b8e36f86c8675be6b759c2a8ced50805f64 (diff) | |
| download | u-boot-imx-b443f7b628bf9e9ba9cd93589c1fea8b908edd22.zip u-boot-imx-b443f7b628bf9e9ba9cd93589c1fea8b908edd22.tar.gz u-boot-imx-b443f7b628bf9e9ba9cd93589c1fea8b908edd22.tar.bz2 | |
Merge branch 'mpc8349ads'
| -rw-r--r-- | CHANGELOG | 1 | ||||
| -rw-r--r-- | board/mpc8349ads/pci.c | 37 | ||||
| -rw-r--r-- | include/configs/MPC8349ADS.h | 6 |
3 files changed, 18 insertions, 26 deletions
@@ -2,7 +2,6 @@ Changes since U-Boot 1.1.4: ====================================================================== -<<<<<<< HEAD/CHANGELOG * Fixed PCI indirect config ops to handle multiple PCI controllers We need to adjust the bus number we are trying to access based on which PCI controller its on diff --git a/board/mpc8349ads/pci.c b/board/mpc8349ads/pci.c index f3c7f53..6cafbaa 100644 --- a/board/mpc8349ads/pci.c +++ b/board/mpc8349ads/pci.c @@ -136,6 +136,7 @@ pci_init_board(void) volatile pciconf8349_t * pci_conf; u16 reg16; u32 reg32; + u32 dev; struct pci_controller * hose; immr = (immap_t *)CFG_IMMRBAR; @@ -200,7 +201,7 @@ pci_init_board(void) /* PCI1 IO space */ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI1 mmio - non-prefetch mem space */ pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; @@ -261,21 +262,17 @@ pci_init_board(void) * Write to Command register */ reg16 = 0xff; - pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, - ®16); + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, - reg16); + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, - 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, - 0x80); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE, - 0x08); + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); @@ -300,7 +297,7 @@ pci_init_board(void) /* PCI2 IO space */ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI2 mmio - non-prefetch mem space */ pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; @@ -361,21 +358,17 @@ pci_init_board(void) * Write to Command register */ reg16 = 0xff; - pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, - ®16); + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, - reg16); + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, - 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, - 0x80); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE, - 0x08); + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); /* * Hose scan. diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h index ab7c890..d273fce 100644 --- a/include/configs/MPC8349ADS.h +++ b/include/configs/MPC8349ADS.h @@ -332,7 +332,7 @@ #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE @@ -341,8 +341,8 @@ #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe3000000 -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define PCI_ALL_PCI1 |