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| author | Minkyu Kang <mk7.kang@samsung.com> | 2010-05-31 09:13:11 +0900 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2010-05-31 09:13:11 +0900 |
| commit | 922d27b596c179c5a7d68abe45ede5adb1b6589c (patch) | |
| tree | c5ef3d5dc70bf51646a7fd7a379f6c2b2588cc2e | |
| parent | de200874fb9ecac51d74b4e9783ebb5d2e94c449 (diff) | |
| parent | 39c209546ab5b11ca6410c5cc57dcbf457e50800 (diff) | |
| download | u-boot-imx-922d27b596c179c5a7d68abe45ede5adb1b6589c.zip u-boot-imx-922d27b596c179c5a7d68abe45ede5adb1b6589c.tar.gz u-boot-imx-922d27b596c179c5a7d68abe45ede5adb1b6589c.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
arch/arm/include/asm/mach-types.h
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
154 files changed, 11352 insertions, 1775 deletions
@@ -1,3 +1,3592 @@ +commit c7da8c19b5f7fd58b5b4b1d247648851af56e1f0 +Author: Andreas Biessmann <andreas.devel@googlemail.com> +Date: Sat May 22 13:17:21 2010 +0200 + + config.mk: use different host compiler for OS X 10.6 + + Compiling tools subdirectory on Mac OS X 10.6 (Snow Leopard) complains about + wrong syntax in system includes. + + In file included from /usr/include/stdio.h:444, + from ../source/u-boot/include/compiler.h:26, + from ../source/u-boot/lib/crc32.c:15: + /usr/include/secure/_stdio.h:46: error: syntax error in macro parameter list + + This can be fixed by reverting the workaround for prior OS X releases in + config.mk conditionally for OS X 10.6+. + + Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> + Acked-by: Mike Frysinger <vapier@gentoo.org> + +commit 6ece2550d1c0c5c811b302b1639ea35c2e485203 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri May 21 04:17:48 2010 -0500 + + Convert Makefiles from COBJS-${} to COBJS-$() + + Match style we use almost everywhere else + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 59dde44acb82e571808190ccd3cd6b82dc9d7001 +Author: Michael Weiss <michael.weiss@ifm.com> +Date: Thu May 20 16:09:35 2010 +0200 + + powerpc/bootcount: Fix endianness problem + + For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem. + + Signed-off-by: Michael Weiss <michael.weiss@ifm.com> + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit d74dda09f0178079705ee1d641444bac44d3ecd9 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed May 26 22:19:35 2010 +0200 + + dm9000x.c: fix compile problems + + Use readX() / writeX() accessors instead of inX() / outX(). + + Suggested-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 40792d675a609c83621d098e48a89de07463b3cd +Author: Wolfgang Denk <wd@denx.de> +Date: Fri May 21 23:14:53 2010 +0200 + + a320evb: fix udelay / __udelay confusion + + Fix the following compiler problems: + + arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay': + /home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay' + lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here + lib/libgeneric.a(time.o): In function `udelay': + time.c:(.text+0x1c): undefined reference to `__udelay' + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 92381c41c718d260476d5c636c473f50e3b5a79c +Author: Wolfgang Denk <wd@denx.de> +Date: Fri May 21 23:13:18 2010 +0200 + + ARM: */timer.c: fix spelling and vertical alignment + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 3f786bb8542ee85ea898152b40b1f0d98f0801df +Author: Mahavir Jain <[mjain@marvell.com]> +Date: Fri May 21 14:37:48 2010 +0530 + + bugfix: Guruplug: Use standard miiphy + + call to reset PHY chip. + + Current PHY Software Reset operation in guruplug does not + poll reset bit in control register to go to 0(auto clearing) + for making sure reset was successful.This patch uses standard + miiphy call miiphy_reset to make sure proper PHY reset operation. + + Signed-off-by: Mahavir Jain <mjain@marvell.com> + +commit 71bd860cce4493c5def07804723661e75271052b +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed May 19 17:06:46 2010 -0500 + + mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c + + commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: + retain POR values of non-configured ACR, SPCR, SCCR, and LCRR + bitfields" incorrectly shifted <register>_<bitfield> (e.g. + ACR_PIPE_DEP) values that were preshifted by their + definition in mpc83xx.h. + + this patch removes the unnecessary shifting for the newly + utilized mask values in cpu_init.c, and prevents seemingly + unrelated symptoms such as an mpc8379erdb board from + locking up whilst performing a networking operation, + e.g. a tftp. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit f6970d0c545b9134af3b347c75ee3d13545b36d8 +Author: Horst Kronstorfer <hkronsto@frequentis.com> +Date: Tue May 18 10:37:05 2010 +0200 + + Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S. + + Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 445093d175b06226549680b6894923bb0f5e50fa +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Nov 17 21:27:39 2009 +0100 + + Fix "par[t]ition" typo. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit bdc5f06789c5a0c3a9a2c0eb33ec4d177dbdaa22 +Author: Stefan Roese <sr@denx.de> +Date: Mon May 17 10:01:05 2010 +0200 + + UBI: Fix problem in UBI/Linux "compatibility layer" + + "down_write_trylock" needs to return 1 instead of 0 for success. + Otherwise copying a block with a read error (e.g. bit-flip on read) + won't work correctly. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 1b1f9a9d00447d9eab32ae5633f60a106196b75f +Author: Stefan Roese <sr@denx.de> +Date: Mon May 17 10:00:51 2010 +0200 + + UBI: Ensure that "background thread" operations are really executed + + The current U-Boot UBI implementation is copied from Linux. In this + porting the UBI background thread was not handled correctly. Upon write + operations ubi_wl_flush() makes sure, that all queued operations, like + page-erase, are completed. But this is missing for read operations. + + This patch now makes sure that such operations (like scrubbing upon + bit-flip errors) are not queued, but executed directly. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 03af5abd85637d27e96fb999ce6e3992293570b0 +Author: Stefano Babic <sbabic@denx.de> +Date: Thu May 13 10:26:40 2010 +0200 + + MX31: Added support for the Casio COM57H5M10XRC to QONG + + The patch adds setup to connect a CASIO COM57H5M10XRC + (640x480 TFT display) to the QONG module. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 2f05e394fccf62a4693c6b8323de725f90d1f003 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon May 17 23:34:18 2010 +0200 + + fsl_diu_fb.c: fix build warnings + + Commit 15351855 "fsl-diu: Using I/O accessor to CCSR space" caused a + number of "passing argument 2 of 'out_be32' makes integer from pointer + without a cast" warnings; fix these. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Cc: Dave Liu <daveliu@freescale.com> + Cc: Jerry Huang <Chang-Ming.Huang@freescale.com> + Cc: Kumar Gala <galak@kernel.crashing.org> + +commit f2d76ae4fdde180e120ea2d29d6ef881360b3cba +Author: Nick Thompson <nick.thompson@ge.com> +Date: Tue May 11 11:29:52 2010 +0100 + + Avoid use of divides in print_size + + Modification of print_size to avoid use of divides and especially + long long divides. Keep the binary scale factor in terms of bit + shifts instead. This should be faster, since the previous code + gave the compiler no clues that the divides where always powers + of two, preventing optimisation. + + Signed-off-by: Nick Thompson <nick.thompson@ge.com> + Acked-by: Timur Tabi <timur@freescale.com> + +commit a599cde7698acc5ae3d0f731b4a7d63a931aae63 +Author: Serge Ziryukin <ftrvxmtrx@gmail.com> +Date: Mon May 10 17:40:49 2010 +0300 + + lan91c96, smc911x: remove useless free(ptr) calls on NULL ptr + + Signed-off-by: Serge Ziryukin <ftrvxmtrx@gmail.com> + +commit b1e1a42bb1ea2f0ddaaea7f4c9d67c98ab38709e +Author: Ron Madrid <ron_madrid@sbcglobal.net> +Date: Fri May 14 16:27:48 2010 -0700 + + Fix SICRL setting in SIMPC8313 + + This patch sets the SICRL_LBC bits in SICRL to change the function of the + associated pins to GPIO functionality. + + Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> + +commit a4bfc4cc466473b97c7fe84bdf261b2935887e3f +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Fri May 14 13:18:54 2010 -0500 + + mpc83xx: fix NAND bootstrap too big error + + commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable + port-mapped access" inadvertently broke 83xx nand boards by + converting NS16550_init to use io accessors, which expanded + the size of the generated code. + + this patch fixes the problem by removing icache functions from + the nand builds, which somewhat follows commit + 1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache + in core initialization to improve u-boot boot time" + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit e74244c5a1c8bcea9b047217277dcd3235a285f4 +Author: Ron Madrid <ron_madrid@sbcglobal.net> +Date: Mon May 10 15:23:20 2010 -0700 + + Removal of checkboard from spl bootstrap build for SIMPC8313 + + This patch removes the checkboard function from the build of + the 4k bootstrap section for the SIMPC8313 as it is not needed + in the spl build. This will allow > 100 bytes of extra room + for other uses. + + Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 9c3f2d6670e6151f4f6329f572a62b0d2d6768ce +Author: Matthias Fuchs <matthias.fuchs@esd.eu> +Date: Tue May 11 09:54:00 2010 +0200 + + ppc4xx: Fix building PLU405 board + + Due to some overlapping sections it's time to update TEXT_BASE + for this board. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a2a0a7171303de5d8ce099344efde2e29ee36eb0 +Author: Wolfgang Denk <wd@denx.de> +Date: Sat May 15 21:23:51 2010 +0200 + + Makefile: fix out-of-tree building of "u-boot.img" target + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 2e4f35dbd8e11c3121af99ea8e04ce4fb39e9a4e +Author: Wolfgang Denk <wd@denx.de> +Date: Sat May 15 20:22:21 2010 +0200 + + MVBLM7, MVSMR: fix Makefile (cleanup bootscript.img) + + Fix MVBLM7 and MVSMR Makefiles for correct out-of-tree building + (create "bootscript.img" in build directory instead of source + directory) and cleanup (remove "bootscript.img" when cleaning up). + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> + +commit cd4b02be1bb732f3990801ff81b57bd597b1d5b6 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon May 10 23:08:02 2010 +0200 + + ARM: add __aeabi_unwind_cpp_pr0() function to avoid linker complaints + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Tested-by: Thomas Weber <weber@corscience.de> + +commit 7b43db92110ec2f15c5f7187a165f2928464966b +Author: Wolfgang Denk <wd@denx.de> +Date: Sun May 9 23:52:59 2010 +0200 + + drivers/mmc/fsl_esdhc.c: fix compiler warnings + + Commit 77c1458d caused the following compiler warnings: + + fsl_esdhc.c: In function 'esdhc_pio_read_write': + fsl_esdhc.c:142: warning: assignment discards qualifiers from pointer target type + fsl_esdhc.c: In function 'esdhc_setup_data': + fsl_esdhc.c:169: warning: unused variable 'wml_value' + fsl_esdhc.c: In function 'esdhc_pio_read_write': + fsl_esdhc.c:164: warning: control reaches end of non-void function + + Fix these. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Cc: Dipen Dudhat <dipen.dudhat@freescale.com> + Cc: Andy Fleming <afleming@freescale.com> + +commit bcb6c2bb84705bfd73eed5c9a31e9ff24833ee8c +Author: York Sun <yorksun@freescale.com> +Date: Fri May 7 09:12:01 2010 -0500 + + Enabled support for Rev 1.3 SPD for DDR2 DIMMs + + SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. + The difference has ben examined and the code is compatible. + Speed bins is not verified on hardware for CL7 at this moment. + + This patch also enables SPD Rev 1.x where x is up to "F". According to SPD + spec, the lower nibble is optionally used to determine which additinal bytes + or attribute bits have been defined. Software can safely use defaults. However, + the upper nibble should always be checked. + + Signed-off-by: York Sun <yorksun@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit f54fe87acedbbad7d29ad18cab31d2b323717514 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 20 10:21:25 2010 -0500 + + 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled + + On the MPC85xx platform if we have SATA its connected on SERDES. + Determing if SATA is enabled via sata_initialize should not be board + specific and thus we move it out of the MPC8536DS board code. + + Additionally, now that we have is_serdes_configured() we can determine + if the given SATA port is enabled and error out if its not in the + driver. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 54648985e2a64e29784e3ed37cd45b637305cd65 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 20 10:21:12 2010 -0500 + + 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled + + The new is_serdes_configured covers a broader range of devices than the + PCI specific code. Use it instead as we convert away from the + is_fsl_pci_cfg() code. + + Additionally move to setting LAWs for PCI based on if its configured. + Also updated PCI FDT fixup code to remove PCI controllers from dtb if + they are configured. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 6ab4011b796e0af130ca160ea3c674d462f3bec4 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 20 10:20:33 2010 -0500 + + 85xx: Add is_serdes_configured() support to MPC8536 SERDES + + Add the ability to determine if a given IP block connected on SERDES is + configured. This is useful for things like PCIe and SRIO since they are + only ever connected on SERDES. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 15351855776f32d40d9c336c0dc6d22a7bcf40c2 +Author: Jerry Huang <Chang-Ming.Huang@freescale.com> +Date: Thu Apr 8 15:56:07 2010 +0800 + + fsl-diu: Using I/O accessor to CCSR space + + Using PPC I/O accessor to DIU I/O space instead of directly + read/write. It will prevent the dozen of compiler order issue + and PPC hardware order issue for accessing I/O space. + + Using the toolchain(tc-fsl-x86lnx-e500-dp-4.3.74-2.i386.rpm) + can show up the order issue of DIU driver. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit fd194f82d1c30802f0597a3e359fdc03ed397367 +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Mon May 3 13:22:31 2010 +0200 + + mpc83xx/mvBLM7: add usb commands and cleanup. + + Add USB commands. + Rename autoscript to bootscript. + Add automatic bootscript image generation to makefile. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 3b439792b0781921c599d8af9bed6a771d295b53 +Author: Ron Madrid <ron_madrid@sbcglobal.net> +Date: Wed Apr 28 16:04:43 2010 -0700 + + mpc83xx: Add UPMA configuration to SIMPC8313 + + Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313 + + Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 5794619e29c5e22280b0b09b2ea6bc3d2e00da3f +Author: Mike Frysinger <vapier@gentoo.org> +Date: Wed May 5 04:32:43 2010 -0400 + + serial: punt unused serial_addr() + + Only one file apparently defines this function, and it merely stubs + it out. So if no one is defining/calling it, punt it. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit f745817e741e4251afbd9d5d7f04b2419f4aa9d9 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Apr 27 14:15:34 2010 -0400 + + update include/asm/ gitignore after move + + With the cpu include paths moved, the gitignore paths need updating. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Tested-by: Tom Rix <tom@bumblecow.com> + +commit d0179083a9c9e12c8c5400b107156c14c7da1222 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Apr 28 02:52:02 2010 -0500 + + Fixup native builds on powerpc + + When we changed ARCH from ppc to powerpc we need to treat HOSTARCH the + same way. We use HOSTARCH == ARCH to determine if a build is native. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 65d342541e78ab9a22bf480cc4fe2f659f94bad4 +Author: Serge Ziryukin <ftrvxmtrx@gmail.com> +Date: Sun Apr 25 21:32:36 2010 +0300 + + cmd_usb.c: show cmd usage if no args given + + Signed-off-by: Serge Ziryukin <ftrvxmtrx@gmail.com> + +commit e4a95d112e5ea8368bfbdac6ff963d1b8dc63cf0 +Author: Stefan Roese <sr@denx.de> +Date: Wed Apr 28 10:47:36 2010 +0200 + + powerpc: Consolidate bootcount_{store|load} for PowerPC + + This patch consolidates bootcount_{store|load} for PowerPC by + implementing a common version in arch/powerpc/lib/bootcount.c. This + code is now used by all PowerPC variants that currently have these + functions implemented. + + The functions now use the proper IO-accessor functions to read/write the + values. + + This code also supports two different bootcount versions: + + a) Use 2 separate words (2 * 32bit) to store the bootcounter + b) Use only 1 word (2 * 16bit) to store the bootcounter + + Version b) was already used by MPC5xxx. + + Signed-off-by: Stefan Roese <sr@denx.de> + Acked-by: Detlev Zundel <dzu@denx.de> + Acked-by: Kim Phillips <kim.phillips@freescale.com> + for 83xx parts + Cc: Michael Zaidman <michael.zaidman@gmail.com> + Cc: Wolfgang Denk <wd@denx.de> + Cc: Kim Phillips <kim.phillips@freescale.com> + Cc: Anatolij Gustschin <agust@denx.de> + +commit 767fdc4af684770f5e97a6c5e19a8ac2616b8329 +Author: Ender.Dai <ender.dai@gmail.com> +Date: Thu Apr 22 15:24:25 2010 +0800 + + drivers/*/Makefile: fix conditional compile rule. + + Fix conditional compile rule for twl4030.c and videomodes.c. + + Signed-off-by: Ender.Dai <ender.dai@gmail.com> + +commit 54fa2c5b51c564cce716942d26492437457980a4 +Author: Larry Johnson <lrj@acm.org> +Date: Tue Apr 20 08:09:43 2010 -0400 + + Move test for unnecessary memmove to memmove_wd() + + Signed-off-by: Larry Johnson <lrj@acm.org> + +commit b050c72d52c4e30d5b978ab6758f8dcdbe5c690c +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Apr 20 05:49:30 2010 -0400 + + compiler.h: add uint typedef + + Recent crc changes started using the "uint" type in headers that are used + on the build system. This subsequently broke mingw targets as they do not + provide such a type. So add this basic typedef to compiler.h so that we + do not have to worry about this breaking again in the future. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 39f7aacf3fd285b42b92c2c2d66d95339a3569cc +Author: Trübenbach, Ralf <Ralf.Truebenbach@men.de> +Date: Wed Apr 14 11:15:16 2010 +0200 + + command.c: Enable auto tab for the editenv command + + Enable the auto completion (with TAB) of the environment variable name + after the editenv command. + + Signed-off-by: Ralf Trübenbach <ralf.truebenbach@men.de> + +commit 0738e24e2c1d95bb94455d44485dc5d7b9c9d707 +Author: Reinhard Arlt <reinhard.arlt@esd.eu> +Date: Tue Apr 13 09:59:09 2010 +0200 + + 74xx_7xx: CPCI750: Add ECC support on esd CPCI-CPU/750 board + + Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board. + + This patch also adds the "pldver" command to display the CPLD + revision. + + Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 1f9f3cf6ccbccae1c1edff01ec20fe2a586b9701 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:06:00 2010 +1000 + + sc520: Fix minor DRAM Controller Setup bug + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit d20053efdf328d97a018536689fc55df4faf1094 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:59 2010 +1000 + + sc520: Update to new AMD Copyright + + AMD recently changed the licensing of the RAM sizing code to the + GPLv2 (or at your option any later version) + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 880c59e5add3681bd4dca14d2fd20152bee7ad14 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:58 2010 +1000 + + eNET: Implement eNET Watchdog + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit f2a55055e9b19f3eba9de97ff454cf8bfef25468 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:57 2010 +1000 + + eNET: Use SC520 MMCR to reset eNET board + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 4a4c31ae08d4dcabe348013e135de28b01c29bf0 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:56 2010 +1000 + + eNET: Add PC/AT compatibility setup function + + The eNET uses the sc520 software timers rather than the PC/AT clones + + Set all interrupts and timers up to be PC/AT compatible + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 8fd805632f95e5e834f312a51aa969bf1d99c41b +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:55 2010 +1000 + + eNET: Add support for onboard RTL8100B (RTL8139) chips + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 21e67e796bb1d59a484dce2b4203d61bf1fd5be8 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:54 2010 +1000 + + sc520: Board Specific PCI Init + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 0278216b76fc1e5dbf4cbd10d5d734323039c36f +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:53 2010 +1000 + + sc520: Move PCI defines to PCI include file + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 4f197c30e5cb3005909402b7fc630cb092eef02f +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:52 2010 +1000 + + eNET: Fix CONFIG_SYS_HZ to be 1000 + + The clock interupt has always been 1kHz as per timer_init() in + /arch/i386/cpu/sc520/sc520_timer.c + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 6fd445c32860bb06e9a68b516845a1bbf7c37889 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:51 2010 +1000 + + eNET: Fix Flash Write + + Onboard AMD Flash chip does not support buffered writes + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 5204566e53a3c519e8795480d056635bc64b11cd +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:50 2010 +1000 + + sc520: Allow boards to override udelay + + If the board has a high precision mico-second timer, it maked sense to use + it instead of the on-chip one + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 95ffaba39042064c5eb68404894fd6b0f1d6a3e3 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:49 2010 +1000 + + x86: Fix support for booting bzImage + + Add support for newer (up to 2.6.33) kernels + + Add zboot command which takes the address of a bzImage as its first + argument and (optionally) the size of the bzImage as the second argument + (the second argument is needed for older kernels which do not include + the bzImage size in the header) + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 79ea6b87011c0524ced31359e2be7aac97c29d0a +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:48 2010 +1000 + + x86: Provide weak PC/AT compatibility setup function + + It is possibly to setup x86 boards to use non-PC/AT configurations. For + example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals. + This function allows the board to set itself up for maximum PC/AT + compatibility just before booting the Linux kernel (the Linux kernel + 'just works' if everything is PC/AT compliant) + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit bf16500f79fdf2653a286b40bb601cb185ac4675 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:47 2010 +1000 + + x86: Use CONFIG_SERIAL_MULTI + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 167cdad1372917bc11c636c359aad02625291fa9 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:46 2010 +1000 + + SERIAL: Enable port-mapped access + + The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access + the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped + and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and + drop the custom serial port driver + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 153c2d9f2397e8b6ca03cfebb4e9666ea0b0637c +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:45 2010 +1000 + + x86: Fix copying of Real-Mode code into RAM + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 2fb1bc4f53618743b92a48763d7aaa0ece9ad98f +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:44 2010 +1000 + + x86: Pass relocation offset into Global Data + + In order to locate the 16-bit BIOS code, we need to know the reloaction + offset. + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit c14a3669b22d3e430b416cdee92b751f13697a1f +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:43 2010 +1000 + + x86: Move GDT to a safe location in RAM + + Currently, the GDT is either located in FLASH or in the non-relocated + U-Boot image in RAM. Both of these locations are unsafe as those + locations can be erased during a U-Boot update. Move the GDT into the + highest available memory location and relocate U-Boot to just below it + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 077e1958ca4afe12d88043b123ded058c51b89f7 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:42 2010 +1000 + + x86: Add RAM bootstrap functionality + + Add a parameter to the 32-bit entry to indicate if entry is from Real + Mode or not. If entry is from Real Mode, execute the destructive 'sizer' + routine to determine memory size as we are booting cold and running in + Flash. If not entering from Real Mode, we are executing a U-Boot image + from RAM and therefore the memory size is already known (and running + 'sizer' will destroy the running image) + + There are now two 32-bit entry points. The first is the 'in RAM' entry + point which exists at the start of the U-Boot binary image. As such, + you can load u-boot.bin in RAM and jump directly to the load address + without needing to calculate any offsets. The second entry point is + used by the real-to-protected mode switch + + This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load + the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot + prompt + + Hopefully a later patch will completely elliminate any dependency on + TEXT_BASE like a relocatable linux kernel (perfect world) + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 759598f82f02cc84614450807cb5de43ca18a339 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:41 2010 +1000 + + x86: Split sc520 memory sizing versus reporting + + This patch allows the low-level assembler boot-strap to obtain the RAM + size without calling the destructive 'sizer' routine. This allows + boot-strapping from a U-Boot image loaded in RAM + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 4dba333b3c7b34073b0439cc942877f98403632c +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:40 2010 +1000 + + x86: Fix sc520 memory size reporting + + There is an error in how the assembler version of the sc520 memory size + reporting code works. As a result, it will only ever report at most the + size of one bank of RAM + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 9e08efcfee22570bb3a9ea384bf4d60b378f6092 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:39 2010 +1000 + + x86: Fix do_go_exec() + + This was broken a long time ago by a49864593e083a5d0779fb9ca98e5a0f2053183d + which munged the NIOS and x86 do_go_exec() + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 433ff2bdbccc5190189528305e4ed6f7205dbafd +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:38 2010 +1000 + + x86: Add register dump to crash handlers + + Shamelessly steal the Linux x86 crash handling code and shove it into + U-Boot (cool - it fits). Be sure to include suitable attribution to + Linus + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 64a0a4995e79ef9813bb51d5f1ff35ae5dabfc7e +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:37 2010 +1000 + + x86: Fix MMCR Access + + Change sc520 MMCR Access to use memory accessor functions + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 535ad2db069aae6d1d36fc05c31cbd8a2b3d8831 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:36 2010 +1000 + + x86: #ifdef out getenv_IPaddr() + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 721c36705a9efc7b67f78d0c3e8485e4f1b8bcc9 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sat Apr 24 00:05:35 2010 +1000 + + x86: Add unaligned.h + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 93c7e70f648fb817e519f6e163b7ef9befc27349 +Author: Michael Zaidman <michael.zaidman@gmail.com> +Date: Wed Apr 7 18:30:08 2010 +0300 + + POST: Added ECC memory test for mpc83xx. + + Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com> + + Fixed minor coding style issue. + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 8cd852824d91e232f1f820a0772c3c1d8af84b05 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Sat Mar 27 17:14:36 2010 +0100 + + cmd_onenand.c: moved to standard subcommand handling + + On the fly also fixed the following things: + - write help talked about a parameter oob, but that one was not used, so + removed it from the help message. + - the test command also allowed a force subcommand but didn't use it. + eliminated the code. + - do_onenand made static + - do_onenand contained + int blocksize; + ... + mtd = &onenand_mtd; + this = mtd->priv; + blocksize = (1 << this->erase_shift); + As blocksize was not used the last two statements were unneeded so + removed them. + The first statement (mtd = ....) assigns to a global. Not sure if it + is needed, and since I could not test this, left the line for now + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit 3882d7a5a57eb8d1f41570522445bab61c628e6f +Author: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> +Date: Fri Mar 19 15:34:25 2010 +0100 + + ppc: unused memory region too close to current stack pointer + + This avoids a possible overwrite of the (end of) ramdisk by u-boot. + The unused memory region for ppc boot currently starts 1k below the + do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since + do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may + very well use more than 1k stack space. + + Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> + +commit 4b42c9059e165500353174601a8e97b2cf81d3f4 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Apr 13 13:16:03 2010 -0500 + + allow print_size to print large numbers on 32-bit systems + + Modify print_size() so that it can accept numbers larger than 4GB on 32-bit + systems. + + Add support for display terabyte, petabyte, and exabyte sizes. Change the + output to use International Electrotechnical Commission binary prefix standard. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 52dbac69c27dee67a4c051b1055d93b0ac4e2062 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Apr 13 13:16:02 2010 -0500 + + fix print_size printing fractional gigabyte numbers on 32-bit platforms + + In print_size(), the math that calculates the fractional remainder of a number + used the same integer size as a physical address. However, the "10 *" factor + of the algorithm means that a large number (e.g. 1.5GB) can overflow the + integer if we're running on a 32-bit system. Therefore, we need to + disassociate this function from the size of a physical address. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit b5cebb4fd60fefc7700a486bb74fecc66c07acff +Author: Mike Frysinger <vapier@gentoo.org> +Date: Wed May 5 03:20:30 2010 -0400 + + Blackfin: TWI/I2C: implement multibus support + + In order to do this cleanly, the register accesses have to be converted to + a C struct (base pointer), so do that in the process. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit b4377e12e9aa0b3bf2dcae0a0f02ec9086338506 +Author: Stefano Babic <sbabic@denx.de> +Date: Tue Mar 16 17:22:21 2010 +0100 + + Add SPI support to mx51evk board + + The patch adds SPI devices to the mx51evk board. + The MC13892 chip (PMIC) is supported. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit d3588a55d4a041f2208290b8b6f9cecbdad179ac +Author: Stefano Babic <sbabic@denx.de> +Date: Sun Apr 18 19:27:44 2010 +0200 + + MX: Added definition file for MC13892 + + The MC13892 is a Power Controller used with processors + of the family MX.51. The file adds definitions to be used to setup + the internal registers via SPI. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit d205ddcfc5b905eff023d5acac395721d80a92c7 +Author: Stefano Babic <sbabic@denx.de> +Date: Sun Apr 4 22:43:38 2010 +0200 + + SPI: added support for MX51 to mxc_spi + + This patch add SPI support for the MX51 processor. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit e98ecd71102de9d97bd82be247ed909260fb671b +Author: Stefano Babic <sbabic@denx.de> +Date: Fri Apr 16 17:13:54 2010 +0200 + + MX31: Add support for PMIC to the QONG module + + Add support for the PMIC (MC13783) controller + and enables charging of the RTC battery. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit dfe5e14fa263eb8f1a9f087f0284788e7559821d +Author: Stefano Babic <sbabic@denx.de> +Date: Fri Apr 16 17:11:19 2010 +0200 + + MX: RTC13783 uses general function to access PMIC + + The RTC is part of the Freescale's PMIC controller. + Use general function to access to PMIC internal registers. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + Tested-by: Magnus Lilja <lilja.magnus@gmail.com> + +commit 28bb6d34d3f431b7b00444e2f829b2c04f5daf4d +Author: Stefano Babic <sbabic@denx.de> +Date: Sun Apr 4 23:08:03 2010 +0200 + + MX: Added Freescale Power Management Driver + + The patch add supports for the Freescale's Power + Management Controller (known as Atlas) used together with i.MX31/51 + processors. It was tested with a MC13783 (MX31) and + MC13892 (MX51). + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit ba6adeb48e71f7f1b791b6e98999a5680d919b26 +Author: Magnus Lilja <lilja.magnus@gmail.com> +Date: Fri Apr 23 20:30:49 2010 +0200 + + i.MX31: Activate NAND support for i.MX31 Litekit board. + + Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> + +commit 60381d687885c0e2100657ca73e97e38c4604f5e +Author: Fabio Estevam <fabioestevam@yahoo.com> +Date: Fri Apr 23 06:32:01 2010 -0700 + + MX51: Fix MX51 CPU detect message + + Fix MX51 CPU detect message. + + Original string was: + CPU: Freescale i.MX51 family 3.0V at 800 MHz + + which can be misinterpreted as 3.0 Volts instead of the silicon revision. + + ,change it to: + CPU: Freescale i.MX51 family rev3.0 at 800 MHz + + Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> + +commit 68c07a0c215a64826ed13c2f9b00a6d3b298822e +Author: Stefano Babic <sbabic@denx.de> +Date: Sun Apr 18 20:01:01 2010 +0200 + + MX51evk: Removed warnings + + Changes reflect modifications in the fsl_esdhc driver + (the clk_enable field war removed in the configuration structure). + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 87db58dca47f93f9fb3b4ed0196dd7a3f5df1cb9 +Author: Anatolij Gustschin <agust@denx.de> +Date: Wed Apr 21 13:52:38 2010 +0200 + + tx25: fix crash while booting Linux + + Currently booting Linux on TX25 board doesn't work + since there is no correct mach-id and boot parameters + setup for tx25 board. Fix it now. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + Cc: John Rigby <jcrigby@gmail.com> + Cc: Stefano Babic <sbabic@denx.de> + +commit b88c5988db176a0f9de5598d5167ee2498637d40 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Apr 13 21:11:53 2010 -0500 + + configs: remove unused CONFIG_COMMAND_HISTORY + + $ git grep CONFIG_COMMAND_HISTORY + CHANGELOG: CONFIG_COMMAND_HISTORY + include/configs/AP1000.h:#define CONFIG_COMMAND_HISTORY 1 + include/configs/keymile-common.h:#define CONFIG_COMMAND_HISTORY 1 + include/configs/manroland/common.h:#define CONFIG_COMMAND_HISTORY 1 + $ + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + Acked-by: Heiko Schocher <hs@denx.de> + +commit 7769c5bc06615293870d00fc81366cd43ba0623a +Author: Anatolij Gustschin <agust@denx.de> +Date: Tue Apr 13 14:47:32 2010 +0200 + + mvsmr: fix link error + + MVSMR board support doesn't link since recent rework + of U-Boot directory structure. Fix it now. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> + Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + Fixed merge conflict + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 4324dc72df5879e5b614c4a3f326884723ede9b7 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Apr 27 14:15:28 2010 -0400 + + Blackfin: bfin_mac: hook up new write_hwaddr function + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 3ac9d6c650d94c51645efa446c1d914c5440990d +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Tue Apr 27 20:20:27 2010 +0800 + + net: ethoc: add write_hwaddr support + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 6c7c444786fc4022999362fce119c8b731eedcb4 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Tue Apr 27 20:15:10 2010 +0800 + + net: altera_tse: add write_hwaddr support + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit fb57ec97b90291c589087167f100483a089837bf +Author: Heiko Schocher <hs@denx.de> +Date: Tue Apr 27 07:43:52 2010 +0200 + + net: fec_mxc: add write_hwaddr support + + tested on the magnesium board. + + Signed-off-by: Heiko Schocher <hs@denx.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit b5ce63ed12b4cd81d211621aca0c222b20d2a691 +Author: Prafulla Wadaskar <prafulla@marvell.com> +Date: Tue Apr 6 22:21:33 2010 +0530 + + net:kirkwood_egiga.c: MAC addresses programming using write_hwaddr + + Added a new function kwgbe_write_hwaddr for programming egiga + controller's hardware address. + This function will be called for each egiga port being used + + Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit ecee9324d73555e744593f3e0d387bec4c566f55 +Author: Ben Warren <biggerbadderben@gmail.com> +Date: Mon Apr 26 11:11:46 2010 -0700 + + Program net device MAC addresses after initializing + + Add a new function to the eth_device struct for programming a network + controller's hardware address. + + After all network devices have been initialized and the proper MAC address + for each has been determined, make a device driver call to program the + address into the device. Only device instances with valid unicast addresses + will be programmed. + + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + Acked-by: Detlev Zundel <dzu@denx.de> + Tested-by: Prafulla Wadaskar <prafulla@marvell.com> + Tested-by: Heiko Schocher <hs@denx.de> + Tested-by: Thomas Chou <thomas@wytron.com.tw> + +commit c960b13ed22d9ea570957379f9f7f2f37d87ef08 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Tue Apr 20 12:49:52 2010 +0800 + + net: add altera triple speeds ethernet mac driver + + This driver supports the Altera triple speeds 10/100/1000 ethernet + mac. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit f6569884b45e480e2c575d85ce86a2636a41c66b +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Thu Apr 15 22:32:38 2010 +0800 + + net: add opencore 10/100 ethernet mac driver + + This patch ports the opencore 10/100 ethernet mac driver ethoc.c + from linux kernel to u-boot. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit bd75db3feb9a8e4123b76006dbe582b71adbf22f +Author: Valentin Yakovenkov <yakovenkov@niistt.ru> +Date: Fri Apr 23 09:40:23 2010 +0400 + + smc911x driver frame alignment patch + + SMSC911x chips have alignment function to allow frame payload data + (which comes after 14-bytes ethernet header) to be aligned at some + boundary when reading it from fifo (usually - 4 bytes boundary). + This is done by inserting fake zeros bytes BEFORE actual frame data when + reading from SMSC's fifo. + This function controlled by RX_CFG register. There are bits that + represents amount of fake bytes to be inserted. + + Linux uses alignment of 4 bytes. Ethernet frame header is 14 bytes long, + so we need to add 2 fake bytes to get payload data aligned at 4-bytes + boundary. + Linux driver does this by adding IP_ALIGNMENT constant (defined at + skb.h) when calculating fifo data length. All network subsystem of Linux + uses this constant too when calculating different offsets. + + But u-boot does not use any packet data alignment, so we don't need to + add anything when calculating fifo data length. + Moreover, driver zeros the RX_CFG register just one line up, so chip + does not insert any fake data at the beginig. So calculated data length + is always bigger by 1 word. + + It seems that at almost every packet read we get an underflow condition + at fifo and possible corruption of data. Especially at continuous + transfers, such as tftp. + + Just after removing this magic addition, I've got tftp transfer speed as + it aught to be at 100Mbps. It was really slow before. + + It seems that fifo underflow occurs only when using byte packing on + 32-bit blackfin bus (may be because of very small delay between reads). + + Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit f0588fdf921c63f84051923bb29eb4255d62a6e7 +Author: Prafulla Wadaskar <prafulla@marvell.com> +Date: Tue Apr 6 21:33:08 2010 +0530 + + net: Kirkwood_egiga.c bugfixes for rx path + + Cosmetic changes: Few comments updated + Functionality: Rx packet frame size is programming should + be done when port is in disabled state. this is corrected + + Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 2e236bf28e729aca28e60c153dd8f913d1b3d058 +Author: Eric Jarrige <eric.jarrige@armadeus.org> +Date: Fri Apr 16 00:03:19 2010 +0200 + + fec_mxc.c: Fix MX27 FEC MAC validity check + + Fix MX27 FEC logic to check validity of the MAC address in fuse. + Only null (empty fuse) or invalid MAC address was retrieved from mx27 fuses before this change. + + Signed-off-by: Eric Jarrige <jorasse@armadeus.org> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 538be58568542aac2ed4bdf4c05398cfa67e98f0 +Author: Andy Fleming <afleming@freescale.com> +Date: Mon Apr 19 14:54:49 2010 -0500 + + tsec: Wait for both RX and TX to stop + + When gracefully stopping the controller, the driver was continuing if + *either* RX or TX had stopped. We need to wait for both, or the + controller could get into an invalid state. + + Signed-off-by: Andy Fleming <afleming@freescale.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit a45dde2293c816138e53c26eca6fd0322583f9a6 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Wed Apr 14 16:29:06 2010 -0400 + + net: dm9000x: use standard I/O accessors + + The current dm9000x driver accesses its memory mapped registers directly + instead of using the standard I/O accessors. This can cause problems on + Blackfin systems as the accesses can get out of order. So convert the + direct volatile dereferences to use the normal in/out macros. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 5525856d59910c72687ab6201f39cdf1c04cfc15 +Author: Detlev Zundel <dzu@denx.de> +Date: Thu Apr 8 11:49:59 2010 +0200 + + mpc512x_fec: Move PHY initialization from probe into init routine. + + This saves the autonegotation delay when not using ethernet in U-Boot + + Signed-off-by: Detlev Zundel <dzu@denx.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 910119b3c462fd6367536899ee43de1eb7d22d8e +Author: John Rigby <jcrigby@gmail.com> +Date: Wed Apr 7 23:29:40 2010 -0600 + + fec_mxc don't use internal eeprom on MX25 + + Avoid using the internal eeprom on MX25 like MX51 already does. + + Signed-off-by: John Rigby <jcrigby@gmail.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 33f684d6d512992ed1ae37ec46e76bdeb0773bac +Author: Wolfgang Wegner <w.wegner@astro-kom.de> +Date: Tue Apr 6 11:13:02 2010 +0200 + + fix lockup in mcfmii/mii_discover_phy() in case communication fails + + Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 23c34af48ff0dbff3bbaa8e94df3bf40350a709f +Author: Richard Retanubun <RichardRetanubun@RuggedCom.com> +Date: Wed Jun 17 16:00:41 2009 -0400 + + 83xx: UEC: Added support for bitBang MII driver access to PHYs + + This patch enabled support for having PHYs on bitBang MII and uec MII + operating at the same time. Modeled after the MPC8360ADS implementation. + + Added the ability to specify which ethernet interfaces have bitbang SMI + on the board header file. + + Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 9739946cc5b616c026d433bd07d193cf452ddea0 +Author: Robin Getz <rgetz@blackfin.uclinux.org> +Date: Mon Mar 8 14:07:00 2010 -0500 + + ./net/net.c - make Microsoft dns servers happy with random_port() numbers + + For some reason, (which I can't find any documentation on), if U-Boot + gives a port number higher than 17500 to a Microsoft DNS server, the + server will reply to port 17500, and U-Boot will ignore things (since + that isn't the port it asked the DNS server to reply to). + + This fixes that by ensuring the random port number is less than 17500. + + Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 6f5f89f01195e2d009b317df27197a38fcab3553 +Author: Detlev Zundel <dzu@denx.de> +Date: Thu Apr 1 14:16:41 2010 +0200 + + Remove unused "local_crc32" function. + + For code archeologists, this is a nice example of copy and paste history. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit aba4b69d01457ab2988e91c8592e5d2ffb10f569 +Author: Detlev Zundel <dzu@denx.de> +Date: Wed Mar 31 17:56:08 2010 +0200 + + net: Trivial coding style issue with empty for statement + + Signed-off-by: Detlev Zundel <dzu@denx.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit e3f2a93362c823fc1feb5e8a40ff3c120716a05b +Author: Prafulla Wadaskar <prafulla@marvell.com> +Date: Wed Mar 3 15:27:21 2010 +0530 + + net: Kirkwood_egiga.c: fixed build warnings + + This patch fixes following build warnings for kirkwood_egiga.c + + kirkwood_egiga.c: In function "kwgbe_init": + kirkwood_egiga.c:448: warning: dereferencing type-punned pointer will break strict-aliasing rules + kirkwood_egiga.c: In function "kwgbe_recv": + kirkwood_egiga.c:609: warning: dereferencing type-punned pointer will break strict-aliasing rules + + Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 20d98c2cea3398ad93beccd4727a371f41514086 +Author: Asen Dimov <dimov@ronetix.at> +Date: Mon Apr 19 14:18:43 2010 +0300 + + pm9263 converted to at91 soc access + + Signed-off-by: Asen Dimov <dimov@ronetix.at> + +commit d6b91e30d32871eb20b6227519fd2f3a6ea073fd +Author: Asen Dimov <dimov@ronetix.at> +Date: Mon Apr 19 14:17:22 2010 +0300 + + at91: define matrix registers bit fields + + Signed-off-by: Asen Dimov <dimov@ronetix.at> + +commit eeb50ce193453951529015f50e5c1ccd7b55aad2 +Author: Stefano Babic <sbabic@denx.de> +Date: Tue Apr 13 12:19:06 2010 +0200 + + MX31: Removed erroneous board name from QONG + + QONG is a module that can be installed on several boards, + not only on the QONG-EVB manufactured by Dave srl. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit c9d944d35e7904229c5333e761bce9d4324971f8 +Author: Stefano Babic <sbabic@denx.de> +Date: Thu Apr 8 17:23:52 2010 +0200 + + MX31: Add UBI support to QONG module + + The UBI/UBIFS support is added to the QONG module. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit eab40f819ddd50eef465619db1386c053b59a95b +Author: Stefano Babic <sbabic@denx.de> +Date: Wed Mar 31 10:27:47 2010 +0200 + + MX31: Support 128MB RAM on QONG module + + The QONG module can be downsized and delivered + with 128MB instead of 256MB. The patch adds + run time support for the two different memory + configurations. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 45997e0a86ee8d8abec6d791a241cb20011fe0e3 +Author: Stefano Babic <sbabic@denx.de> +Date: Mon Mar 29 16:43:39 2010 +0200 + + MX31: Add support for NAND to QONG board + + The NAND device is connected to the FPGA of the QONG board + and not to the NFC controller. For this reason, the FPGA must + be set and initialized before accessing to the NAND itself. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit efb9591069ee276f7fa27a821240c7511f72fe65 +Author: Stefano Babic <sbabic@denx.de> +Date: Mon Mar 29 15:56:10 2010 +0200 + + MX31: add pin definitions for NAND controller + + Add pin definitions ralted to the NAND controller to be used + to set up the pin multiplexer. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 7d27cd08b4c1adfd58c54aaa8b8c8f4eeb3c7021 +Author: Stefano Babic <sbabic@denx.de> +Date: Tue Apr 13 12:07:00 2010 +0200 + + MX31: add accessor function to get a gpio + + The patch adds an accessor function to get the value of a gpio. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit dfe83352cb58c55dfdbd5b535cb335526cb1c581 +Author: Stefano Babic <sbabic@denx.de> +Date: Tue Apr 13 12:38:43 2010 +0200 + + mx51evk: correct list of possible BOOT_FROM values + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit f581e3a2157fbd736e7dd2378465ae242fba545c +Author: Stefano Babic <sbabic@denx.de> +Date: Tue Apr 13 12:38:22 2010 +0200 + + mkimage: correct spelling error in imximage + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 34196b0a8bd7ab6d472e2e6f6c90b73e915a1fae +Author: John Rigby <jcrigby@gmail.com> +Date: Wed Apr 7 23:30:09 2010 -0600 + + MX25 print arm clock instead of mpllclk on boot + + Replace call to imx_get_mpllclk with imx_get_armclk + to show frequency of ARM core instead of mpll internal + bus in print_cpuinfo. + + Signed-off-by: John Rigby <jcrigby@gmail.com> + CC: Stefano Babic <sbabic@denx.de> + +commit 1c9d91aca649f17762bae2c0e38f5101d62ed0b5 +Author: Frans Meulenbroeks <[fransmeulenbroeks@gmail.com]> +Date: Tue Apr 6 19:06:11 2010 +0530 + + configs/openrd_base.h: reordered macros + + moved CONFIG_CMD_FAT to filesystem section + swapped CONFIG_CMD_NAND and CONFIG_CMD_MII so they are alpha correct + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit 5414fec85ff558af8823d4391f03977288871fe4 +Author: Frans Meulenbroeks <[fransmeulenbroeks@gmail.com]> +Date: Tue Apr 6 18:26:19 2010 +0530 + + configs/sheevaplug: added a few additional commands + + This patch includes a few additional commands in the sheevaplug + version of u-boot: + - support for LONGHELP so you can get help messages + - auto completion and command editing + - ubi and mii support + - ext2 filesystem (convenient if you have an ext2 from which you want to boot) + - jffs2 and ubifs filesystems (if you want to use these in NAND) + + This also makes it more similar to openrd client. + + Side effect of this patch is that the code now needs 3 sectors i.s.o. 2 + so an existing env is overwritten + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit 16b76705d36ac137fa9231cedfe1355561639e47 +Author: Siddarth Gore <[gores@marvell.com]> +Date: Thu Mar 18 20:25:40 2010 +0530 + + Marvell GuruPlug Board Support + + GuruPlug Standard: 1 Gb Ethernet, 2 USB 2.0 + GuruPlug Plus: 2 Gb Ethernet, 2 USB 2.0, 1 eSATA, 1 uSD slot + + References: + http://www.globalscaletechnologies.com/t-guruplugdetails.aspx + http://plugcomputer.org + + This patch is for GuruPlug Plus, but it supports Standard version + as well. + + Signed-off-by: Siddarth Gore <gores@marvell.com> + +commit 5e1fe88fe3df2555a8a0cba7d2ffaf2b03041dfb +Author: Stefano Babic <sbabic@denx.de> +Date: Sun Mar 28 13:43:26 2010 +0200 + + Moved board specific values in config file + + The lowlevel_init file contained some hard-coded values + to setup the RAM. These board related values are moved into + the board configuration file. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 272017853339f5b9685f9488bdaf5405812d12a4 +Author: Fabio Estevam <fabioestevam@yahoo.com> +Date: Wed Mar 31 06:32:56 2010 -0700 + + MX51EVK: Remove CPLD related code + + There is no CPLD on MX51EVK board, so remove CPLD related function. + + Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> + +commit bbe310922f4d0b12c8aba97b45ed979db9c0ec9a +Author: Heiko Schocher <hs@denx.de> +Date: Fri Mar 5 07:36:33 2010 +0100 + + arm, i.mx27: add support for magnesium board from projectiondesign + + This patch adds support for the magnesium board from + projectiondesign. This board uses i.MX27 SoC and has + 8MB NOR flash, 128MB NAND flash, FEC ethernet controller + integrated into i.MX27. As this port is based on + the imx27lite port, common config options are collected + in include/configs/imx27lite-common.h + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 1e65c2beb5805f975cd5d0ab7d853040a716d51b +Author: Heiko Schocher <hs@denx.de> +Date: Thu Mar 4 08:12:05 2010 +0100 + + arm, mx27: add support for SDHC1 pin init + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 3bb6b037e8557fd3c0f3b3d9840c8b5996651dcb +Author: Minkyu Kang <mk7.kang@samsung.com> +Date: Wed Mar 24 15:31:06 2010 +0900 + + SAMSUNG: make s5p common gpio functions + + Because of s5pc1xx gpio is same as s5p seires SoC, + move gpio functions to drvier/gpio/ + and modify structure's name from s5pc1xx_ to s5p_. + + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit 46a3b5c8df939f5547bcd3684030072c94d06bd8 +Author: Minkyu Kang <mk7.kang@samsung.com> +Date: Wed Mar 24 16:59:30 2010 +0900 + + SAMSUNG: serial: modify name from s5pc1xx to s5p + + Because of other s5p series SoC will use these serial functions, + modify function's name and structure's name. + + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit da0f2af279563ddc75eff304ad5389f7f0e79381 +Author: Asen Dimov <dimov@ronetix.at> +Date: Wed Apr 7 12:33:11 2010 +0300 + + pm9263: remove CONFIG_CMD_AUTOSCRIPT + + Signed-off-by: Asen Dimov <dimov@ronetix.at> + +commit 47eb08a97eb166e93d0495848b0c7582a0639fbc +Author: Alexander Holler <holler@ahsoftware.de> +Date: Mon Mar 29 21:39:43 2010 +0200 + + at91: add defines for RTT and GPBR + + Signed-off-by: Alexander Holler <holler@ahsoftware.de> + +commit dc8cab87459d682fc272444044592d20243da2f0 +Author: Asen Dimov <dimov@ronetix.at> +Date: Tue Apr 6 16:17:34 2010 +0300 + + pm9261: remove CONFIG_CMD_AUTOSCRIPT + + Signed-off-by: Asen Dimov <dimov@ronetix.at> + +commit e3150c77617c7d452420e6c87769b79b6671b12d +Author: Asen Dimov <dimov@ronetix.at> +Date: Tue Apr 6 16:18:04 2010 +0300 + + pm9261 converted to at91 soc access + + Signed-off-by: Asen Dimov <dimov@ronetix.at> + +commit 7bc8768039948e50cc149bea2ec214bde3245c4a +Author: trix <trix@windriver.com> +Date: Sat Apr 10 12:46:49 2010 -0500 + + ARM Update mach-types + + Fetched from http://www.arm.linux.org.uk/developer/machines/download.php + And built with + + repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm + commit 85b3cce880a19e78286570d5fd004cc3cac06f57 + + Signed-off-by: Tom Rix <Tom.Rix@windriver.com> + +commit d3061c692155412aa87e7f4f66b4a2c7b77ee417 +Author: Stefan Roese <sr@denx.de> +Date: Wed Apr 28 11:09:59 2010 +0200 + + ppc4xx: Fix APC405 build breakage + + This patch fixes APC405 build, by defining CONFIG_PPC4XX_I2C. This is + needed since the move of the PPC4xx I2C driver into the drivers/i2c + directory. + + Signed-off-by: Stefan Roese <sr@denx.de> + Cc: Matthias Fuchs <matthias.fuchs@esd.eu> + +commit 029faf3e85e9406f32f133e6f2a114ed26b02fb4 +Author: Stefan Roese <sr@denx.de> +Date: Tue Apr 27 11:37:28 2010 +0200 + + ppc4xx: Add support for ICON board (PPC440SPe) + + This patch adds support for the Mosaix Technologies, Inc. ICON board, + based on the AppliedMicro (AMCC) PPC440SPe. It's equipped with an SODIMM + (512MB standard) and 64MByte of NOR FLASH. + + Support for the onboard SM502 will be added later. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 96a0d6235db4c93c03d41c492f5960b18547b7a7 +Author: Stefan Roese <sr@denx.de> +Date: Mon Apr 26 13:31:08 2010 +0200 + + ppc4xx: Add missing APC405 to MAKEALL + + Signed-off-by: Stefan Roese <sr@denx.de> + Cc: Matthias Fuchs <matthias.fuchs@esd.eu> + +commit 64123e3f06f74dd09b86e2a41d77d31044f495fb +Author: Larry Johnson <lrj@acm.org> +Date: Tue Apr 20 08:11:40 2010 -0400 + + Fix typos in Korat board console output + + Signed-off-by: Larry Johnson <lrj@acm.org> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 8a1cdaa9d54c93db300e8565191d60712aa481dc +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 28 12:54:43 2010 +0200 + + QONG: Adapt flash addresses and mtdparts to grown image size + + Also enable HUSH shell. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit e1d2950d0f5aaa7ab6609ffa96dde2e163fc2902 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 28 10:58:10 2010 +0200 + + mtdparts: get rid of custom DEBUG macro, use debug() + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 2697eff1af136c6424c065cba994aa9aceadbcd1 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 28 10:53:47 2010 +0200 + + mtdparts: fix write through NULL pointer + + The "mtdparts add" command wrote through a NULL pointer - on many + systems this went unnoticed (PowerPC has writable RAM there, some ARM + systems have ROM where a write has no effect), but on arm1136 + (i.MX31) it crashed the system. + + Add appropriate checks. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 68651683593958cedcdfb9d06a5fe0a524f8dd6e +Author: Stefano Babic <sbabic@denx.de> +Date: Wed Apr 21 09:47:19 2010 +0200 + + ubifsmount fails due to not initialized list + + ubifsmount is not working and causes an access with + a pointer set to zero because the ubifs_fs_type + is not initialized correctly. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 7c8cf0d0c7b12c7c63765e936cf760dc2c7d7306 +Author: Stefano Babic <sbabic@denx.de> +Date: Wed Apr 21 09:56:31 2010 +0200 + + MX31: Added LCD support for QONG module + + Added support for LCD and splash image to the QONG module. + The supported display is VBEST-VGG322403. + + Signed-off-by: Stefano Babic <sbabic@denx.de> + +commit 7e1afb62a7e68843248b9a76a265c9193e716768 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 20 10:02:24 2010 -0500 + + ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ + + The MPC83xx SERDES control is different from the other FSL PPC chips. + For now lets split it out so we can standardize on interfaces for + determining of a device on SERDES is configured. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Kim Phillips <kim.phillips@freescale.com> + +commit 3f0202ed13add5fd6e2ed66fcb3f5e1228cdf766 +Author: Lan Chunhe <b25806@freescale.com> +Date: Wed Apr 21 07:40:50 2010 -0500 + + mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash + + Signed-off-by: Lan Chunhe <b25806@freescale.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 0c955dafab495fef5a76f5383387281d0408056c +Author: Dave Liu <daveliu@freescale.com> +Date: Wed Apr 14 19:05:06 2010 +0800 + + 85xx: clean up the io_sel for PCI express of P1022 + + clean up the wrong io_sel for PCI express according to latest manual. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 47106ce168890d637fd849682ba88ecfdb9c35de +Author: Detlev Zundel <dzu@denx.de> +Date: Wed Apr 14 11:32:20 2010 +0200 + + 85xx/socrates: Remove NFS support to fit image size. + + This fixes an overflow during the link phase. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 9ce3c228276b0f85105da8c39b164f2b6c84ea34 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 13 11:07:57 2010 -0500 + + 85xx: Fix compile warning + + cpu.c: In function 'checkcpu': + cpu.c:47: warning: unused variable 'gur' + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 4db9708b94b6745f5c1eaa699d4d76477de8588a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Apr 13 23:56:23 2010 -0500 + + 85xx: Convert cpu_init_f code to use out_be32 for LBC registers + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit cd3abcfa2d4dc8df09f6d01e735e4dc2f6c87ebc +Author: Dave Liu <daveliu@freescale.com> +Date: Mon Apr 12 14:23:35 2010 +0800 + + fsl_sata: Move the snoop bit to another place + + For P1022 SATA host controller, the data snoop bit of DW3 in PRDT + is moved to bit28. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit e4773debb735323a9eedf353239e8e88e03d7c58 +Author: Dave Liu <daveliu@freescale.com> +Date: Mon Apr 12 14:23:25 2010 +0800 + + fsl_sata: Add the workaround for errata SATA-A001 + + After power on, the SATA host controller of P1022 Rev1 is configured + in legacy mode instead of the expected enterprise mode. + + Software needs to clear bit[28] of HControl register to change to + enterprise mode after bringing the host offline. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 99bac479dd183529f4e259a0de8d31644219d487 +Author: Dave Liu <daveliu@freescale.com> +Date: Tue Dec 8 11:56:48 2009 +0800 + + fsl-ddr: Add extra cycle to turnaround times + + Add an extra cycle turnaround time to read->write to ensure stability + at high DDR frequencies. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit f8d05e5e5888d88ab42524d699924936e8e77970 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Mar 5 12:23:00 2010 +0800 + + fsl-ddr: add the macro for Rtt_Nom definition + + add the macro definition for Rtt_Nom termination value for DDR3 + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 1231c498e016b5bfe85f1eb87c2e044d3389d7da +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Apr 7 10:39:46 2010 -0500 + + ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines + + Added some needed fines and some misc additional defines + used by p4080 initialization. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 17d90f31a810a19ade1a1c534fde9f65d4d66390 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Mar 5 12:23:00 2010 +0800 + + ppc/p4080: Extend the GUTS memory map + + Extend pin control and clock control to GUTS memory map + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit ab48ca1a661b9ab8e3fee9fe2df65432b09ed073 +Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> +Date: Wed Feb 10 17:32:43 2010 +0800 + + ppc/p4080: Fix synchronous frequency calculations + + When DDR is in synchronous mode, the existing code assigns sysclk + frequency to DDR frequency. It should be synchronous with the platform + frequency. CPU frequency is based on platform frequency in synchronous + mode. + + Also fix: + + * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) + * Corrects the detection of synchronous mode. + + Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 1749c3da8d8445cdf78d70120a803e3e9553113c +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Apr 7 02:49:12 2010 -0500 + + ppc/85xx: Fixup PCI nodes for P1_P2_RDB + + While we had ft_pci_board_setup it wasn't being called by + ft_board_setup. Fix that so we actually update the device tree PCI + nodes on P1_P2_RDB boards. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 8cbb0ddd7e696c6a4be1ae3ab3c95d3c8f6a7031 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Wed Apr 21 08:40:59 2010 +0800 + + nios2: add nios2-generic board + + This is a generic approach to port u-boot for nios2 boards. + You may find the usage of this approach on the nioswiki, + http://nioswiki.com/DasUBoot + + A fpga parameter file, which contains base address information + and drivers declaration, is generated from Altera's hardware system + description sopc file using tools. + + The example fpga parameter file is compatible with EP1C20, EP1S10 + and EP1S40 boards. So these boards can be removed after this commit. + Though epcs controller is removed to cut the dependency of altera_spi + driver. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 441cac10d8a9438b144ab0ad46280780b58f638b +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Thu Apr 22 17:27:16 2010 +0800 + + nios2: fix no flash, add nand and mmc init in board.c + + This patch fixes error when CONFIG_SYS_NO_FLASH. And adds + nand flash and mmc initialization, which should go before + env initialization. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit fd2712d0b1d4c1624bef35b784ee64451ee5a017 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Tue Apr 20 11:01:11 2010 +0800 + + nios2: consolidate reset initialization + + Global interrupt should be disabled from the beginning. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 994852966d2e6cf98c1dbeea8ee62c233b305ffb +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Wed Mar 31 08:30:08 2010 +0800 + + altera_jtag_uart: bypass when no jtag connection + + This patch adds an option to bypass output waiting when there + is no jtag connection. This allows the jtag uart work similar + to a serial uart, ie, boot even without connection. + + This option is enabled with CONFIG_ALTERA_JTAG_UART_BYPASS + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 7e812f2e9cdac80f6287d4aee5deb434597c4f8b +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Apr 17 23:34:40 2010 +0800 + + nios2: add dma_alloc_coherent + + This function return cache-line aligned allocation which is mapped + to uncached io region. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 0dc1c7f692c15fe1745e3eeab918e98ee6126677 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Apr 17 23:10:09 2010 +0800 + + nios2: add 64 bits swab support + + This patch adds 64 bits swab support. Most 32 bits processors use + this. We need 64 bits swab for UBI. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit e4bf588609d8d9cefbc312a6c6b8bb309b194fd5 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Wed Mar 31 08:36:24 2010 +0800 + + nios2: add altera cf reset + + This patch toggles power to reset the cf card. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit dd168ef5b82255401e46a27faae09e39c66967fe +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Apr 17 17:39:12 2010 +0800 + + nios2: allow link script overriding from boards + + This patch allow boards to override the default link script. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 29fd7ceb3c1cb7ffaffce1047e806d1e85e3ab4b +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:11 2010 +0200 + + mpc5121: pdm360ng: add coprocessor POST + + Adds coprocessor communication POST code + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit 2ebdb9a9d7abcb17fdbfdc4bbb71b4ef538fc713 +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:10 2010 +0200 + + mpc5121: add common post_word_load/store code + + Add common post_word_load/post_word_store routines + for all mpc5121 boards. pdm360ng board POST support + added by subsequent patch needs them. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit a3921eefa1440d23f22751704cd7df999769f169 +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:09 2010 +0200 + + mpc5121: add support for PDM360NG board + + PDM360NG is a MPC5121E based board by ifm ecomatic gmbh. + + Signed-off-by: Michael Weiss <michael.weiss@ifm.com> + Signed-off-by: Detlev Zundel <dzu@denx.de> + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit b9947bbb08d0483be03004bdbce283b644471cb7 +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:08 2010 +0200 + + mpc5121: determine RAM size using get_ram_size() + + Configure CONFIG_SYS_MAX_RAM_SIZE address range in + DDR Local Access Window and determine the RAM size. + Fix DDR LAW afterwards using detected RAM size. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit 5d937e8b59f27d8c300a2e78c168a4c22ec6922a +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:07 2010 +0200 + + mpc512x: make MEM IO Control configuration a board config option + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit 8e234e33bf60a850685c7e81ea92d383c643486b +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:06 2010 +0200 + + mpc5121: add PSC serial communication routines + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit e3b28e67329de99a315d509920760dcbc565f8c6 +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:05 2010 +0200 + + mpc512x: add multi serial PSC support + + Extend mpc512x serial driver to support multiple PSC ports. + + Subsequent patches for PDM360NG board support make use of this + functionality by defining CONFIG_SERIAL_MULTI in the board config + file. Additionally the used PSC devices are specified by defining + e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6. + + Support for PSC devices other than 1, 3, 4 and 6 is not added + by this patch because these aren't used currently. In the future + it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and + INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c. + Additionally you have to add code for registering added + devices in serial_initialize() in common/serial.c. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit fbb0030e3894119c089256f16626edd166c7629c +Author: Anatolij Gustschin <agust@denx.de> +Date: Sat Apr 24 19:27:04 2010 +0200 + + serial: struct serial_device: add uninit() entry for drivers + + Subsequent patch extends mpc512x serial driver to support + multiple PSC ports. The driver will provide an uninit() + function to stop the serial controller and to disable the + controller's clock. Adding uninit() entry to struct serial_device + allows disabling the serial controller after usage of + a stdio serial device. + + This patch adds uninit() entry to the struct serial_device + and fixes initialization of this structure in the code + accordingly. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit 77c1458d130d33704472db9c88d2310c8fc90f4c +Author: Dipen Dudhat <dipen.dudhat@freescale.com> +Date: Mon Oct 5 15:41:58 2009 +0530 + + ppc/85xx: PIO Support for FSL eSDHC Controller Driver + + On some Freescale SoC Internal DMA of eSDHC controller has bug. + So PIO Mode has been introduced to do data transfer using CPU. + + Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> + +commit 1a2e203b31d33fb720f2cf1033b241ad36ab405a +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Apr 20 19:37:54 2010 -0500 + + mpc83xx: turn on icache in core initialization to improve u-boot boot time + + before, MPC8349ITX boots u-boot in 4.3sec: + + column1 is elapsed time since first message + column2 is elapsed time since previous message + column3 is the message + 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX + 0.000 0.000: + 0.000 0.000: Reset Status: + 0.000 0.000: + 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz + 0.032 0.000: Board: Freescale MPC8349E-mITX + 0.032 0.000: UPMA: Configured for compact flash + 0.032 0.000: I2C: ready + 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) + 1.516 1.456: FLASH: 16 MB + 2.641 1.125: PCI: Bus Dev VenId DevId Class Int + 2.652 0.011: 00 10 1095 3114 0180 00 + 2.652 0.000: PCI: Bus Dev VenId DevId Class Int + 2.652 0.000: In: serial + 2.652 0.000: Out: serial + 2.652 0.000: Err: serial + 2.682 0.030: Board revision: 1.0 (PCF8475A) + 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic + 3.080 0.000: TSEC0, TSEC1 + 4.300 1.219: IDE: Bus 0: .** Timeout ** + + after, MPC8349ITX boots u-boot in 3.0sec: + + 0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX + 0.010 0.000: + 0.010 0.000: Reset Status: + 0.010 0.000: + 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz + 0.017 0.000: Board: Freescale MPC8349E-mITX + 0.038 0.020: UPMA: Configured for compact flash + 0.038 0.000: I2C: ready + 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) + 0.260 0.222: FLASH: 16 MB + 1.390 1.130: PCI: Bus Dev VenId DevId Class Int + 1.390 0.000: 00 10 1095 3114 0180 00 + 1.390 0.000: PCI: Bus Dev VenId DevId Class Int + 1.400 0.010: In: serial + 1.400 0.000: Out: serial + 1.400 0.000: Err: serial + 1.400 0.000: Board revision: 1.0 (PCF8475A) + 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic + 1.832 0.000: TSEC0, TSEC1 + 3.038 1.205: IDE: Bus 0: .** Timeout ** + + also tested on these boards (albeit with a less accurate + boottime measurement method): + + seconds: before after + 8349MDS ~2.6 ~2.2 + 8360MDS ~2.8 ~2.6 + 8313RDB ~2.5 ~2.3 #nand boot + 837xRDB ~3.1 ~2.3 + + also tested on an 8323ERDB. + + v2: also remove the delayed icache enablement assumption in arch ppc's + board.c, and add a CONFIG_MPC83xx define in the ITX config file for + consistency (even though it was already being defined in 83xx' + config.mk). + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit a059e90e16e126e25da33ce23a37e2acce84284c +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Apr 15 17:36:05 2010 -0500 + + mpc83xx: enable command line autocompletion + + because it's convenient. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit dfe812c744ee6dacae3b4d553694642668d9ac9d +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Apr 15 17:36:02 2010 -0500 + + mpc83xx: use "A" nomenclature only on mpc834x and mpc836x families + + marketing didn't extend their postpend-with-an-A naming strategy + on rev.2's and higher beyond the first two 83xx families. This + patch stops us from misreporting we're running e.g., on an MPC8313EA, + when such a name doesn't exist. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 27ef578df7b9c7862c36a31b819c652f8b0aeea0 +Author: Rini van Zetten <rini@arvoo.nl> +Date: Thu Apr 15 16:03:05 2010 +0200 + + mpc83xx: Use CONFIG_FSL_ESDHC to enable sdhc clk + + Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define + instead of a platform define. This will enable all the 83xx + platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. It's + the same patch as commit 6b9ea08c5010eab5ad1056bc9bf033afb672d9cc + for the ppc/85xx. + + Signed-off-by: Rini <rini@arvoo.nl> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit a47a12becf66f02a56da91c161e2edb625e9f20c +Author: Stefan Roese <sr@denx.de> +Date: Thu Apr 15 16:07:28 2010 +0200 + + Move arch/ppc to arch/powerpc + + As discussed on the list, move "arch/ppc" to "arch/powerpc" to + better match the Linux directory structure. + + Please note that this patch also changes the "ppc" target in + MAKEALL to "powerpc" to match this new infrastructure. But "ppc" + is kept as an alias for now, to not break compatibility with + scripts using this name. + + Signed-off-by: Stefan Roese <sr@denx.de> + Acked-by: Wolfgang Denk <wd@denx.de> + Acked-by: Detlev Zundel <dzu@denx.de> + Acked-by: Kim Phillips <kim.phillips@freescale.com> + Cc: Peter Tyser <ptyser@xes-inc.com> + Cc: Anatolij Gustschin <agust@denx.de> + +commit cf6eb6da433179674571f9370566b1ec8989a41a +Author: Stefan Roese <sr@denx.de> +Date: Wed Apr 14 13:57:18 2010 +0200 + + ppc4xx: TLB init file cleanup + + This patch adds new macros, with frequently used combinations of the + 4xx TLB access control and storage attibutes. Additionally the 4xx init.S + files are updated to make use of these new macros. Resulting in easier + to read TLB definitions. + + Additionally some init.S files are updated to use the mmu header for the + TLB defines, instead of defining their own macros. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 26a33504a55e4882520f2e9da96ba6c22badb353 +Author: Richard Retanubun <RichardRetanubun@RuggedCom.com> +Date: Mon Apr 12 15:08:17 2010 -0400 + + fsl_i2c: Added a callpoint for i2c_board_late_init + + This patch adds a callpoint in i2c_init that allows board specific + i2c board initialization (typically for i2c bus reset) that is called + after i2c_init operations, allowing the i2c_board_late_init function + to use the pre-configured i2c bus speed and slave address. + +commit 254ab7bd464657600aba69d840406f9358f3e116 +Author: Scott McNutt <smcnutt@psyent.com> +Date: Fri Apr 16 16:12:39 2010 -0400 + + nios2: Move individual board linker scripts to common script in cpu tree. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 8ff972c6e99938f1a033e5500dccc9a37ce3406f +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 12:56:33 2010 +0200 + + microblaze: Consolidate cache code + + Merge cpu and lib cache code. + Flush cache before disabling. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 9b4d90569028604bc491ea419187c31e4467bdca +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 12:01:32 2010 +0200 + + microblaze: Flush cache before jumping to kernel + + There is used max cache size on system which doesn't define + cache size. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 70524883b0424277e5b3ff3768c0c5628b5fce44 +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:59:29 2010 +0200 + + microblaze: Support system with WB cache + + WB cache use different instruction that WT cache but the major code + is that same. That means that wdc.flush on system with WT cache + do the same thing as before. + + You need newer toolchain with wdc.flush support. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 9769b73f60fc0fb8de7ab16ff6300eae56505020 +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:57:35 2010 +0200 + + microblaze: Change initialization sequence + + env_relocation should be called first. + Added stdio_init too. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit e6177b36b87d0ce627651e407b91245f16e5382e +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:55:01 2010 +0200 + + microblaze: Change cache report messages + + It is more accurate to show that caches are OFF instead of FAIL. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 8125c980cc282000cbddb415f8ddbebf96e4edb4 +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:51:59 2010 +0200 + + microblaze: Fix interrupt handler code + + It is better to read ivr and react on it than do long parsing from + two regs. Interrupt controller returs actual irq number. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit b26640971a7ba8800f0eb32af145ff0727fe21fe +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:43:43 2010 +0200 + + microblaze: Move FSL initialization to board.c + + Move FSL out of interrupt controller. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 5bbcb6cf22b1121d8c3e56b0e1fb84366e903ac7 +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:37:41 2010 +0200 + + microblaze: Move timer initialization to board.c + + I would like to handle case where system doesn't contain + intc that's why I need timer initialization out of intc code. + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit cc53690e05f47b4c25e0a528de50e024fc0164ad +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Apr 16 11:30:16 2010 +0200 + + microblaze: Fix irq.S code + + It is ancient code. There is possible to save several instructions + just if we use offset instead of addik + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 398b1d57a6a56aada1f77198746a7dd1b038cd5d +Author: Arun Bhanu <arun@bhanu.net> +Date: Thu Apr 15 18:27:17 2010 +0800 + + microblaze: Add FDT support + + This patch adds FDT (flattened device tree) support to microblaze arch. + + Tested with Linux arch/microblaze kernels with and without compiled in + FDT on Xilinx ML506 board. + + Signed-off-by: Arun Bhanu <arun@bhanu.net> + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 2a72e9ed18d2164eb7fe569119342eb631b568da +Author: Stefan Roese <sr@denx.de> +Date: Fri Apr 9 14:03:59 2010 +0200 + + ppc4xx: Add option for PPC440SPe ports without old Rev. A support + + The 440SPe Rev. A is quite old and newer 440SPe boards don't need support + for this CPU revision. Since removing support for this older version + simplifies the creation for newer U-Boot ports, this patch now enables + 440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By + defining this in the board config header, Rev. A will still be supported. + Otherwise (default for newer board ports), Rev. A will not be supported. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 288991c93fdd150ef3817e676c657cb487468d38 +Author: Stefan Roese <sr@denx.de> +Date: Thu Apr 8 09:33:13 2010 +0200 + + ppc4xx: alpr: Remove some not needed commands to make image fit again + + The latest changes increased the size of the alpr image a bit more. + Now it doesn't fit into the 256k reserved for it. This patch now removes + the commands "loads" and "loadb" which are not needed in the production + systems. + + Signed-off-by: Stefan Roese <sr@denx.de> + Cc: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl> + +commit 8d321b81c5441db93425ee37cb79cc51d9ce2fb0 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:21 2010 -0500 + + Update README to reflect new directory structure + + Also fix up some whitespace issues that were introduced when moving + directory locations. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 37e4dafaae96ccc970a896f90186fadcf858aad0 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:20 2010 -0500 + + nios2: Move cpu/nios2/* to arch/nios2/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 6a8a2b7058a398fe207021259cb2c529fb225eff +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:19 2010 -0500 + + nios: Move cpu/nios/* to arch/nios/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 1e9c26578ebbeecbaf3d8fb574957405eff17c86 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:18 2010 -0500 + + sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23] + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit e9a882803eb59f482ca4aa6ffd6fa21e4c53d618 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:17 2010 -0500 + + i386: Move cpu/i386/* to arch/i386/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 6260fb0458d94c83aa5b180745b1946c0c94d364 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:16 2010 -0500 + + microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 8a15c2d10b0b784f0cfba1240f06a4d933b975fa +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:15 2010 -0500 + + avr32: Move cpu/at32ap/* to arch/avr32/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 1e3827d9cf9442e188604fd1099ac38375135125 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:14 2010 -0500 + + mips: Move cpu/mips/* to arch/mips/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit c6fb83d21729321426308c3acff2a3dfb20d250b +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:13 2010 -0500 + + blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/* + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit a4145534851bf74619cb373a942613a74547bb82 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:12 2010 -0500 + + m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 84ad688473bec2875e171b71040eb9e033c6c206 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:11 2010 -0500 + + arm: Move cpu/$CPU to arch/arm/cpu/$CPU + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 8f0fec74ac6d0f3a7134ccebafa1ed9bd8c712ba +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:10 2010 -0500 + + sh: Move cpu/$CPU to arch/sh/cpu/$CPU + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 8d1f268204b07e172f3cb5cee0a3974d605b0b98 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:09 2010 -0500 + + ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 819833af39a91fa1c1e8252862bbda6f5a602f7b +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:08 2010 -0500 + + Move architecture-specific includes to arch/$ARCH/include/asm + + This helps to clean up the include/ directory so that it only contains + non-architecture-specific headers and also matches Linux's directory + layout which many U-Boot developers are already familiar with. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 61f2b38a17f5b21c59f2afe6cf1cbb5f28638cf9 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:07 2010 -0500 + + Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>" + + The appropriate include/asm-$ARCH directory should already by symlinked + to include/asm so using the whole "asm-$ARCH" path is unnecessary. + + This change should also allow us to move the include/asm-$ARCH + directories into their appropriate lib/$ARCH/ directories. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 0de71d507157c4bd4fddcd3a419140d2b986eed2 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:06 2010 -0500 + + Move libfdt/ into lib/ + + Move the libfdt directory into the common lib/ directory to clean up the + top-level directory. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 78acc472d9719316f22e002a009a998d9ceec29d +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:05 2010 -0500 + + Rename lib_generic/ to lib/ + + Now that the other architecture-specific lib directories have been + moved out of the top-level directory there's not much reason to have the + '_generic' suffix on the common lib directory. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit ea0364f1bbfed1e3ea711147420875cf338fe77a +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:04 2010 -0500 + + Move lib_$ARCH directories to arch/$ARCH/lib + + Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk + + This change is intended to clean up the top-level directory structure + and more closely mimic Linux's directory organization. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 89f39e177e7b0152aa1d3152baa25d986e36cdcf +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:03 2010 -0500 + + Change directory-specific CFLAGS to use full path + + Previously, a specific file or directory could be compiled with custom + CFLAGS by adding a Makefile variable such as: + CFLAGS_dlmalloc.o = <custom flags for common/dlmalloc.c> + or + CFLAGS_lib = <custom flags for lib directory> + + This method breaks down once multiple files or directories share the + same path. Eg FLAGS_fileA = <custom flags> would incorrectly result in + both dir1/fileA.c and dir2/fileA.c being compiled with <custom flags>. + + This change allows finer grained control which we need once we move + lib_$ARCH to arch/$ARCH/lib/ and lib_generic/ to lib/. Without this + change all lib/ directories would share the same custom CFLAGS. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 03b7004ddafc70d83904d790abaa50843868130e +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Mon Apr 12 22:28:02 2010 -0500 + + Create CPUDIR variable + + The CPUDIR variable points to the location of a target's CPU directory. + Currently, it is set to cpu/$CPU. However, using $CPUDIR will allow for + more flexibility in the future. It lays the groundwork for reorganizing + U-Boot's directory structure to support a layout such as: + + arch/$ARCH/cpu/$CPU/* (architecture with multiple CPU types) + arch/$ARCH/cpu/* (architecture with one CPU type) + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 30dc165a76b5165af77219189bc05d0fa4229d8b +Author: Jens Scharsig <js_at_ng@scharsoft.de> +Date: Fri Apr 9 19:02:38 2010 +0200 + + FIX: watchdog timeout, while waiting for input + + * add WATCHDOG_RESET to !tstc() loops + * prevents watchdog timeout, while waiting for input, + if CONFIG_BOOT_RETRY_TIME or CONFIG_SHOW_ACTIVITY defined + + Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de> + +commit 8178110bc28249f3ff1c22b15d7dcdee50be69eb +Author: Detlev Zundel <dzu@denx.de> +Date: Thu Apr 8 17:55:48 2010 +0200 + + config_cmd_all.h: Sort entries alphabetically + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit 9157e9c40ab3a942bdd0679bb433cd9ed485f434 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Thu Apr 8 17:55:47 2010 +0200 + + config_cmd_all.h: added missing CONFIG_CMD_UBI and CONFIG_CMD_UBIFS + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit ae30b8c200dc071d719ad649d0bf5635d61754f3 +Author: karl.beldan@gmail.com <karl.beldan@gmail.com> +Date: Tue Apr 6 22:18:08 2010 +0200 + + malloc: sbrk() should return MORECORE_FAILURE instead of NULL on failure + + Signed-off-by: Karl Beldan <karl.beldan@gmail.com> + +commit a2513e27e8df2b7bf481d03e7719f91ce19e89d5 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Sun Apr 4 22:36:03 2010 -0500 + + mkimage: Fix strict-aliasing compiler warning + + Version 4.2.4 of gcc produces the following warnings without this change: + mkimage.c: In function ‘main’: + mkimage.c:204: warning: dereferencing type-punned pointer will break strict-aliasing rules + mkimage.c:222: warning: dereferencing type-punned pointer will break strict-aliasing rules + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit 1f2463d7642c582339c9f9d96471d5d2a169b9bb +Author: Andre Schwarz <andre.schwarz@matrix-vision.de> +Date: Thu Apr 1 21:26:55 2010 +0200 + + Add initial support for Matrix Vision mvSMR board based on MPC5200B. + + Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> + +commit 9acd4f0e914913796e4e56f550726d216f7b16e5 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Sat Mar 27 11:16:10 2010 +0100 + + cmd_bmp.c: add standard subcommand handling + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + Acked-by: Detlev Zundel <dzu@denx.de> + +commit f852a0c3bfe0b30b4816135b9a0d2aaae7e5de6a +Author: Albin Tonnerre <albin.tonnerre@free-electrons.com> +Date: Sun Mar 14 18:47:23 2010 +0100 + + drivers/mtd/spi/eeprom_m95xxx.c: add missing error checking + + Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> + +commit 3b653fdb322028b27c5ae3d60ecb0eea2d58837f +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Sun Apr 4 22:40:50 2010 -0500 + + cmd_ubi: Fix uninitialized variable warning + + gcc 3.4.6 previously reported the following error on many MIPS boards + which utilize UBI: + cmd_ubi.c:193: warning: 'vol' might be used uninitialized in this function + + The current code is structured such that 'vol' will never be used when + it is NULL anyway, but gcc isn't smart enough to figure this out. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit fac71cc49f93db7d460dbc957dfbbadefa2ca0e9 +Author: Kim B. Heino <Kim.Heino@bluegiga.com> +Date: Fri Mar 12 10:07:00 2010 +0200 + + USB storage probe + + While debugging one ill behaving USB device I found two bugs in USB + storage probe. + + usb_stor_get_info() returns -1 (error), 0 (skip) or 1 (ok). First part + of this patch fixes error case. + + Second part fixes usb_inquiry()'s retry counter handling. Original code + had retry = -1 on error case, not retry = 0 as checked in the next line. + + Signed-off-by: Kim B. Heino <Kim.Heino@bluegiga.com> + +commit aaad108b889c6980a2d05262a2f7febb14f94d68 +Author: Kim B. Heino <Kim.Heino@bluegiga.com> +Date: Fri Mar 12 15:46:56 2010 +0200 + + USB storage count + + Here's another USB storage patch. Currently U-Boot handles storage + devices #0 - #4 as valid devices, even if there is none connected. This + patch fixes usb_stor_get_dev() to check detected device count instead + of MAX-define. + + This is very important for ill behaving devices. usb_dev_desc[] can be + partially initialized if device probe fails. + + After fixing get_dev() it was easy to fix "usb part" etc commands. + Previously it outputed "Unknown partition table" five times, now it's + "no USB devices available". + + Signed-off-by: Kim B. Heino <Kim.Heino@bluegiga.com> + +commit d7a22a364ceea97133c1fb7aff073953c7a61228 +Author: Sergei Shtylyov <sshtylyov@ru.mvista.com> +Date: Sat Feb 27 21:34:41 2010 +0300 + + EHCI: add NEC PCI ID + + Add NEC EHCI controller to the list of the supported devices. + + Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> + + drivers/usb/host/ehci-pci.c | 1 + + 1 file changed, 1 insertion(+) + +commit c8b2d1dc0f1667029f42c3fa21f70906414af325 +Author: Sergei Shtylyov <sshtylyov@ru.mvista.com> +Date: Sat Feb 27 21:33:21 2010 +0300 + + EHCI: fix port reset reporting + + Commit b416191a14770c6bcc6fd67be7decf8159b2baee (Fix EHCI port reset.) didn't + move the code that checked for successful clearing of the port reset bit from + ehci_submit_root(), relying on wait_ms() call instead. The mentioned code also + erroneously reported port reset state when the reset was already completed. + + Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> + +commit e06a055bcd966adf62a5653c84db781915392e41 +Author: Sergei Shtylyov <sshtylyov@ru.mvista.com> +Date: Sat Feb 27 21:32:17 2010 +0300 + + EHCI: fix off-by-one error in ehci_submit_root() + + USB devices on the 2nd port are not detected and I get the following message: + + The request port(1) is not configured + + That's with default CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS value of 2. 'req->index' + is 1-based, so the comparison in ehci_submit_root() can't be correct. + + Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> + +commit 6d313c84ded168427240e62d108b6ba9afdcf535 +Author: Sergei Shtylyov <sshtylyov@ru.mvista.com> +Date: Sat Feb 27 21:29:42 2010 +0300 + + EHCI: fix root hub device descriptor + + On little endian machines, EHCI root hub's USB revision is reported as 0.2 -- + cpu_to_le16() was missed in the initializer for the 'bcdUSB' descriptor field. + The same should be done for the 'bcdDevice' field. + + Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com> + +commit 760bce07f182f678d42f2a85a0e47b59e831ba25 +Author: Anatolij Gustschin <agust@denx.de> +Date: Thu Apr 8 15:50:55 2010 +0200 + + video: ati_radeon_fb.c: fix warning while compiling with DEBUG + + Fixes this warning: + + ati_radeon_fb.c: In function 'radeon_probe': + ati_radeon_fb.c:598: warning: format '%x' expects type 'unsigned int', + but argument 2 has type 'void *' + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit f6a7a2e88854666e6a9ede50891fe415e803ace2 +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Wed Mar 31 15:52:40 2010 -0500 + + ati_radeon: Support PCI virtual not eq bus mapping. + + Use pci_bus_to_virt() to convert the bus address from the BARs to + virtual address' to eliminate the direct mapping requirement. + + Rename variables to better match usage (_phys -> _bus or no-suffix) + + This fixes the mpc8572ds CONFIG_PHYS_64BIT mode failure: + "videoboot: Video ROM failed to map!" + + Tested on mpc8572ds with and without CONFIG_PHYS_64BIT. + + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + +commit 9624f6d9eb4b7223e97a27844ec4489ab953a2e2 +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Wed Mar 31 09:54:28 2010 -0500 + + ati_radeon: return with error when emulator fails + + Console was being switched to video even if emulator fails and + causing this hang: + + Scanning PCI bus 04 + 04 00 1095 3132 0104 00 + PCIE3 on bus 03 - 04 + Video: ATI Radeon video card (1002, 5b60) found @(2:0:0) + videoboot: Booting PCI video card bus 2, function 0, device 0 + videoboot: Video ROM failed to map! + 640x480x8 31kHz 59Hz + radeonfb: FIFO Timeout ! + + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + Tested-by: Anatolij Gustschin <agust@denx.de> + +commit d5011762f53ada9cc7cdf1f89f3a722f887af577 +Author: Anatolij Gustschin <agust@denx.de> +Date: Mon Mar 15 14:50:25 2010 +0100 + + video: cfb_console.c: add support for RLE8 bitmaps + + Allow displaying 8-bit RLE BMP images. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit 22d6c8faac4e9fa43232b0cf4da427ec14d72ad3 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Thu Apr 1 11:15:05 2010 +0800 + + cfi_flash: reset timer in flash status check + + This patch adds reset_timer() before the flash status check + waiting loop. + + Since the timer is basically running asynchronous to the cfi + code, it is possible to call get_timer(0), then only a few + _SYSCLK_ cycles later an interrupt is generated. This causes + timeout even though much less time has elapsed. So the timer + period registers should be reset before get_timer(0) is + called. + + There is similar usage in nand_base.c. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 933419096e857275b8b01f1ae577162231b143ff +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Apr 7 01:34:11 2010 -0500 + + ppc/85xx: Use CONFIG_NS16550_MIN_FUNCTIONS to reduce NAND_SPL size + + The MPC8536DS_NAND SPL build was failing due to code size increase + introduced by commit: + + commit 33f57bd553edf29dffef5a6c7d76e169c79a6049 + Author: Kumar Gala <galak@kernel.crashing.org> + Date: Fri Mar 26 15:14:43 2010 -0500 + + 85xx: Fix enabling of L1 cache parity on secondary cores + + We built in some NS16550 functions that we dont need and can get + rid of them via CONFIG_NS16550_MIN_FUNCTIONS. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 5a4696088376fff82629e7e4a2444294dc589c96 +Author: Timur Tabi <timur@freescale.com> +Date: Thu Apr 1 10:49:42 2010 -0500 + + p2020ds: add alternate boot bank support using the ngPIXIS FPGA + + The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. + The ngPIXIS has one distinct new feature: the values of the on-board switches + can be selectively overridden with shadow registers. This feature is used to + boot from a different NOR flash bank, instead of having a register dedicated + for this purpose. Because the ngPIXIS is so different from the previous PIXIS, + a new file is introduced: ngpixis.c. + + Also update the P2020DS checkboard() function to use the new macros defined + in the header file. + + Signed-off-by: Timur Tabi <timur@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 2feb4af001a0be5ccad6e6a6eb072207cbef6e3f +Author: Timur Tabi <timur@freescale.com> +Date: Wed Mar 31 17:44:13 2010 -0500 + + fsl: improve the PIXIS code and fix a few bugs + + Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx + boards. This makes the code easier to read and more flexible. + + Delete pixis.h, because none of the exported functions were actually being + used by any other file. Make all of the functions in pixis.c 'static'. + Remove "#include pixis.h" from every file that has it. + + Remove some unnecessary #includes. + + Make 'pixis_base' into a macro, so that we don't need to define it in every + function. + + Add "while(1);" loops at the end of functions that reset the board, so that + execution doesn't continue while the reset is in progress. + + Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where + appropriate. + + Replace ulong/uint with their spelled-out equivalents. Remove unnecessary + typecasts, changing the types of some variables if necessary. + + Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make + it easier for specific boards to support variations in the PIXIS registers + sets. No current boards appears to need this feature. + + Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. + Apparently, "pixis_reset altbank" has never worked on this board. + + Signed-off-by: Timur Tabi <timur@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit ff8473e90a018c2bb19a196176c1f2e9602d6354 +Author: Sandeep Gopalpet <sandeep.kumar@freescale.com> +Date: Fri Mar 12 10:45:02 2010 +0530 + + 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater + + The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize + the performance of mbar/eieio instructions. + + Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> + +commit 216082754f6da5359ea0db9b0cc03ad531ac6e45 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Mar 30 23:06:53 2010 -0500 + + 85xx: Added various P1012/P1013/P1021/P1022 defines + + There are various locations that we have chip specific info: + + * Makefile for which ddr code to build + * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list + * Added number of LAWs for P1012/P1013/P1021/P1022 + * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 + * PCI port config + + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> + Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 5a85a3096940b0a0cd016c8acf4944421c64f8c7 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Mar 30 10:07:12 2010 -0500 + + ppc/8xxx: Delete PCI nodes from device tree if not configured + + If the PCI controller wasn't configured or enabled delete from the + device tree (include its alias). + + For the case that we didn't even configure u-boot with knowledge of + the controller we can use the fact that the pci_controller pointer + is NULL to delete the node in the device tree. We determine that + a controller was not setup (because of HW config) based on the fact + that cfg_addr wasn't setup. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 3f1a5c1655d32b7ab8ae74c79934ce100ebcd2bf +Author: Brent Kandetzki <BrentK@teleco.com> +Date: Wed Mar 24 17:41:33 2010 -0400 + + Blackfin: IP04: new board port + + A low cost 4 port IP-PBX board. + + Signed-off-by: Brent Kandetzki <BrentK@teleco.com> + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit a3c08363b927b84dee911bfcb29ab45d53c98f62 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Mar 23 16:23:39 2010 -0400 + + Blackfin: drop bfin #undef in linker script + + Now that the linker script is preprocessed with -ansi, there is no need to + manually undef the bfin define. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 0c080aa753eb92e1c0033d3fd33033b2b4813884 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Thu Feb 11 20:19:10 2010 -0500 + + Blackfin: call watchdog_init() for external watchdogs + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit b874ed17472de492cfbf58c8e362364bc80e3dcd +Author: Mike Frysinger <vapier@gentoo.org> +Date: Wed Feb 10 01:20:44 2010 -0500 + + Blackfin: link with normal ABI target + + If someone uses the FDPIC toolchain to compile U-Boot, make sure the + linker knows to use the normal ABI target rather than the FDPIC one. + This wasn't needed with older toolchains, but when we fixed the linker + such that the default target changed based on tuple, this broke. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit dd97022cbeaae5fd4bce25cf7e86019101a040ef +Author: Mike Frysinger <vapier@gentoo.org> +Date: Fri Jan 29 15:48:28 2010 -0500 + + Blackfin: sync ptrace headers with linux + + Scrub a lot of dead cruft in the process. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 6a0be8f8fe6d72a30e69d08decb72dc3bec5484c +Author: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at> +Date: Fri Jan 22 17:15:55 2010 -0500 + + Blackfin: cm-bf561: update network/env settings + + Switch to the SMC911X driver by default now, and fix LDR env settings. + + Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at> + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 216818c1a2d03b1c0994f00993c99af38c5b1e83 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Thu Jan 21 23:29:18 2010 -0500 + + Blackfin: bf537-stamp: add board test defines + + We tweak the configs a little when doing automated hardware tests. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 38b9b7446ecd3a728bad3e1913a984628a7363fb +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Jan 19 21:02:00 2010 -0500 + + Blackfin: relax .data alignment + + The strictest alignment on Blackfin systems is 32bits (since that is the + largest load instruction), so don't force 256byte alignment here. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 03f7053f70bc55b50c9d23e54f90d772419300a6 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Jan 19 15:39:07 2010 -0500 + + Blackfin: drop reference to gd->reloc_off + + The reloc_off member no longer exists, so drop it. Also change this + function so that it is always compiled and prevents latent issues like + this in the future. + + Reported-by: Peter Meerwald <pmeerw@pmeerw.net> + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 49b97d9c8ea7b11c4fc9e457cc2cd9fd6ebf0c21 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Mar 30 10:19:26 2010 -0500 + + fdt: Add fdt_del_node_and_alias helper + + Add a helper function that given an alias will delete both the node + the alias points to and the alias itself + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Gerald Van Baren <vanbaren@cideas.com> + +commit 459c41a8e1be96edeba1c0afeccacafd93b2c4e6 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Nov 3 15:53:12 2009 -0500 + + Blackfin: disable NetBSD bootm support by default + + There is no Blackfin/NetBSD port, so enabling support for it by default + doesn't make any sense. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 69bcf5bc80a47acbd62b8cfff932cb12d47997d7 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Mar 29 13:50:31 2010 -0500 + + 85xx: Add defines for BUCSR bits to make code more readable + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 22c9de064a218ae617bfeea35d2164532df91597 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Mar 5 12:22:00 2010 +0800 + + fsl-ddr: change the default burst mode for DDR3 + + For 64B cacheline SoC, set the fixed 8-beat burst len, + for 32B cacheline SoC, set the On-The-Fly as default. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit ec145e87b80f6764d17a6b0aebf521fe758c3fdc +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Mar 5 12:22:00 2010 +0800 + + fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 + + Read-to-read/Write-to-write turnaround for same chip select + of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and + OTF case, BL/2 cycles is enough for fixed BL8. + Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 + will improve the memory performance. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit ab467c512e79dbd14f02352655f054a4304c457e +Author: Roy Zang <tie-fei.zang@freescale.com> +Date: Tue Feb 9 18:23:33 2010 +0800 + + fsl_esdhc: Only modify the field we are changing in WML + + When we set the read or write watermark in WML we should maintain the + rest of the register as is, rather than using some hard coded value. + + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + Acked-by: Stefano Babic <sbabic@denx.de> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 48bb3bb5ac4dd21e931ae157caad6449bcb2d0d4 +Author: Jerry Huang <Chang-Ming.Huang@freescale.com> +Date: Thu Mar 18 15:57:06 2010 -0500 + + fsl_esdhc: Add function to reset the eSDHC controller + + To support multiple block read command we must set abort or use auto + CMD12. If we booted from eSDHC controller neither of these are used + and thus we need to reset the controller to allow multiple block read + to function. + + Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + Acked-by: Stefano Babic <sbabic@denx.de> + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit cc4d1226585fa2544b5116702b02eacbb7aa48a1 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Mar 18 15:51:05 2010 -0500 + + fsl_esdhc: Always stop clock before changing frequency + + We need to stop the clocks on 83xx/85xx as well as imx. No need to make + this code conditional to just imx. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Stefano Babic <sbabic@denx.de> + +commit d0b0dcaa220549999d6ea74cf87487846c186a0f +Author: Stefan Roese <sr@denx.de> +Date: Thu Apr 1 14:37:24 2010 +0200 + + i2c: Move PPC4xx I2C driver into drivers/i2c directory + + This patch moves the PPC4xx specific I2C device driver into the I2C + drivers directory. All 4xx config headers are updated to include this + driver. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit b5045cdda556c73e2697cd1d3ea6563315cbf490 +Author: Detlev Zundel <dzu@denx.de> +Date: Wed Mar 31 15:38:55 2010 +0200 + + arm/integrator: Remove unneccessary CONFIG_PCI check. + + pci_eth_init() is already conditional to CONFIG_PCI so not every caller + needs to have conditionals. + + This is the only place in the current code base where such a check is + still at the calling site. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + CC: Ben Warren <biggerbadderben@gmail.com> + CC: Peter Pearse <peter.pearse@arm.com> + +commit 0701f730cebc8dd065b70812ca0332055dcf10f8 +Author: Matthias Fuchs <matthias.fuchs@esd.eu> +Date: Thu Mar 25 14:30:13 2010 +0100 + + at91: use C structs for AT91 OHCI code + + This patch is part of migrating the AT91 support towards + using C struct for all SOC access. + + It removes one more CONFIG_AT91_LEGACY warning. + + at91_pmc.h needs cleanup after migration of the drivers + has been done. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> + +commit e99056e3877d1f04a36991aa48f1c690547f5ab9 +Author: Asen Dimov <dimov@ronetix.at> +Date: Thu Mar 18 13:46:45 2010 +0200 + + using AT91_PMC_MCKR_MDIV_ instead of LEGACY one in at91/clock.c + + Signed-off-by: Asen Dimov <dimov@ronetix.at> + +commit 4b894a97d307c3207af40031d9e820e2960de57f +Author: Alessandro Rubini <rubini@unipv.it> +Date: Wed Nov 25 23:41:51 2009 +0100 + + Nomadik: fix reset_timer() + + Previous code was failing when reading back the timer less than + 400us after resetting it. This lead nand operations to incorrectly + timeout any now and then. Moreover, writing the load register isn't + immediately reflected in the value register. We must wait for a clock + edge, so read_timer now waits for the value to change at least once, + otherwise nand operation would timeout anyways (though less frequently). + + Signed-off-by: Alessandro Rubini <rubini@unipv.it> + Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> + +commit f936aa0528fe4f5d86168575528e0c52b485c642 +Author: Achim Ehrlich <aehrlich@taskit.de> +Date: Wed Mar 17 14:50:29 2010 +0100 + + Convert at91 watchdog driver to new SoC access + + This converts the at91 watchdog driver to new c structure + type to access registers of the SoC + + Signed-off-by: Achim Ehrlich <aehrlich@taskit.de> + +commit c9f72b3da8855c3c9679c821127cccd91e0380ed +Author: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu> +Date: Wed Mar 17 08:21:11 2010 +0100 + + at91: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT + + CONFIG_CMD_AUTOSCRIPT support is deprecated and non-existing + This clean up patch removes the references for esd boards + + Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu> + +commit b032698ff687034286c98c09fd4830d804cd1786 +Author: Matthias Kaehlcke <matthias@kaehlcke.net> +Date: Tue Mar 9 22:13:56 2010 +0100 + + ep93xx timer: refactoring + + ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and + performing (almost) all manipulation of the timer structure in read_timer() + + Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> + +commit 33eef04bf8541f7b15d4f694ad10f9b912b9caa6 +Author: Matthias Kaehlcke <matthias@kaehlcke.net> +Date: Tue Mar 9 22:13:47 2010 +0100 + + ep93xx timer: Rename struct timer_reg pointers + + ep93xx timer: Renamed pointers to struct timer_regs from name 'timer' to + 'timer_regs' in order to avoid confusion with the global variable 'timer' + + Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> + +commit 2528dc52361bea49e6bd4a95ce2374d0004ca56f +Author: Naveen Krishna CH <ch.naveen@samsung.com> +Date: Fri Mar 5 17:16:05 2010 +0900 + + SAMSUNG: SMDKC100: Adds ethernet support. + + Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be + loaded over tftp. + + The preinit function will configure GPIO (GPK0CON) & SROMC to look + for environment in SROM Bank 3. + + Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit 01802e0d22a4bb3903b342ff2357ea3bbcccd289 +Author: Naveen Krishna CH <ch.naveen@samsung.com> +Date: Fri Mar 5 17:15:38 2010 +0900 + + S5PC100: Function to configure the SROMC registers. + + Nand Flash, Ethernet, other features might need to configure the + SROMC registers accordingly. + The config_sromc() functions helps with this. + + Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit a28bec89ccc17b56a50d841c8f0778e927434d1c +Author: Naveen Krishna CH <ch.naveen@samsung.com> +Date: Fri Mar 5 17:15:13 2010 +0900 + + S5PC100: Memory SubSystem Header file, register description(SROMC). + + Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand, + NAND Flash, DDRs. + smc.h is a common place for the register description of Memory subsystem + of S5PC100. + Note: Only SROM related registers are descibed now. + + Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit abbe18c353c297a40c428ba92f3e1a85e8e694fc +Author: Minkyu Kang <mk7.kang@samsung.com> +Date: Fri Feb 12 18:21:17 2010 +0900 + + s5pc1xx: update the README file + + Because adds support the GPIO Interface, README file is updated. + + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit ab693e9c4c06b42d1746a0d7a03541968fb55bb9 +Author: Minkyu Kang <mk7.kang@samsung.com> +Date: Fri Feb 12 18:17:52 2010 +0900 + + s5pc1xx: support the GPIO interface + + This patch adds support the GPIO interface + + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit 7b92159bd9fc0acaddd65b314da252b715d1b44e +Author: Joonyoung Shim <jy0922.shim@samsung.com> +Date: Mon Feb 8 22:00:52 2010 +0900 + + s3c64xx: Add ifdef at the S3C64XX only codes + + The s3c6400.h file is only for S3C64XX cpu and the pheripheral port + address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they + should be included by only S3C64XX cpu. + + Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit 6c71a8fec95a9e0f90fbc47469c389c6f35d96bc +Author: Naveen Krishna CH <ch.naveen.samsung.com> +Date: Thu Feb 4 14:17:38 2010 +0900 + + S5PC100: Moves the Macros to a common header file + + The get_pll_clk(int) API returns the PLL frequency based on + the (int) argument which is defined locally in clock.c + + Moving that #define to common header file (clk.h) would + be helpful when using the API from other files. + + Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit 2ca551dd7ad6ec11418f113b1b50c96fdd15a370 +Author: Minkyu Kang <mk7.kang@samsung.com> +Date: Mon Mar 8 16:22:33 2010 +0900 + + MAINTAINERS: sort the list of ARM Maintainers by last name + + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> + +commit c937c42431923c96a617e9462e2c0ecbaf2ad72d +Author: Vipin KUMAR <vipin.kumar@st.com> +Date: Mon Mar 8 10:46:07 2010 +0530 + + SPEAr : Adding maintainer name for spear SoCs + + Signed-off-by: Vipin Kumar <vipin.kumar@st.com> + +commit d8bc0a2889700ba063598de6d4e7d135360b537e +Author: Scott McNutt <smcnutt@psyent.com> +Date: Thu Apr 1 00:00:56 2010 -0400 + + nios2: Reload timer count in reset_timer() + + When the timestamp is incremented via interrupt and the interrupt + period is greater than 1 msec, successive calls to get_timer() can + produce inaccurate timing since the interrupts are asynchronous + to the timing loop. For example, with an interrupt period of 10 msec + two successive calls to get_timer() could indicate an elapsed time + of 10 msec after only several hundred usecs -- depending on when + the next interrupt actually occurs. This behavior can cause + reliability issues with components such as CFI and NAND. + + This can be remedied by calling reset_timer() prior to establishing + the base timestamp with get_timer(0), provided reset_timer() + resets the hardware timer (rather than simply resetting only the + timestamp). This has the effect of synchronizing the interrupts + (and the advance of the timestamp) with the timing loop. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit ed2941578480d30b413e081b6f1a5675d4afd9e2 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Wed Mar 24 11:41:46 2010 +0800 + + nios2: pass command line and initrd to linux in bootm.c + + This patch adds bootargs passing to nios2 linux. + + The args passing is enabled with, + r4 : 'NIOS' magic + r5 : pointer to initrd start + r6 : pointer to initrd end + r7 : pointer to command line + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 9e486ab1c98ea7ab357520307fe5d5a0847cd1bb +Author: Scott McNutt <smcnutt@psyent.com> +Date: Tue Mar 30 20:26:15 2010 -0400 + + nios2: Fix AMDLV065D flash write bug in altera board common tree. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 3a89a91a10fed545af458418e63d911953a9849c +Author: Scott McNutt <smcnutt@psyent.com> +Date: Tue Mar 30 20:23:04 2010 -0400 + + nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards. + + CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration + headers. Updated comments to accurately describe timebase macros. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 3ea0037f2337de692b5fd2b6a4449db1de3067a2 +Author: Scott McNutt <smcnutt@psyent.com> +Date: Sun Mar 21 21:24:43 2010 -0400 + + nios2: Fix outx/writex parameter order in io.h + + The outx/writex macros were using writex(addr, val) rather than + the standard writex(val, addr), resulting in incompatibilty with + architecture independent components. This change set uses standard + parameter order. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 64da04d24ea685483f9afa07088f76931b6c0e01 +Author: Scott McNutt <smcnutt@psyent.com> +Date: Sun Mar 21 15:36:44 2010 -0400 + + nios2: Add support for EPCS16 and EPCS64 configuration devices. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 3fd2a1f3eb83a0bbb84a1397ff9c2af7e6f5d069 +Author: Scott McNutt <smcnutt@psyent.com> +Date: Sun Mar 21 13:26:33 2010 -0400 + + nios2: Add missing Ethernet initialization to board_init(). + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit c72bfafbc94e61ea3ff3915c84aa7f9d91a045a0 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Mar 20 07:05:47 2010 +0800 + + nios2: add struct stat support in linux/stat.h + + This is needed for jffs2 support. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 3bef253f0802c6292b8e2acc0089894019e99e62 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Mar 20 07:05:46 2010 +0800 + + nios2: use bitops from linux-2.6 asm-generic + + These are needed to use ubi/ubifs. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit d8b73dffa9866d6de3c05c8a2d07ecd4bc0d5d7e +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Mar 20 07:05:45 2010 +0800 + + nios2: add local_irq_enable/disable to asm-nios2/system.h + + Copy from linux header. This is needed for generic bitops. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 54d809e7553939629e8941ab9eef1f762463a2b3 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Sat Mar 20 07:05:44 2010 +0800 + + nios2: add asm-nios2/errno.h + + Just pull in asm-generic. + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit c9d4f46b5d639a45747d5eaabd31d35856cb918f +Author: Scott McNutt <smcnutt@psyent.com> +Date: Fri Mar 19 19:03:28 2010 -0400 + + nios2: Move serial drivers to individual files in drivers/serial + + The standard Altera UART & JTAG UART as well as the OpenCores + YANU driver are now in individual files in drivers/serial + rather than a single file uner cpu/nios2. + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Mar 31 23:54:39 2010 +0200 + + Prepare v2010.03 + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 8e64d6efd8d778a5f83d8bff9cd273a86dcc182f Author: Heiko Schocher <hs@denx.de> Date: Wed Mar 31 08:34:51 2010 +0200 @@ -140,6 +3729,53 @@ Date: Mon Mar 29 13:15:48 2010 +0200 Signed-off-by: Heiko Schocher <hs@denx.de> +commit fd03ea89641d6f6ade6d1a8580c1bb9f52b8542c +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Fri Mar 26 09:46:42 2010 +0100 + + i2c: made unused function i2c_mux_add_device static + + and removed it from the .h file + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit 2c0dc990202c69a6231122ec2463c4e3076a16f3 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Fri Mar 26 09:46:41 2010 +0100 + + cmd_i2c: introduced get_alen helper function + + The code to parse alen appeared 6 times in the function. + Factored this out in a small helper function + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit a266fe955a55bb7a03a67f3c91033068f317b337 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Fri Mar 26 09:46:40 2010 +0100 + + cmd_i2c: moved a define to before the functions + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit 4a8cf3382a6fea5cccc1e2ae61a4601bf26490c3 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Fri Mar 26 09:46:39 2010 +0100 + + cmd_i2c: moved mispositioned comment for i2c md + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit 3a6dcb988eee3fd3cd9c5ef96855a8da729a290e +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Fri Mar 26 09:46:38 2010 +0100 + + cmd_i2c.c: declared local functions as static + + Declared all functions that were not called outside the file as static + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + commit 2883cc2d48e99fd1873ef8af03fee7966611b735 Author: Wolfgang Denk <wd@denx.de> Date: Sun Mar 28 00:25:14 2010 +0100 @@ -183,6 +3819,27 @@ Date: Sat Mar 27 23:37:46 2010 +0100 Signed-off-by: Wolfgang Denk <wd@denx.de> +commit e5720823f6f81a0f3a9e3404dbc37059bf6644f1 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Fri Mar 26 08:17:00 2010 +0800 + + cfi flash: add status polling method for amd flash + + This patch adds status polling method to offer an alternative to + data toggle method for amd flash chips. + + This patch is needed for nios2 cfi flash interface, where the bus + controller performs 4 bytes read cycles for a single byte read + instruction. The data toggle method can not detect chip busy + status correctly. So we have to poll DQ7, which will be inverted + when the chip is busy. + + This feature is enabled with the config def, + CONFIG_SYS_CFI_FLASH_STATUS_POLL + + Signed-off-by: Thomas Chou <thomas@wytron.com.tw> + Signed-off-by: Stefan Roese <sr@denx.de> + commit c40c94a3d20a8616264c2dfcda85279185d69aeb Author: Renato Andreola <renato.andreola@imagos.it> Date: Wed Mar 24 23:00:47 2010 +0800 @@ -196,6 +3853,205 @@ Date: Wed Mar 24 23:00:47 2010 +0800 Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de> +commit 9d3a86aec52cb3c0e9badd12167d9292184ce4dd +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Tue Mar 16 12:39:36 2010 -0500 + + ColdFire: Fix m54455EVB save environment bug + + The ATMEL flash does not have buffer write feature. Assgined + buffer_size = 1, so that when there is a write to the flash + will not use buffer write function. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit f26a247308568e32857a5cc054f7219510a7d44e +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Mon Mar 15 19:39:21 2010 -0500 + + ColdFire: Fix incorrect M5253DEMO default environment + + The flash location is at 0xff800000, not 0 + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit dd9f054ede433de73b137987fb3dc066e8d24ebb +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Thu Mar 11 22:12:53 2010 -0600 + + ColdFire: Cache update for all platforms + + The CF will call cache functions in lib_m68/cache.c and the + cache settings are defined in platform configuration file. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit f628e2f72daee810aa568619b6629da68ad042d6 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Wed Mar 10 18:50:22 2010 -0600 + + ColdFire: Fix SDRAM size on M5208evb rev E + + The proper SDRAM size is 32MB not 64MB + + Signed-off-by: Jingchang Lu <b22599@freescale.com> + +commit 9e8e927023582231b034e199568e49f84ac032a9 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Wed Mar 10 18:24:07 2010 -0600 + + ColdFire: Misc update for M53017 + + Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add + CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update + DRAM control and SRAM control register setting. Update cache + setting where size does not write to proper region. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit f9d877a6479878ca96688671f37d87b620c3e77c +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Wed Mar 10 17:32:13 2010 -0600 + + ColdFire: Add CPU compile flag for mcf5301x and mcf532x + + Add CPU compile flag -mcpu=53015 in cpu/config.mk + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit 0e8a75550695aba9d8cfe9c7f7713da42c1f3e89 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Wed Mar 10 16:33:03 2010 -0600 + + ColdFire: Update Extra environment Data for M5275EVB + + Provide extra environment Data. Remove default network + address and MAC address. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit 53e4290f20b5f73c95717f47f4c04ed6932ff931 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Wed Mar 10 16:14:01 2010 -0600 + + ColdFire: M5271EVB DRAM Bring up issue + + Fix proper portsize: The register for portsize is either 00b, 01b, + or 1xb. The value that previous assigned is 32d. + Fix DRAM bring up: insert asm("nop") for every DRAM register setup + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit ac265f7fcab1a09b9a837a34ef8b10acc101695e +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Wed Mar 10 11:56:36 2010 -0600 + + ColdFire: Update M5253DEMO configuration file + + Fix incorrect default environment for flash erase or protect + range. Change offset from 0 to 0xff80nnnn. Remove default + ethernet setup and MAC address. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit 68e4e76af55746a4330865f56476e58ce4140ca8 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Thu Mar 11 15:04:21 2010 -0600 + + ColdFire: Relocate vector table - mcf5445x + + Newer ColdFire processors family boot from address 0 instead of + 0xFFnn_nnnn. When the boot flash base chip select is set at new + location instead of 0, an un-predictable error will occur if + there is an vector being trigger and refer it to an invalid + address or the vector table handler is not existed at address + 0. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit fa9da596212d7f28eb26a3257d79d9515f9838cd +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Tue Mar 9 19:24:43 2010 -0600 + + ColdFire: Update uart_port_conf in serial driver + + Provide proper port passing from serial_init to uart_part_conf. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit 52affe04fa5493597d8a5f6202507190950a32e6 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Tue Mar 9 19:17:52 2010 -0600 + + ColdFire: Update processors' serial port configuration + + Provide parameter passing to uart_port_config(). Update port + configuration - un-mask it before enable the bits. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit d04c1efae3d834db6e21e9976e338bf1e588e987 +Author: TsiChung Liew <tsicliew@gmail.com> +Date: Tue Mar 9 18:32:16 2010 -0600 + + ColdFire: Correct bit definition + + Use correct definition for _MASK and _UNMASK. It was combined in + the previous used and causes confusion. + + Signed-off-by: TsiChung Liew <tsicliew@gmail.com> + +commit 116095eb1f0f7017ea8062aa8a8ba8ceecb430b5 +Author: Philippe De Muyter <phdm at macqel.be> +Date: Mon Sep 21 22:20:29 2009 -0600 + + fix cmd_bdinfo.c:354: warning: 'print_eth' defined but not used + + This fixes the following warnings when running MAKEALL for coldfire : + cmd_bdinfo.c:354: warning: 'print_eth' defined but not used + + Signed-off-by: Philippe De Muyter <phdm at macqel.be> + +commit dfc2b7697dc07862da804c1be084f96301884bc7 +Author: Michael Durrant <mdurrant@arcturusnetworks.com> +Date: Wed Jan 20 19:33:02 2010 -0600 + + Adding EP2500 MCF5282 board [PATCH] + + Mercury-EP2500.patch + - added Mercury's EP2500 board uses the mcf5282 processor + + CREDITS.patch + + Signed-off-by: David Wu <davidwu@arcturusnetworks.com> + Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> + +commit 89083346d0627a5e6e271e61bd34ab5121f9462b +Author: Wolfgang Wegner <w.wegner@astro-kom.de> +Date: Fri Oct 30 16:55:02 2009 +0100 + + add block write function to spartan3 slave serial load + + Using seperate function calls for each bit-bang of slave serial + load can be painfully slow. This patch adds the possibility to + supply a block write function that loads the complete block of + data in one call (like it can already be done with Altera FPGAs). + On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load + time from around 15 seconds to around 3 seconds + + Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de> + +commit 9d79e5758c3a6776be9a86856823d28e7154a481 +Author: Wolfgang Wegner <w.wegner@astro-kom.de> +Date: Mon Jan 25 11:27:44 2010 +0100 + + add ASTRO MCF5373L board + + This patch adds support for ASTRO board(s) based on MCF5373L. + + Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de> + commit c550afada5fcad426aa6a219a329feb9eedae8b2 Author: Rupjyoti Sarmah <rsarmah@appliedmicro.com> Date: Wed Mar 24 16:52:02 2010 +0530 @@ -240,6 +4096,41 @@ Date: Sat Mar 13 17:44:08 2010 +0100 Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> +commit 6b94b4962211c16ee2197048faa887e1f92f3757 +Author: Florian Fainelli <f.fainelli@gmail.com> +Date: Sat Mar 20 19:02:58 2010 +0100 + + cmd_nand: show nand scrub confirmation character + + When issuing a nand scrub command, the entered character is not displayed + this may be confusing. This patch makes the input character being + displayed if it is a 'y' so that an user knows he is about to scrub his + nand. + + Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> + +commit 7c27b7b1eac43cdcda735bad6231cdfc1f602284 +Author: Nikolay Petukhov <nikolaypetukhov@gmail.com> +Date: Fri Mar 19 10:49:27 2010 +0500 + + at91: add hwecc method for nand + + This is a patch to use the hardware ECC controller of + the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. + + Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com> + +commit cc41a59a74ca9095d518d6d69655c6735dd00809 +Author: Cyril Chemparathy <cyril@ti.com> +Date: Wed Mar 17 10:03:10 2010 -0400 + + TI: Davinci: NAND Driver Cleanup + + Modified to use IO accessor routines consistently. Eliminated volatile usage + to keep checkpatch.pl happy. + + Signed-off-by: Cyril Chemparathy <cyril@ti.com> + commit 152dda3d94e97ede7af3f9560a59a659384d4585 Author: Wolfgang Denk <wd@denx.de> Date: Mon Mar 22 23:25:00 2010 +0100 @@ -272,6 +4163,160 @@ Date: Tue Mar 9 22:13:20 2010 +0100 Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> +commit 3c950e2ebfde083084cc926b020e3a22a536bf85 +Author: Anatolij Gustschin <agust@denx.de> +Date: Tue Mar 16 17:10:05 2010 +0100 + + fdt_support: add partitions fixup in mtd node + + Allow overwriting defined partitions in the device tree blob + using partition info defined in the 'mtdparts' environment + variable. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + Cc: Gerald Van Baren <vanbaren@cideas.com> + +commit d611295032c30e6c533cb356005fa82ab7992824 +Author: John Schmoller <jschmoller@xes-inc.com> +Date: Fri Mar 12 09:49:24 2010 -0600 + + cmd history: Match history buffer size to console buffer + + Match history buffer size to console buffer size. History buffer size + was hard coded to 256, artificially limiting the command buffer size. + The history buffer now tracks CONFIG_SYS_CBSIZE. + + Signed-off-by: John Schmoller <jschmoller@xes-inc.com> + +commit 6475b9f91bd33bfd38418469cabdcfc0fefbd848 +Author: John Schmoller <jschmoller@xes-inc.com> +Date: Fri Mar 12 09:49:23 2010 -0600 + + console: Fix console buffer overrun + + When CONFIG_SYS_CBSIZE equals MAX_CMDBUF_SIZE, a command string of + maximum length will overwrite part of the history buffer, causing the + board to die. Expand the console_buffer and hist_lines buffer by one + character each to hold the missing NULL char. + + Signed-off-by: John Schmoller <jschmoller@xes-inc.com> + +commit e070a56c777f1fd05950e1bc63483c19decd6f78 +Author: Michael Zaidman <michael.zaidman@gmail.com> +Date: Mon Mar 1 11:47:36 2010 +0200 + + POST: add progress API + + Add POST progress API implemented as weak calls before and after + each call to the POST test callback in the post_run_single routine + of the post.c file. + + Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com> + Acked-by: Detlev Zundel <dzu@denx.de> + +commit 47ab5ad14575531798431f0d1e8f83ee9bb0a87e +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Fri Feb 26 14:00:19 2010 +0100 + + cmd_setexpr: allow memory addresses in expressions + + This patch add functionality to use memory addresses in expressions. + This increases the power of expressions substantially + + It adheres to the standard convemtions: memory addresses can be given + in the format *address (e.g. *1000) + + Rationale for this change is that it allows masking off bits from a + byte that is obtained by reading data from e.g. i2c. + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + + Fix warning: control reaches end of non-void function + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 652e53546b23c25f80756287eaf607b713afdc87 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Thu Feb 25 10:12:16 2010 +0100 + + cmd_i2c.c: added i2c read to memory function + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit fb0070e9101a1f288d7054f7e80b3d808fd7ead2 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Thu Feb 25 10:12:15 2010 +0100 + + cmd_i2c.c: sorted commands alphabetically + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit bfc3b77ebe68435b46e988e3a440bc4857bc7cf4 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Thu Feb 25 10:12:14 2010 +0100 + + cmd_i2c.c: reworked subcommand handling + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit f74d9bd2a248efa229f0f3478fe331e2a319588c +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Thu Feb 25 10:12:13 2010 +0100 + + cmd_bootm.c: made subcommand array static + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit faffe14f016db10f33836b018c4b304d939cf586 +Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> +Date: Thu Feb 25 10:12:12 2010 +0100 + + cmd_i2c.c: reduced subaddress length to 3 bytes + + according to some of the comments the subaddress length is 1 or 2, but we are being + prepared for the case it becomes 3. However the code also accepted 4. + This repairs this by changing the constand 4 to 3. + + Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> + +commit a6a04967bc2957d20799f4bb2a6b3dd0353c1cfd +Author: Renato Andreola <renato.andreola@imagos.it> +Date: Tue Mar 16 16:01:29 2010 -0400 + + nios2: Added support to YANU UART + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit 352745ad487f72e839986ddbb020e1fe86c1d482 +Author: Thomas Chou <thomas@wytron.com.tw> +Date: Tue Mar 16 12:12:48 2010 -0400 + + nios2: use generic unaligned.h + + Signed-off-by: Scott McNutt <smcnutt@psyent.com> + +commit fd428c05c863aefb575b12b2a1916b02d5bfa759 +Author: Detlev Zundel <dzu@denx.de> +Date: Fri Mar 12 10:01:12 2010 +0100 + + mpc5xxx: Remove all references to MGT5100 + + We do not support a processor that never reached a real customer. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit c0c316569f70055eb7c70864aaa6d48666782600 +Author: Matthias Weisser <matthias.weisser@graf-syteco.de> +Date: Tue Jan 12 12:06:31 2010 +0100 + + video: Fix console display when splashscreen is used + + If a splashscreen is used the console scrolling used the + scroll size as needed when a logo was displayed. This + patch sets the scroll size to the whole screen if + a splashscreen is shown. + + Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> + commit daa989b47297c9f73426783599c286ef3a1f3f49 Author: Asen Dimov <dimov@ronetix.at> Date: Thu Mar 18 13:41:47 2010 +0200 diff --git a/MAINTAINERS b/MAINTAINERS index 7f688c3..5cbc845 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -372,6 +372,7 @@ Stefan Roese <sr@denx.de> ebony PPC440GP glacier PPC460GT haleakala PPC405EXr + icon PPC440SPe katmai PPC440SPe kilauea PPC405EX lwmon5 PPC440EPx @@ -186,6 +186,7 @@ LIST_4xx=" \ ADCIOP \ alpr \ AP1000 \ + APC405 \ AR405 \ arches \ ASH405 \ @@ -223,6 +224,7 @@ LIST_4xx=" \ hcu5 \ HH405 \ HUB405 \ + icon \ intip \ JSE \ KAREF \ @@ -22,9 +22,9 @@ # VERSION = 2010 -PATCHLEVEL = 03 +PATCHLEVEL = 06 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -38,9 +38,9 @@ HOSTARCH := $(shell uname -m | \ -e s/sun4u/sparc64/ \ -e s/arm.*/arm/ \ -e s/sa110/arm/ \ - -e s/powerpc/ppc/ \ - -e s/ppc64/ppc/ \ - -e s/macppc/ppc/) + -e s/ppc64/powerpc/ \ + -e s/ppc/powerpc/ \ + -e s/macppc/powerpc/) HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ sed -e 's/\(cygwin\).*/cygwin/') @@ -313,7 +313,7 @@ $(obj)u-boot.ldr.srec: $(obj)u-boot.ldr $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary $(obj)u-boot.img: $(obj)u-boot.bin - ./tools/mkimage -A $(ARCH) -T firmware -C none \ + $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ -a $(TEXT_BASE) -e 0 \ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ @@ -1357,6 +1357,9 @@ HH405_config: unconfig HUB405_config: unconfig @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hub405 esd +icon_config: unconfig + @$(MKCONFIG) $(@:_config=) powerpc ppc4xx icon mosaixtech + # Compact-Center(codename intip) & DevCon-Center use different U-Boot images intip_config \ devconcenter_config: unconfig @@ -3303,6 +3303,11 @@ o If both the SROM and the environment contain a MAC address, and the o If neither SROM nor the environment contain a MAC address, an error is raised. +If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses +will be programmed into hardware as part of the initialization process. This +may be skipped by setting the appropriate 'ethmacskip' environment variable. +The naming convention is as follows: +"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc. Image Formats: ============== diff --git a/arch/.gitignore b/arch/.gitignore new file mode 100644 index 0000000..a1fbe01 --- /dev/null +++ b/arch/.gitignore @@ -0,0 +1,2 @@ +/*/include/asm/arch +/*/include/asm/proc diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 7972ba0..b8848c4 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -151,7 +151,7 @@ void set_timer (ulong t) timestamp = time_to_tick(t); } -/* delay x useconds AND perserve advance timstamp value */ +/* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { unsigned long long tmp; diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c index 6754749..68fe1b2 100644 --- a/arch/arm/cpu/arm1136/omap24xx/timer.c +++ b/arch/arm/cpu/arm1136/omap24xx/timer.c @@ -73,25 +73,25 @@ void set_timer (ulong t) timestamp = t; } -/* delay x useconds AND perserve advance timstamp value */ +/* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { ulong tmo, tmp; - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } tmp = get_timer (0); /* get current timestamp */ - if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + if ( (tmo + tmp + 1) < tmp ) /* if setting this forward will roll time stamp */ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ else - tmo += tmp; /* else, set advancing stamp wake up time */ + tmo += tmp; /* else, set advancing stamp wake up time */ while (get_timer_masked () < tmo)/* loop till event */ /*NOP*/; } @@ -100,16 +100,16 @@ void reset_timer_masked (void) { /* reset time */ lastinc = READ_TIMER; /* capture current incrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ + timestamp = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked (void) { ulong now = READ_TIMER; /* current tick value */ - if (now >= lastinc) /* normal mode (non roll) */ + if (now >= lastinc) /* normal mode (non roll) */ timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ - else /* we have rollover of incrementer */ + else /* we have rollover of incrementer */ timestamp += (0xFFFFFFFF - lastinc) + now; lastinc = now; return timestamp; diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c index bb65593..d2e316f 100644 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ b/arch/arm/cpu/arm920t/a320/timer.c @@ -155,8 +155,8 @@ void set_timer(ulong t) timestamp = t; } -/* delay x useconds AND perserve advance timstamp value */ -void udelay(unsigned long usec) +/* delay x useconds AND preserve advance timestamp value */ +void __udelay(unsigned long usec) { long tmo = usec * (TIMER_CLOCK / 1000) / 1000; unsigned long now, last = readl(&tmr->timer3_counter); diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c index 2ac38c4..7d4b6e6 100644 --- a/arch/arm/cpu/arm926ejs/omap/timer.c +++ b/arch/arm/cpu/arm926ejs/omap/timer.c @@ -79,14 +79,14 @@ void set_timer (ulong t) timestamp = t; } -/* delay x useconds AND perserve advance timstamp value */ +/* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { ulong tmo, tmp; if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ }else{ /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c index 563db36..81d6749 100644 --- a/arch/arm/cpu/arm926ejs/versatile/timer.c +++ b/arch/arm/cpu/arm926ejs/versatile/timer.c @@ -108,14 +108,14 @@ void set_timer (ulong t) timestamp = t; } -/* delay x useconds AND perserve advance timstamp value */ +/* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { ulong tmo, tmp; if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ }else{ /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; diff --git a/arch/arm/cpu/arm_cortexa8/mx51/timer.c b/arch/arm/cpu/arm_cortexa8/mx51/timer.c index 8ecfec6..81c4a06 100644 --- a/arch/arm/cpu/arm_cortexa8/mx51/timer.c +++ b/arch/arm/cpu/arm_cortexa8/mx51/timer.c @@ -102,7 +102,7 @@ void set_timer(ulong t) timestamp = t; } -/* delay x useconds AND perserve advance timstamp value */ +/* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { unsigned long now, start, tmo; diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 513c635..940d814 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -2824,6 +2824,44 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_GINGER 2841 #define MACH_TYPE_TNY_T3530 2842 #define MACH_TYPE_PCA102 2843 +#define MACH_TYPE_SPADE 2844 +#define MACH_TYPE_MXC25_TOPAZ 2845 +#define MACH_TYPE_T5325 2846 +#define MACH_TYPE_GW2361 2847 +#define MACH_TYPE_ELOG 2848 +#define MACH_TYPE_INCOME 2849 +#define MACH_TYPE_BCM589X 2850 +#define MACH_TYPE_ETNA 2851 +#define MACH_TYPE_HAWKS 2852 +#define MACH_TYPE_MESON 2853 +#define MACH_TYPE_XSBASE255 2854 +#define MACH_TYPE_PVM2030 2855 +#define MACH_TYPE_MIOA502 2856 +#define MACH_TYPE_VVBOX_SDORIG2 2857 +#define MACH_TYPE_VVBOX_SDLITE2 2858 +#define MACH_TYPE_VVBOX_SDPRO4 2859 +#define MACH_TYPE_HTC_SPV_M700 2860 +#define MACH_TYPE_MX257SX 2861 +#define MACH_TYPE_GONI 2862 +#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863 +#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864 +#define MACH_TYPE_QUICKSTEP 2865 +#define MACH_TYPE_DMW96 2866 +#define MACH_TYPE_HAMMERHEAD 2867 +#define MACH_TYPE_TRIDENT 2868 +#define MACH_TYPE_LIGHTNING 2869 +#define MACH_TYPE_ICONNECT 2870 +#define MACH_TYPE_AUTOBOT 2871 +#define MACH_TYPE_COCONUT 2872 +#define MACH_TYPE_DURIAN 2873 +#define MACH_TYPE_CAYENNE 2874 +#define MACH_TYPE_FUJI 2875 +#define MACH_TYPE_SYNOLOGY_6282 2876 +#define MACH_TYPE_EM1SY 2877 +#define MACH_TYPE_M502 2878 +#define MACH_TYPE_MATRIX518 2879 +#define MACH_TYPE_TINY_GURNARD 2880 +#define MACH_TYPE_SPEAR1310 2881 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -23964,9 +24002,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_MARVELL_NEWDB # endif -# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) +# define machine_is_dove_avng() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) #else -# define machine_is_marvell_newdb() (0) +# define machine_is_dove_avng() (0) #endif #ifdef CONFIG_MACH_VANDIHUD @@ -32616,9 +32654,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_WHITESTONE # endif -# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) +# define machine_is_htcwhitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) #else -# define machine_is_whitestone() (0) +# define machine_is_htcwhitestone() (0) #endif #ifdef CONFIG_MACH_AT91SAM9263NIT @@ -35772,9 +35810,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_LPC2 # endif -# define machine_is_lpc2() (machine_arch_type == MACH_TYPE_LPC2) +# define machine_is_lpc_evo() (machine_arch_type == MACH_TYPE_LPC2) #else -# define machine_is_lpc2() (0) +# define machine_is_lpc_evo() (0) #endif #ifdef CONFIG_MACH_OLYMPUS @@ -36569,6 +36607,462 @@ extern unsigned int __machine_arch_type; # define machine_is_pca102() (0) #endif +#ifdef CONFIG_MACH_SPADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPADE +# endif +# define machine_is_spade() (machine_arch_type == MACH_TYPE_SPADE) +#else +# define machine_is_spade() (0) +#endif + +#ifdef CONFIG_MACH_MXC25_TOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC25_TOPAZ +# endif +# define machine_is_mxc25_topaz() (machine_arch_type == MACH_TYPE_MXC25_TOPAZ) +#else +# define machine_is_mxc25_topaz() (0) +#endif + +#ifdef CONFIG_MACH_T5325 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T5325 +# endif +# define machine_is_t5325() (machine_arch_type == MACH_TYPE_T5325) +#else +# define machine_is_t5325() (0) +#endif + +#ifdef CONFIG_MACH_GW2361 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2361 +# endif +# define machine_is_gw2361() (machine_arch_type == MACH_TYPE_GW2361) +#else +# define machine_is_gw2361() (0) +#endif + +#ifdef CONFIG_MACH_ELOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELOG +# endif +# define machine_is_elog() (machine_arch_type == MACH_TYPE_ELOG) +#else +# define machine_is_elog() (0) +#endif + +#ifdef CONFIG_MACH_INCOME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCOME +# endif +# define machine_is_income() (machine_arch_type == MACH_TYPE_INCOME) +#else +# define machine_is_income() (0) +#endif + +#ifdef CONFIG_MACH_BCM589X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM589X +# endif +# define machine_is_bcm589x() (machine_arch_type == MACH_TYPE_BCM589X) +#else +# define machine_is_bcm589x() (0) +#endif + +#ifdef CONFIG_MACH_ETNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETNA +# endif +# define machine_is_etna() (machine_arch_type == MACH_TYPE_ETNA) +#else +# define machine_is_etna() (0) +#endif + +#ifdef CONFIG_MACH_HAWKS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAWKS +# endif +# define machine_is_hawks() (machine_arch_type == MACH_TYPE_HAWKS) +#else +# define machine_is_hawks() (0) +#endif + +#ifdef CONFIG_MACH_MESON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON +# endif +# define machine_is_meson() (machine_arch_type == MACH_TYPE_MESON) +#else +# define machine_is_meson() (0) +#endif + +#ifdef CONFIG_MACH_XSBASE255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSBASE255 +# endif +# define machine_is_xsbase255() (machine_arch_type == MACH_TYPE_XSBASE255) +#else +# define machine_is_xsbase255() (0) +#endif + +#ifdef CONFIG_MACH_PVM2030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVM2030 +# endif +# define machine_is_pvm2030() (machine_arch_type == MACH_TYPE_PVM2030) +#else +# define machine_is_pvm2030() (0) +#endif + +#ifdef CONFIG_MACH_MIOA502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA502 +# endif +# define machine_is_mioa502() (machine_arch_type == MACH_TYPE_MIOA502) +#else +# define machine_is_mioa502() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDORIG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDORIG2 +# endif +# define machine_is_vvbox_sdorig2() (machine_arch_type == MACH_TYPE_VVBOX_SDORIG2) +#else +# define machine_is_vvbox_sdorig2() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDLITE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDLITE2 +# endif +# define machine_is_vvbox_sdlite2() (machine_arch_type == MACH_TYPE_VVBOX_SDLITE2) +#else +# define machine_is_vvbox_sdlite2() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDPRO4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDPRO4 +# endif +# define machine_is_vvbox_sdpro4() (machine_arch_type == MACH_TYPE_VVBOX_SDPRO4) +#else +# define machine_is_vvbox_sdpro4() (0) +#endif + +#ifdef CONFIG_MACH_HTC_SPV_M700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_SPV_M700 +# endif +# define machine_is_htc_spv_m700() (machine_arch_type == MACH_TYPE_HTC_SPV_M700) +#else +# define machine_is_htc_spv_m700() (0) +#endif + +#ifdef CONFIG_MACH_MX257SX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX257SX +# endif +# define machine_is_mx257sx() (machine_arch_type == MACH_TYPE_MX257SX) +#else +# define machine_is_mx257sx() (0) +#endif + +#ifdef CONFIG_MACH_GONI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GONI +# endif +# define machine_is_goni() (machine_arch_type == MACH_TYPE_GONI) +#else +# define machine_is_goni() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_FFA +# endif +# define machine_is_msm8x55_svlte_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA) +#else +# define machine_is_msm8x55_svlte_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_SURF +# endif +# define machine_is_msm8x55_svlte_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF) +#else +# define machine_is_msm8x55_svlte_surf() (0) +#endif + +#ifdef CONFIG_MACH_QUICKSTEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUICKSTEP +# endif +# define machine_is_quickstep() (machine_arch_type == MACH_TYPE_QUICKSTEP) +#else +# define machine_is_quickstep() (0) +#endif + +#ifdef CONFIG_MACH_DMW96 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DMW96 +# endif +# define machine_is_dmw96() (machine_arch_type == MACH_TYPE_DMW96) +#else +# define machine_is_dmw96() (0) +#endif + +#ifdef CONFIG_MACH_HAMMERHEAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAMMERHEAD +# endif +# define machine_is_hammerhead() (machine_arch_type == MACH_TYPE_HAMMERHEAD) +#else +# define machine_is_hammerhead() (0) +#endif + +#ifdef CONFIG_MACH_TRIDENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIDENT +# endif +# define machine_is_trident() (machine_arch_type == MACH_TYPE_TRIDENT) +#else +# define machine_is_trident() (0) +#endif + +#ifdef CONFIG_MACH_LIGHTNING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIGHTNING +# endif +# define machine_is_lightning() (machine_arch_type == MACH_TYPE_LIGHTNING) +#else +# define machine_is_lightning() (0) +#endif + +#ifdef CONFIG_MACH_ICONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONNECT +# endif +# define machine_is_iconnect() (machine_arch_type == MACH_TYPE_ICONNECT) +#else +# define machine_is_iconnect() (0) +#endif + +#ifdef CONFIG_MACH_AUTOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUTOBOT +# endif +# define machine_is_autobot() (machine_arch_type == MACH_TYPE_AUTOBOT) +#else +# define machine_is_autobot() (0) +#endif + +#ifdef CONFIG_MACH_COCONUT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COCONUT +# endif +# define machine_is_coconut() (machine_arch_type == MACH_TYPE_COCONUT) +#else +# define machine_is_coconut() (0) +#endif + +#ifdef CONFIG_MACH_DURIAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DURIAN +# endif +# define machine_is_durian() (machine_arch_type == MACH_TYPE_DURIAN) +#else +# define machine_is_durian() (0) +#endif + +#ifdef CONFIG_MACH_CAYENNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAYENNE +# endif +# define machine_is_cayenne() (machine_arch_type == MACH_TYPE_CAYENNE) +#else +# define machine_is_cayenne() (0) +#endif + +#ifdef CONFIG_MACH_FUJI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJI +# endif +# define machine_is_fuji() (machine_arch_type == MACH_TYPE_FUJI) +#else +# define machine_is_fuji() (0) +#endif + +#ifdef CONFIG_MACH_SYNOLOGY_6282 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYNOLOGY_6282 +# endif +# define machine_is_synology_6282() (machine_arch_type == MACH_TYPE_SYNOLOGY_6282) +#else +# define machine_is_synology_6282() (0) +#endif + +#ifdef CONFIG_MACH_EM1SY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM1SY +# endif +# define machine_is_em1sy() (machine_arch_type == MACH_TYPE_EM1SY) +#else +# define machine_is_em1sy() (0) +#endif + +#ifdef CONFIG_MACH_M502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M502 +# endif +# define machine_is_m502() (machine_arch_type == MACH_TYPE_M502) +#else +# define machine_is_m502() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX518 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX518 +# endif +# define machine_is_matrix518() (machine_arch_type == MACH_TYPE_MATRIX518) +#else +# define machine_is_matrix518() (0) +#endif + +#ifdef CONFIG_MACH_TINY_GURNARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY_GURNARD +# endif +# define machine_is_tiny_gurnard() (machine_arch_type == MACH_TYPE_TINY_GURNARD) +#else +# define machine_is_tiny_gurnard() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR1310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR1310 +# endif +# define machine_is_spear1310() (machine_arch_type == MACH_TYPE_SPEAR1310) +#else +# define machine_is_spear1310() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 86eacf1..eb3e26d 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -16,3 +16,8 @@ int raise (int signum) printf("raise: Signal # %d caught\n", signum); return 0; } + +/* Dummy function to avoid linker complaints */ +void __aeabi_unwind_cpp_pr0(void) +{ +}; diff --git a/arch/i386/cpu/Makefile b/arch/i386/cpu/Makefile index c658c6e..bb0a48f 100644 --- a/arch/i386/cpu/Makefile +++ b/arch/i386/cpu/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o start16.o resetvec.o -COBJS = serial.o interrupts.o cpu.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index 4b57437..51023f3 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -5,6 +5,9 @@ * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. * + * Portions of this file are derived from the Linux kernel source + * Copyright (C) 1991, 1992 Linus Torvalds + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,12 +35,112 @@ ".hidden irq_"#x"\n" \ ".type irq_"#x", @function\n" \ "irq_"#x":\n" \ - "pushl %ebp\n" \ - "movl %esp,%ebp\n" \ - "pusha\n" \ "pushl $"#x"\n" \ "jmp irq_common_entry\n" +/* + * Volatile isn't enough to prevent the compiler from reordering the + * read/write functions for the control registers and messing everything up. + * A memory clobber would solve the problem, but would prevent reordering of + * all loads stores around it, which can hurt performance. Solution is to + * use a variable and mimic reads and writes to it to enforce serialization + */ +static unsigned long __force_order; + +static inline unsigned long read_cr0(void) +{ + unsigned long val; + asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); + return val; +} + +static inline unsigned long read_cr2(void) +{ + unsigned long val; + asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order)); + return val; +} + +static inline unsigned long read_cr3(void) +{ + unsigned long val; + asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order)); + return val; +} + +static inline unsigned long read_cr4(void) +{ + unsigned long val; + asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order)); + return val; +} + +static inline unsigned long get_debugreg(int regno) +{ + unsigned long val = 0; /* Damn you, gcc! */ + + switch (regno) { + case 0: + asm("mov %%db0, %0" :"=r" (val)); + break; + case 1: + asm("mov %%db1, %0" :"=r" (val)); + break; + case 2: + asm("mov %%db2, %0" :"=r" (val)); + break; + case 3: + asm("mov %%db3, %0" :"=r" (val)); + break; + case 6: + asm("mov %%db6, %0" :"=r" (val)); + break; + case 7: + asm("mov %%db7, %0" :"=r" (val)); + break; + default: + val = 0; + } + return val; +} + +void dump_regs(struct pt_regs *regs) +{ + unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; + unsigned long d0, d1, d2, d3, d6, d7; + + printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n", + (u16)regs->xcs, regs->eip, regs->eflags); + + printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", + regs->eax, regs->ebx, regs->ecx, regs->edx); + printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", + regs->esi, regs->edi, regs->ebp, regs->esp); + printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", + (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss); + + cr0 = read_cr0(); + cr2 = read_cr2(); + cr3 = read_cr3(); + cr4 = read_cr4(); + + printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", + cr0, cr2, cr3, cr4); + + d0 = get_debugreg(0); + d1 = get_debugreg(1); + d2 = get_debugreg(2); + d3 = get_debugreg(3); + + printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n", + d0, d1, d2, d3); + + d6 = get_debugreg(6); + d7 = get_debugreg(7); + printf("DR6: %08lx DR7: %08lx\n", + d6, d7); +} + struct idt_entry { u16 base_low; u16 selector; @@ -122,7 +225,7 @@ int disable_interrupts(void) } /* IRQ Low-Level Service Routine */ -__isr__ irq_llsr(int ip, int seg, int irq) +__isr__ irq_llsr(struct pt_regs *regs) { /* * For detailed description of each exception, refer to: @@ -131,73 +234,92 @@ __isr__ irq_llsr(int ip, int seg, int irq) * Order Number: 253665-029US, November 2008 * Table 6-1. Exceptions and Interrupts */ - switch (irq) { + switch (regs->orig_eax) { case 0x00: - printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip); + printf("Divide Error (Division by zero)\n"); + dump_regs(regs); while(1); break; case 0x01: - printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip); + printf("Debug Interrupt (Single step)\n"); + dump_regs(regs); break; case 0x02: - printf("NMI Interrupt at %04x:%08x\n", seg, ip); + printf("NMI Interrupt\n"); + dump_regs(regs); break; case 0x03: - printf("Breakpoint at %04x:%08x\n", seg, ip); + printf("Breakpoint\n"); + dump_regs(regs); break; case 0x04: - printf("Overflow at %04x:%08x\n", seg, ip); + printf("Overflow\n"); + dump_regs(regs); while(1); break; case 0x05: - printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip); + printf("BOUND Range Exceeded\n"); + dump_regs(regs); while(1); break; case 0x06: - printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip); + printf("Invalid Opcode (UnDefined Opcode)\n"); + dump_regs(regs); while(1); break; case 0x07: - printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip); + printf("Device Not Available (No Math Coprocessor)\n"); + dump_regs(regs); while(1); break; case 0x08: - printf("Double fault at %04x:%08x\n", seg, ip); + printf("Double fault\n"); + dump_regs(regs); while(1); break; case 0x09: - printf("Co-processor segment overrun at %04x:%08x\n", seg, ip); + printf("Co-processor segment overrun\n"); + dump_regs(regs); while(1); break; case 0x0a: - printf("Invalid TSS at %04x:%08x\n", seg, ip); + printf("Invalid TSS\n"); + dump_regs(regs); break; case 0x0b: - printf("Segment Not Present at %04x:%08x\n", seg, ip); + printf("Segment Not Present\n"); + dump_regs(regs); while(1); break; case 0x0c: - printf("Stack Segment Fault at %04x:%08x\n", seg, ip); + printf("Stack Segment Fault\n"); + dump_regs(regs); while(1); break; case 0x0d: - printf("General Protection at %04x:%08x\n", seg, ip); + printf("General Protection\n"); + dump_regs(regs); break; case 0x0e: - printf("Page fault at %04x:%08x\n", seg, ip); + printf("Page fault\n"); + dump_regs(regs); while(1); break; case 0x0f: - printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip); + printf("Floating-Point Error (Math Fault)\n"); + dump_regs(regs); break; case 0x10: - printf("Alignment check at %04x:%08x\n", seg, ip); + printf("Alignment check\n"); + dump_regs(regs); break; case 0x11: - printf("Machine Check at %04x:%08x\n", seg, ip); + printf("Machine Check\n"); + dump_regs(regs); break; case 0x12: - printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip); + printf("SIMD Floating-Point Exception\n"); + dump_regs(regs); break; case 0x13: case 0x14: @@ -212,12 +334,13 @@ __isr__ irq_llsr(int ip, int seg, int irq) case 0x1d: case 0x1e: case 0x1f: - printf("Reserved Exception %d at %04x:%08x\n", irq, seg, ip); + printf("Reserved Exception\n"); + dump_regs(regs); break; default: /* Hardware or User IRQ */ - do_irq(irq); + do_irq(regs->orig_eax); } } @@ -226,22 +349,45 @@ __isr__ irq_llsr(int ip, int seg, int irq) * fully relocatable code. * - The call to irq_llsr will be a relative jump * - The IRQ entries will be guaranteed to be in order - * It's a bit annoying that we need to waste 3 bytes per interrupt entry - * (total of 768 code bytes), but we MUST create a Stack Frame and this is - * the easiest way I could do it. Maybe it can be made better later. + * Interrupt entries are now very small (a push and a jump) but they are + * now slower (all registers pushed on stack which provides complete + * crash dumps in the low level handlers */ asm(".globl irq_common_entry\n" \ ".hidden irq_common_entry\n" \ ".type irq_common_entry, @function\n" \ "irq_common_entry:\n" \ - "pushl $0\n" \ - "pushl $0\n" \ + "cld\n" \ + "pushl %gs\n" \ + "pushl %fs\n" \ + "pushl %es\n" \ + "pushl %ds\n" \ + "pushl %eax\n" \ + "pushl %ebp\n" \ + "pushl %edi\n" \ + "pushl %esi\n" \ + "pushl %edx\n" \ + "pushl %ecx\n" \ + "pushl %ebx\n" \ + "mov %esp, %eax\n" \ + "pushl %ebp\n" \ + "movl %esp,%ebp\n" \ + "pushl %eax\n" \ "call irq_llsr\n" \ "popl %eax\n" \ - "popl %eax\n" \ - "popl %eax\n" \ - "popa\n" \ "leave\n"\ + "popl %ebx\n" \ + "popl %ecx\n" \ + "popl %edx\n" \ + "popl %esi\n" \ + "popl %edi\n" \ + "popl %ebp\n" \ + "popl %eax\n" \ + "popl %ds\n" \ + "popl %es\n" \ + "popl %fs\n" \ + "popl %gs\n" \ + "add $4, %esp\n" \ "iret\n" \ DECLARE_INTERRUPT(0) \ DECLARE_INTERRUPT(1) \ diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 4b566a7..519bfd8 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -44,24 +44,24 @@ void init_sc520(void) /* Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference */ - sc520_mmcr->uart1ctl = 0x07; - sc520_mmcr->uart2ctl = 0x07; + writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x07, &sc520_mmcr->uart2ctl); /* first set the timer pin mapping */ - sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */ + writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ /* enable PCI bus arbitrer */ - sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */ + writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */ - sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */ - sc520_mmcr->hbctl = 0x04; /* enable posted-writes */ + writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */ + writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */ if (CONFIG_SYS_SC520_HIGH_SPEED) { - sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */ + writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */ gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); } else { - sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */ + writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */ printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; } @@ -74,7 +74,7 @@ void init_sc520(void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - sc520_mmcr->dbctl = 0x11; + writeb(0x11, &sc520_mmcr->dbctl); /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -88,6 +88,7 @@ unsigned long init_sc520_dram(void) u32 dram_present=0; u32 dram_ctrl; + #ifdef CONFIG_SYS_SDRAM_DRCTMCTL /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, @@ -97,7 +98,8 @@ unsigned long init_sc520_dram(void) * simply dictates it. */ #else - int val; + u8 tmp; + u8 val; int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; @@ -116,9 +118,10 @@ unsigned long init_sc520_dram(void) val = 3; /* 62.4us */ } - sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4); + tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4); + writeb(tmp, &sc520_mmcr->drcctl); - val = sc520_mmcr->drctmctl & 0xf0; + val = readb(&sc520_mmcr->drctmctl) & 0xf0; if (cas_precharge_delay==3) { val |= 0x04; /* 3T */ @@ -133,12 +136,12 @@ unsigned long init_sc520_dram(void) } else { val |= 1; } - sc520_mmcr->drctmctl = val; + writeb(val, &c520_mmcr->drctmctl); #endif /* We read-back the configuration of the dram * controller that the assembly code wrote */ - dram_ctrl = sc520_mmcr->drcbendadr; + dram_ctrl = readl(&sc520_mmcr->drcbendadr); bd->bi_dram[0].start = 0; if (dram_ctrl & 0x80) { @@ -191,7 +194,7 @@ void reset_cpu(ulong addr) { printf("Resetting using SC520 MMCR\n"); /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - sc520_mmcr->rescfg = 0x01; + writeb(0x01, &sc520_mmcr->rescfg); /* NOTREACHED */ } diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S index 2042d9b..fff56c0 100644 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ b/arch/i386/cpu/sc520/sc520_asm.S @@ -25,48 +25,85 @@ * copyright is included below */ -/* - * ============================================================================= - * - * Copyright 1999 Advanced Micro Devices, Inc. - * - * This software is the property of Advanced Micro Devices, Inc (AMD) which - * specifically grants the user the right to modify, use and distribute this - * software provided this COPYRIGHT NOTICE is not removed or altered. All - * other rights are reserved by AMD. - * - * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY - * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF - * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. - * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS - * INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY - * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR - * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE - * LIMITATION MAY NOT APPLY TO YOU. - * - * AMD does not assume any responsibility for any errors that may appear in - * the Materials nor any responsibility to support or update the Materials. - * AMD retains the right to make changes to its test specifications at any - * time, without notice. - * - * So that all may benefit from your experience, please report any problems - * or suggestions about this software back to AMD. Please include your name, - * company, telephone number, AMD product requiring support and question or - * problem encountered. - * - * Advanced Micro Devices, Inc. Worldwide support and contact - * Embedded Processor Division information available at: - * Systems Engineering epd.support@amd.com - * 5204 E. Ben White Blvd. -or- - * Austin, TX 78741 http://www.amd.com/html/support/techsup.html - * ============================================================================ +/* TITLE SIZER - Aspen DRAM Sizing Routine. + * ============================================================================= + * + * Copyright 1999 Advanced Micro Devices, Inc. + * You may redistribute this program and/or modify this program under the terms + * of the GNU General Public License as published by the Free Software Foundation; + * either version 2 of the License, or (at your option) any later version. + * + * This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED + * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY + * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF + * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. + * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY + * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR + * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE + * LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors that may appear in + * the Materials nor any responsibility to support or update the Materials. + * AMD retains the right to make changes to its test specifications at any + * time, without notice. + * ============================================================================== */ - -/******************************************************************************* - * AUTHOR : Buddy Fey - Original. +/* + ****************************************************************************** + * + * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm + * + * + * + * FUNCTIONS : sizemem() - jumped to, not called. To be executed after + * reset to determine the size of the SDRAM DIMMs. Initializes + * the memory subsystem. + * + * + * AUTHOR : Buddy Fey - Original. + * + * + * DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor. + * NOTE: This is a small memory model version + * + * + * INPUTS : BP contains return address offset + * CACHE is assumed to be disabled. + * The FS segment limit has already been set to big real mode + * (full 32-bit addressing capability) + * + * + * OUTPUTS : None + * + * + * REG USE : ax,bx,cx,dx,di,si,bp, fs + * + * + * REVISION : See PVCS info below + * + * + * TEST PLAN CROSS REFERENCE: + * + * + * $Workfile: $ + * $Revision: 1.2 $ + * $Date: 1999/09/22 12:49:33 $ + * $Author: chipf $ + * $Log: sizer.asm $ + * Revision 1.2 1999/09/22 12:49:33 chipf + * Add legal header + * ******************************************************************************* */ @@ -463,7 +500,7 @@ emptybank: /* just have your hardware desinger _GIVE_ you what you need here! */ movl $DRCTMCTL, %edi movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al - movb (%edi), %al + movb %al, (%edi) #else #if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) /* set the CAS latency now since it is hard to do @@ -498,48 +535,21 @@ bad_ram: dram_done: - /* readback DRCBENDADR and return the number - * of available ram bytes in %eax */ - - movl $DRCBENDADR, %edi /* DRAM ending address register */ - - movl (%edi), %eax - movl %eax, %ecx - andl $0x80000000, %ecx - jz bank2 - andl $0x7f000000, %eax - shrl $2, %eax - movl %eax, %ebx - -bank2: movl (%edi), %eax - movl %eax, %ecx - andl $0x00800000, %ecx - jz bank1 - andl $0x007f0000, %eax - shll $6, %eax - movl %eax, %ebx - -bank1: movl (%edi), %eax - movl %eax, %ecx - andl $0x00008000, %ecx - jz bank0 - andl $0x00007f00, %eax - shll $14, %eax - movl %eax, %ebx - -bank0: movl (%edi), %eax - movl %eax, %ecx - andl $0x00000080, %ecx - jz done - andl $0x0000007f, %eax - shll $22, %eax - movl %eax, %ebx +#if CONFIG_SYS_SDRAM_ECC_ENABLE + /* + * We are in the middle of an existing 'call' - Need to store the + * existing return address before making another 'call' + */ + movl %ebp, %ebx + /* Get the memory size */ + movl $init_ecc, %ebp + jmpl get_mem_size -done: - movl %ebx, %eax +init_ecc: + /* Restore the orignal return address */ + movl %ebx, %ebp -#if CONFIG_SYS_SDRAM_ECC_ENABLE /* A nominal memory test: just a byte at each address line */ movl %eax, %ecx shrl $0x1, %ecx @@ -576,6 +586,50 @@ set_ecc: mov $0x05, %al movb %al, (%edi) #endif + out: + jmp *%ebp + +/* + * Read and decode the sc520 DRCBENDADR MMCR and return the number of + * available ram bytes in %eax + */ +.globl get_mem_size +get_mem_size: + movl $DRCBENDADR, %edi /* DRAM ending address register */ + +bank0: movl (%edi), %eax + movl %eax, %ecx + andl $0x00000080, %ecx + jz bank1 + andl $0x0000007f, %eax + shll $22, %eax + movl %eax, %ebx + +bank1: movl (%edi), %eax + movl %eax, %ecx + andl $0x00008000, %ecx + jz bank2 + andl $0x00007f00, %eax + shll $14, %eax + movl %eax, %ebx + +bank2: movl (%edi), %eax + movl %eax, %ecx + andl $0x00800000, %ecx + jz bank3 + andl $0x007f0000, %eax + shll $6, %eax + movl %eax, %ebx + +bank3: movl (%edi), %eax + movl %eax, %ecx + andl $0x80000000, %ecx + jz done + andl $0x7f000000, %eax + shrl $2, %eax + movl %eax, %ebx + +done: movl %ebx, %eax jmp *%ebp diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c index f446c6d..b917734 100644 --- a/arch/i386/cpu/sc520/sc520_pci.c +++ b/arch/i386/cpu/sc520/sc520_pci.c @@ -25,7 +25,9 @@ #include <common.h> #include <pci.h> +#include <asm/io.h> #include <asm/pci.h> +#include <asm/ic/pci.h> #include <asm/ic/sc520.h> static struct { @@ -63,6 +65,8 @@ int sc520_pci_ints[15] = { int pci_sc520_set_irq(int pci_pin, int irq) { int i; + u8 tmpb; + u16 tmpw; # if 1 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); @@ -80,31 +84,34 @@ int pci_sc520_set_irq(int pci_pin, int irq) /* PCI interrupt mapping (A through D)*/ for (i=0; i<=3 ;i++) { - if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority) - sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED; + if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority) + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]); } /* GP IRQ interrupt mapping */ for (i=0; i<=10 ;i++) { - if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority) - sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED; + if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority) + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]); } /* Set the trigger to level */ - sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] = - sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit; + tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]); + tmpb |= sc520_irq[irq].level_bit; + writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]); if (pci_pin < 4) { /* PCI INTA-INTD */ /* route the interrupt */ - sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority; + writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]); } else { /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority; + writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]); /* also set the polarity in this case */ - sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4)); + tmpw = readw(&sc520_mmcr->intpinpol); + tmpw |= (1 << (pci_pin-4)); + writew(tmpw, &sc520_mmcr->intpinpol); } /* register the pin */ @@ -118,43 +125,7 @@ void pci_sc520_init(struct pci_controller *hose) { hose->first_busno = 0; hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - SC520_PCI_MEMORY_BUS, - SC520_PCI_MEMORY_PHYS, - SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - SC520_PCI_MEM_BUS, - SC520_PCI_MEM_PHYS, - SC520_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - SC520_ISA_MEM_BUS, - SC520_ISA_MEM_PHYS, - SC520_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - SC520_PCI_IO_BUS, - SC520_PCI_IO_PHYS, - SC520_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - SC520_ISA_IO_BUS, - SC520_ISA_IO_PHYS, - SC520_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; + hose->region_count = pci_set_regions(hose); pci_setup_type1(hose, SC520_REG_ADDR, diff --git a/arch/i386/cpu/sc520/sc520_ssi.c b/arch/i386/cpu/sc520/sc520_ssi.c index 8dbe17a..6e5e346 100644 --- a/arch/i386/cpu/sc520/sc520_ssi.c +++ b/arch/i386/cpu/sc520/sc520_ssi.c @@ -24,6 +24,7 @@ /* stuff specific for the sc520, but independent of implementation */ #include <common.h> +#include <asm/io.h> #include <asm/ic/ssi.h> #include <asm/ic/sc520.h> @@ -61,34 +62,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) temp |= PHS_INV_ENB; } - sc520_mmcr->ssictl = temp; + writeb(temp, &sc520_mmcr->ssictl); return 0; } u8 ssi_txrx_byte(u8 data) { - sc520_mmcr->ssixmit = data; - while (sc520_mmcr->ssista & SSISTA_BSY); - sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV; - while (sc520_mmcr->ssista & SSISTA_BSY); + writeb(data, &sc520_mmcr->ssixmit); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); - return sc520_mmcr->ssircv; + return readb(&sc520_mmcr->ssircv); } void ssi_tx_byte(u8 data) { - sc520_mmcr->ssixmit = data; - while (sc520_mmcr->ssista & SSISTA_BSY); - sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT; + writeb(data, &sc520_mmcr->ssixmit); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd); } u8 ssi_rx_byte(void) { - while (sc520_mmcr->ssista & SSISTA_BSY); - sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV; - while (sc520_mmcr->ssista & SSISTA_BSY); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); + writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd); + while (readb(&sc520_mmcr->ssista) & SSISTA_BSY); - return sc520_mmcr->ssircv; + return readb(&sc520_mmcr->ssircv); } diff --git a/arch/i386/cpu/sc520/sc520_timer.c b/arch/i386/cpu/sc520/sc520_timer.c index 93b5b55..d5617e9 100644 --- a/arch/i386/cpu/sc520/sc520_timer.c +++ b/arch/i386/cpu/sc520/sc520_timer.c @@ -24,13 +24,14 @@ /* stuff specific for the sc520, but independent of implementation */ #include <common.h> +#include <asm/io.h> #include <asm/interrupt.h> #include <asm/ic/sc520.h> void sc520_timer_isr(void) { /* Ack the GP Timer Interrupt */ - sc520_mmcr->gptmrsta = 0x02; + writeb(0x02, &sc520_mmcr->gptmrsta); } int timer_init(void) @@ -42,43 +43,47 @@ int timer_init(void) irq_install_handler (0, timer_isr, NULL); /* Map GP Timer 1 to Master PIC IR0 */ - sc520_mmcr->gp_tmr_int_map[1] = 0x01; + writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]); /* Disable GP Timers 1 & 2 - Allow configuration writes */ - sc520_mmcr->gptmr1ctl = 0x4000; - sc520_mmcr->gptmr2ctl = 0x4000; + writew(0x4000, &sc520_mmcr->gptmr1ctl); + writew(0x4000, &sc520_mmcr->gptmr2ctl); /* Reset GP Timers 1 & 2 */ - sc520_mmcr->gptmr1cnt = 0x0000; - sc520_mmcr->gptmr2cnt = 0x0000; + writew(0x0000, &sc520_mmcr->gptmr1cnt); + writew(0x0000, &sc520_mmcr->gptmr2cnt); /* Setup GP Timer 2 as a 100kHz (10us) prescaler */ - sc520_mmcr->gptmr2maxcmpa = 83; - sc520_mmcr->gptmr2ctl = 0xc001; + writew(83, &sc520_mmcr->gptmr2maxcmpa); + writew(0xc001, &sc520_mmcr->gptmr2ctl); /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ - sc520_mmcr->gptmr1maxcmpa = 100; - sc520_mmcr->gptmr1ctl = 0xe009; + writew(100, &sc520_mmcr->gptmr1maxcmpa); + writew(0xe009, &sc520_mmcr->gptmr1ctl); unmask_irq (0); /* Clear the GP Timer 1 status register to get the show rolling*/ - sc520_mmcr->gptmrsta = 0x02; + writeb(0x02, &sc520_mmcr->gptmrsta); return 0; } +/* Allow boards to override udelay implementation */ void __udelay(unsigned long usec) + __attribute__((weak, alias("sc520_udelay"))); + +void sc520_udelay(unsigned long usec) { int m = 0; long u; long temp; - temp = sc520_mmcr->swtmrmilli; - temp = sc520_mmcr->swtmrmicro; + temp = readw(&sc520_mmcr->swtmrmilli); + temp = readw(&sc520_mmcr->swtmrmicro); do { - m += sc520_mmcr->swtmrmilli; - u = sc520_mmcr->swtmrmicro + (m * 1000); + m += readw(&sc520_mmcr->swtmrmilli); + u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000); } while (u < usec); } diff --git a/arch/i386/cpu/serial.c b/arch/i386/cpu/serial.c deleted file mode 100644 index e7025a3..0000000 --- a/arch/i386/cpu/serial.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ */ - -/* - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - */ -/*------------------------------------------------------------------------------- */ - -#include <common.h> -#include <watchdog.h> -#include <asm/io.h> -#include <asm/ibmpc.h> - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include <malloc.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; - int cts; -} serial_buffer_t; - -volatile serial_buffer_t buf_info; -static int serial_buffer_active=0; -#endif - - -static int serial_div(int baudrate) -{ - - switch (baudrate) { - case 1200: - return 96; - case 9600: - return 12; - case 19200: - return 6; - case 38400: - return 3; - case 57600: - return 2; - case 115200: - return 1; - } - - return 12; -} - - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -int serial_init(void) -{ - volatile char val; - int bdiv = serial_div(gd->baudrate); - - outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */ - outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ - outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ - outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */ - outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */ - val = inb(UART0_BASE + UART_LSR); /* clear line status */ - val = inb(UART0_BASE + UART_RBR); /* read receive buffer */ - outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */ - outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */ - - return 0; -} - - -void serial_setbrg(void) -{ - unsigned short bdiv; - - bdiv = serial_div(gd->baudrate); - - outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */ - outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ - outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ -} - - -void serial_putc(const char c) -{ - int i; - - if (c == '\n') - serial_putc ('\r'); - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { - if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) { - break; - } - udelay(100); - } - outb(c, UART0_BASE + UART_THR); /* put character out */ -} - - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - - -int serial_getc(void) -{ - unsigned char status = 0; - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - if (serial_buffer_active) { - return serial_buffered_getc(); - } -#endif - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ - status = inb(UART0_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); - } - } - return (0x000000ff & (int) inb (UART0_BASE)); -} - - -int serial_tstc(void) -{ - unsigned char status; - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - if (serial_buffer_active) { - return serial_buffered_tstc(); - } -#endif - - status = inb(UART0_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); - } - return 0; -} - - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr(void *arg) -{ - int space; - int c; - int rx_put = buf_info.rx_put; - - if (buf_info.rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get); - } else { - space = buf_info.rx_get - rx_put; - } - - while (inb(UART0_BASE + UART_LSR) & 1) { - c = inb(UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - - if (rx_put == buf_info.rx_get) { - buf_info.rx_get++; - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { - buf_info.rx_get = 0; - } - } - - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { - rx_put = 0; - if (0 == buf_info.rx_get) { - buf_info.rx_get = 1; - } - - } - - } - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02), - UART0_BASE + UART_MCR); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init(void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (inb (UART0_BASE + UART_MSR) & 0x10) { - serial_puts ("Check CTS signal present on serial port: OK.\n"); - buf_info.cts = 1; - } else { - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - buf_info.cts = 0; - } - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - /* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */ - outb(0x01, UART0_BASE + UART_IER); - - /* Set DTR and RTS active, enable interrupts */ - outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR); - - /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ - outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR); - - serial_buffer_active = 1; -} - -void serial_buffered_putc (const char c) -{ - int i; - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(inb (UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - if (buf_info.cts) { - for (i=0;i<1000;i++) { - if ((inb (UART0_BASE + UART_MSR) & 0x10)) { - break; - } - } - if (i!=1000) { - buf_info.cts = 0; - } - } else { - if ((inb (UART0_BASE + UART_MSR) & 0x10)) { - buf_info.cts = 1; - } - } - -#endif - serial_putc (c); -} - -void serial_buffered_puts(const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc(void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); -#else - while (rx_get == buf_info.rx_put); -#endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) { - rx_get = 0; - } - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR); - } - - return c; -} - -int serial_buffered_tstc(void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} - -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - - -#if defined(CONFIG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init(void) -{ - volatile char val; - bdiv = serial_div (CONFIG_KGDB_BAUDRATE); - - /* - * Init onboard 16550 UART - */ - outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */ - outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ - outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ - outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */ - outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */ - outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */ - val = inb(UART1_BASE + UART_LSR); /* clear line status */ - val = inb(UART1_BASE + UART_RBR); /* read receive buffer */ - outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */ - outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */ -} - - -void putDebugChar(const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - outb(c, UART1_BASE + UART_THR); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - - -void putDebugStr(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - - -int getDebugChar(void) -{ - unsigned char status = 0; - - while (1) { - status = inb(UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR); - } - } - return (0x000000ff & (int) inb(UART1_BASE)); -} - - -void kgdb_interruptible(int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init(void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar(int c) -{ - serial_putc (c); -} - -void putDebugStr(const char *str) -{ - serial_puts (str); -} - -int getDebugChar(void) -{ - return serial_getc (); -} - -void kgdb_interruptible(int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 25d32e6..7def8de 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -33,7 +33,27 @@ .type _start, @function .globl _i386boot_start _i386boot_start: + /* + * This is the fail safe 32-bit bootstrap entry point. The + * following code is not executed from a cold-reset (actually, a + * lot of it is, but from real-mode after cold reset. It is + * repeated here to put the board into a state as close to cold + * reset as necessary) + */ + cli + cld + + /* Turn of cache (this might require a 486-class CPU) */ + movl %cr0, %eax + orl $0x60000000,%eax + movl %eax, %cr0 + wbinvd + + /* Tell 32-bit code it is being entered from an in-RAM copy */ + movw $0x0000, %bx _start: + /* This is the 32-bit cold-reset entry point */ + movl $0x18,%eax /* Load our segement registes, the * gdt have already been loaded by start16.S */ movw %ax,%fs @@ -42,6 +62,18 @@ _start: movw %ax,%es movw %ax,%ss + /* Clear the interupt vectors */ + lidt blank_idt_ptr + + /* + * Skip low-level board and memory initialization if not starting + * from cold-reset. This allows us to do a fail safe boot-strap + * into a new build of U-Boot from a known-good boot flash + */ + movw $0x0001, %ax + cmpw %ax, %bx + jne mem_init_ret + /* We call a few functions in the board support package * since we have no stack yet we'll have to use %ebp * to store the return address */ @@ -63,6 +95,58 @@ early_board_init_ret: jmp mem_init mem_init_ret: + /* fetch memory size (into %eax) */ + mov $get_mem_size_ret, %ebp + jmp get_mem_size +get_mem_size_ret: + + /* + * We are now in 'Flat Protected Mode' and we know how much memory + * the board has. The (temporary) Global Descriptor Table is not + * in a 'Safe' place (it is either in Flash which can be erased or + * reprogrammed or in a fail-safe boot-strap image which could be + * over-written). + * + * Move the final gdt to a safe place (top of RAM) and load it. + * This is not a trivial excercise - the lgdt instruction does not + * have a register operand (memory only) and we may well be + * running from Flash, so self modifying code will not work here. + * To overcome this, we copy a stub into upper memory along with + * the GDT. + */ + + /* Reduce upper memory limit by (Stub + GDT Pointer + GDT) */ + subl $(end_gdt_setup - start_gdt_setup), %eax + + /* Copy the GDT and Stub */ + movl $start_gdt_setup, %esi + movl %eax, %edi + movl $(end_gdt_setup - start_gdt_setup), %ecx + shrl $2, %ecx + cld + rep movsl + + /* write the lgdt 'parameter' */ + subl $(jmp_instr - start_gdt_setup - 4), %ebp + addl %eax, %ebp + movl $(gdt_ptr - start_gdt_setup), %ebx + addl %eax, %ebx + movl %ebx, (%ebp) + + /* write the gdt address into the pointer */ + movl $(gdt_addr - start_gdt_setup), %ebp + addl %eax, %ebp + movl $(gdt - start_gdt_setup), %ebx + addl %eax, %ebx + movl %ebx, (%ebp) + + /* Save the return address */ + movl $load_gdt_ret, %ebp + + /* Load the new (safe) Global Descriptor Table */ + jmp *%eax + +load_gdt_ret: /* Check we have enough memory for stack */ movl $CONFIG_SYS_STACK_SIZE, %ecx cmpl %ecx, %eax @@ -133,3 +217,56 @@ stack_ok: die: hlt jmp die hlt + +blank_idt_ptr: + .word 0 /* limit */ + .long 0 /* base */ + +.align 4 +start_gdt_setup: + lgdt gdt_ptr +jmp_instr: + jmp *%ebp + +.align 4 +gdt_ptr: + .word 0x30 /* limit (48 bytes = 6 GDT entries) */ +gdt_addr: + .long gdt /* base */ + + /* The GDT table ... + * + * Selector Type + * 0x00 NULL + * 0x08 Unused + * 0x10 32bit code + * 0x18 32bit data/stack + * 0x20 16bit code + * 0x28 16bit data/stack + */ + +.align 4 +gdt: + .word 0, 0, 0, 0 /* NULL */ + .word 0, 0, 0, 0 /* unused */ + + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0 /* base address = 0 */ + .word 0x9B00 /* code read/exec */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0x0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9b00 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ + + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ +end_gdt_setup: diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index 1ebb6bc..3e8b2cc 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -44,11 +44,9 @@ board_init16_ret: movl %eax, %cr0 wbinvd - /* load the descriptor tables */ -o32 cs lidt idt_ptr + /* load the temporary Global Descriptor Table */ o32 cs lgdt gdt_ptr - /* Now, we enter protected mode */ movl %cr0, %eax orl $1,%eax @@ -57,6 +55,8 @@ o32 cs lgdt gdt_ptr /* Flush the prefetch queue */ jmp ff ff: + /* Tell 32-bit code it is being entered from hard-reset */ + movw $0x0001, %bx /* Finally jump to the 32bit initialization code */ movw $code32start, %ax @@ -68,12 +68,13 @@ code32start: .long _start /* offset */ .word 0x10 /* segment */ -idt_ptr: - .word 0 /* limit */ - .long 0 /* base */ - +/* + * The following Global Descriptor Table is just enough to get us into + * 'Flat Protected Mode' - It will be discarded as soon as the final + * GDT is setup in a safe location in RAM + */ gdt_ptr: - .word 0x30 /* limit (48 bytes = 6 GDT entries) */ + .word 0x20 /* limit (32 bytes = 4 GDT entries) */ .long BOOT_SEG + gdt /* base */ /* The GDT table ... @@ -83,8 +84,6 @@ gdt_ptr: * 0x08 Unused * 0x10 32bit code * 0x18 32bit data/stack - * 0x20 16bit code - * 0x28 16bit data/stack */ gdt: @@ -100,13 +99,3 @@ gdt: .word 0x0 /* base address = 0 */ .word 0x9300 /* data read/write */ .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9b00 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ diff --git a/arch/i386/include/asm/bootparam.h b/arch/i386/include/asm/bootparam.h new file mode 100644 index 0000000..1400951 --- /dev/null +++ b/arch/i386/include/asm/bootparam.h @@ -0,0 +1,120 @@ +#ifndef _ASM_X86_BOOTPARAM_H +#define _ASM_X86_BOOTPARAM_H + +#include <linux/types.h> +#include <linux/screen_info.h> +#include <linux/apm_bios.h> +#include <linux/edd.h> +#include <asm/e820.h> +#include <asm/ist.h> +#include <asm/video/edid.h> + +/* setup data types */ +#define SETUP_NONE 0 +#define SETUP_E820_EXT 1 + +/* extensible setup data list node */ +struct setup_data { + __u64 next; + __u32 type; + __u32 len; + __u8 data[0]; +}; + +struct setup_header { + __u8 setup_sects; + __u16 root_flags; + __u32 syssize; + __u16 ram_size; +#define RAMDISK_IMAGE_START_MASK 0x07FF +#define RAMDISK_PROMPT_FLAG 0x8000 +#define RAMDISK_LOAD_FLAG 0x4000 + __u16 vid_mode; + __u16 root_dev; + __u16 boot_flag; + __u16 jump; + __u32 header; + __u16 version; + __u32 realmode_swtch; + __u16 start_sys; + __u16 kernel_version; + __u8 type_of_loader; + __u8 loadflags; +#define LOADED_HIGH (1<<0) +#define QUIET_FLAG (1<<5) +#define KEEP_SEGMENTS (1<<6) +#define CAN_USE_HEAP (1<<7) + __u16 setup_move_size; + __u32 code32_start; + __u32 ramdisk_image; + __u32 ramdisk_size; + __u32 bootsect_kludge; + __u16 heap_end_ptr; + __u8 ext_loader_ver; + __u8 ext_loader_type; + __u32 cmd_line_ptr; + __u32 initrd_addr_max; + __u32 kernel_alignment; + __u8 relocatable_kernel; + __u8 _pad2[3]; + __u32 cmdline_size; + __u32 hardware_subarch; + __u64 hardware_subarch_data; + __u32 payload_offset; + __u32 payload_length; + __u64 setup_data; +} __attribute__((packed)); + +struct sys_desc_table { + __u16 length; + __u8 table[14]; +}; + +struct efi_info { + __u32 efi_loader_signature; + __u32 efi_systab; + __u32 efi_memdesc_size; + __u32 efi_memdesc_version; + __u32 efi_memmap; + __u32 efi_memmap_size; + __u32 efi_systab_hi; + __u32 efi_memmap_hi; +}; + +/* The so-called "zeropage" */ +struct boot_params { + struct screen_info screen_info; /* 0x000 */ + struct apm_bios_info apm_bios_info; /* 0x040 */ + __u8 _pad2[4]; /* 0x054 */ + __u64 tboot_addr; /* 0x058 */ + struct ist_info ist_info; /* 0x060 */ + __u8 _pad3[16]; /* 0x070 */ + __u8 hd0_info[16]; /* obsolete! */ /* 0x080 */ + __u8 hd1_info[16]; /* obsolete! */ /* 0x090 */ + struct sys_desc_table sys_desc_table; /* 0x0a0 */ + __u8 _pad4[144]; /* 0x0b0 */ + struct edid_info edid_info; /* 0x140 */ + struct efi_info efi_info; /* 0x1c0 */ + __u32 alt_mem_k; /* 0x1e0 */ + __u32 scratch; /* Scratch field! */ /* 0x1e4 */ + __u8 e820_entries; /* 0x1e8 */ + __u8 eddbuf_entries; /* 0x1e9 */ + __u8 edd_mbr_sig_buf_entries; /* 0x1ea */ + __u8 _pad6[6]; /* 0x1eb */ + struct setup_header hdr; /* setup header */ /* 0x1f1 */ + __u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)]; + __u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */ + struct e820entry e820_map[E820MAX]; /* 0x2d0 */ + __u8 _pad8[48]; /* 0xcd0 */ + struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */ + __u8 _pad9[276]; /* 0xeec */ +} __attribute__((packed)); + +enum { + X86_SUBARCH_PC = 0, + X86_SUBARCH_LGUEST, + X86_SUBARCH_XEN, + X86_SUBARCH_MRST, + X86_NR_SUBARCHS, +}; +#endif /* _ASM_X86_BOOTPARAM_H */ diff --git a/arch/i386/include/asm/e820.h b/arch/i386/include/asm/e820.h new file mode 100644 index 0000000..d155ce9 --- /dev/null +++ b/arch/i386/include/asm/e820.h @@ -0,0 +1,155 @@ +#ifndef _ASM_X86_E820_H +#define _ASM_X86_E820_H +#define E820MAP 0x2d0 /* our map */ +#define E820MAX 128 /* number of entries in E820MAP */ + +/* + * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the + * constrained space in the zeropage. If we have more nodes than + * that, and if we've booted off EFI firmware, then the EFI tables + * passed us from the EFI firmware can list more nodes. Size our + * internal memory map tables to have room for these additional + * nodes, based on up to three entries per node for which the + * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT), + * plus E820MAX, allowing space for the possible duplicate E820 + * entries that might need room in the same arrays, prior to the + * call to sanitize_e820_map() to remove duplicates. The allowance + * of three memory map entries per node is "enough" entries for + * the initial hardware platform motivating this mechanism to make + * use of additional EFI map entries. Future platforms may want + * to allow more than three entries per node or otherwise refine + * this size. + */ + +/* + * Odd: 'make headers_check' complains about numa.h if I try + * to collapse the next two #ifdef lines to a single line: + * #if defined(__KERNEL__) && defined(CONFIG_EFI) + */ +#ifdef __KERNEL__ +#ifdef CONFIG_EFI +#include <linux/numa.h> +#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES) +#else /* ! CONFIG_EFI */ +#define E820_X_MAX E820MAX +#endif +#else /* ! __KERNEL__ */ +#define E820_X_MAX E820MAX +#endif + +#define E820NR 0x1e8 /* # entries in E820MAP */ + +#define E820_RAM 1 +#define E820_RESERVED 2 +#define E820_ACPI 3 +#define E820_NVS 4 +#define E820_UNUSABLE 5 + +/* reserved RAM used by kernel itself */ +#define E820_RESERVED_KERN 128 + +#ifndef __ASSEMBLY__ +#include <linux/types.h> +struct e820entry { + __u64 addr; /* start of memory segment */ + __u64 size; /* size of memory segment */ + __u32 type; /* type of memory segment */ +} __attribute__((packed)); + +struct e820map { + __u32 nr_map; + struct e820entry map[E820_X_MAX]; +}; + +#define ISA_START_ADDRESS 0xa0000 +#define ISA_END_ADDRESS 0x100000 + +#define BIOS_BEGIN 0x000a0000 +#define BIOS_END 0x00100000 + +#ifdef __KERNEL__ +/* see comment in arch/x86/kernel/e820.c */ +extern struct e820map e820; +extern struct e820map e820_saved; + +extern unsigned long pci_mem_start; +extern int e820_any_mapped(u64 start, u64 end, unsigned type); +extern int e820_all_mapped(u64 start, u64 end, unsigned type); +extern void e820_add_region(u64 start, u64 size, int type); +extern void e820_print_map(char *who); +extern int +sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, u32 *pnr_map); +extern u64 e820_update_range(u64 start, u64 size, unsigned old_type, + unsigned new_type); +extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type, + int checktype); +extern void update_e820(void); +extern void e820_setup_gap(void); +extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize, + unsigned long start_addr, unsigned long long end_addr); +struct setup_data; +extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data); + +#if defined(CONFIG_X86_64) || \ + (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION)) +extern void e820_mark_nosave_regions(unsigned long limit_pfn); +#else +static inline void e820_mark_nosave_regions(unsigned long limit_pfn) +{ +} +#endif + +#ifdef CONFIG_MEMTEST +extern void early_memtest(unsigned long start, unsigned long end); +#else +static inline void early_memtest(unsigned long start, unsigned long end) +{ +} +#endif + +extern unsigned long end_user_pfn; + +extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align); +extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align); +extern void reserve_early(u64 start, u64 end, char *name); +extern void reserve_early_overlap_ok(u64 start, u64 end, char *name); +extern void free_early(u64 start, u64 end); +extern void early_res_to_bootmem(u64 start, u64 end); +extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align); + +extern unsigned long e820_end_of_ram_pfn(void); +extern unsigned long e820_end_of_low_ram_pfn(void); +extern int e820_find_active_region(const struct e820entry *ei, + unsigned long start_pfn, + unsigned long last_pfn, + unsigned long *ei_startpfn, + unsigned long *ei_endpfn); +extern void e820_register_active_regions(int nid, unsigned long start_pfn, + unsigned long end_pfn); +extern u64 e820_hole_size(u64 start, u64 end); +extern void finish_e820_parsing(void); +extern void e820_reserve_resources(void); +extern void e820_reserve_resources_late(void); +extern void setup_memory_map(void); +extern char *default_machine_specific_memory_setup(void); + +/* + * Returns true iff the specified range [s,e) is completely contained inside + * the ISA region. + */ +/* +static inline bool is_ISA_range(u64 s, u64 e) +{ + return s >= ISA_START_ADDRESS && e <= ISA_END_ADDRESS; +} +*/ +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#ifdef __KERNEL__ +/* #include <linux/ioport.h> */ + +#define HIGH_MEMORY (1024*1024) +#endif /* __KERNEL__ */ + +#endif /* _ASM_X86_E820_H */ diff --git a/arch/i386/include/asm/ic/pci.h b/arch/i386/include/asm/ic/pci.h index bcccdbe..2e4376b 100644 --- a/arch/i386/include/asm/ic/pci.h +++ b/arch/i386/include/asm/ic/pci.h @@ -24,6 +24,35 @@ #ifndef _ASM_IC_SC520_PCI_H_ #define _ASM_IC_SC520_PCI_H_ 1 +/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ +#define SC520_REG_ADDR 0x00000cf8 +#define SC520_REG_DATA 0x00000cfc + +#define SC520_ISA_MEM_PHYS 0x00000000 +#define SC520_ISA_MEM_BUS 0x00000000 +#define SC520_ISA_MEM_SIZE 0x01000000 + +#define SC520_ISA_IO_PHYS 0x00000000 +#define SC520_ISA_IO_BUS 0x00000000 +#define SC520_ISA_IO_SIZE 0x00001000 + +/* PCI I/O space from 0x1000 to 0xdfff + * (make 0xe000-0xfdff available for stuff like PCCard boot) */ +#define SC520_PCI_IO_PHYS 0x00001000 +#define SC520_PCI_IO_BUS 0x00001000 +#define SC520_PCI_IO_SIZE 0x0000d000 + +/* system memory from 0x00000000 to 0x0fffffff */ +#define SC520_PCI_MEMORY_PHYS 0x00000000 +#define SC520_PCI_MEMORY_BUS 0x00000000 +#define SC520_PCI_MEMORY_SIZE 0x10000000 + +/* PCI bus memory from 0x10000000 to 0x26ffffff + * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ +#define SC520_PCI_MEM_PHYS 0x10000000 +#define SC520_PCI_MEM_BUS 0x10000000 +#define SC520_PCI_MEM_SIZE 0x17000000 + /* pin number used for PCI interrupt mappings */ #define SC520_PCI_INTA 0 #define SC520_PCI_INTB 1 @@ -44,6 +73,7 @@ extern int sc520_pci_ints[]; void pci_sc520_init(struct pci_controller *hose); +int pci_set_regions(struct pci_controller *hose); int pci_sc520_set_irq(int pci_pin, int irq); #endif diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h index 57c9904..053d9c6 100644 --- a/arch/i386/include/asm/ic/sc520.h +++ b/arch/i386/include/asm/ic/sc520.h @@ -28,6 +28,7 @@ void init_sc520(void); unsigned long init_sc520_dram(void); +void sc520_udelay(unsigned long usec); /* Memory mapped configuration registers */ typedef struct sc520_mmcr { @@ -292,35 +293,6 @@ extern volatile sc520_mmcr_t *sc520_mmcr; #define UART2_DIS 0x02 /* UART2 Disable */ #define UART1_DIS 0x01 /* UART1 Disable */ -/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ -#define SC520_REG_ADDR 0x00000cf8 -#define SC520_REG_DATA 0x00000cfc - -#define SC520_ISA_MEM_PHYS 0x00000000 -#define SC520_ISA_MEM_BUS 0x00000000 -#define SC520_ISA_MEM_SIZE 0x01000000 - -#define SC520_ISA_IO_PHYS 0x00000000 -#define SC520_ISA_IO_BUS 0x00000000 -#define SC520_ISA_IO_SIZE 0x00001000 - -/* PCI I/O space from 0x1000 to 0xdfff - * (make 0xe000-0xfdff available for stuff like PCCard boot) */ -#define SC520_PCI_IO_PHYS 0x00001000 -#define SC520_PCI_IO_BUS 0x00001000 -#define SC520_PCI_IO_SIZE 0x0000d000 - -/* system memory from 0x00000000 to 0x0fffffff */ -#define SC520_PCI_MEMORY_PHYS 0x00000000 -#define SC520_PCI_MEMORY_BUS 0x00000000 -#define SC520_PCI_MEMORY_SIZE 0x10000000 - -/* PCI bus memory from 0x10000000 to 0x26ffffff - * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ -#define SC520_PCI_MEM_PHYS 0x10000000 -#define SC520_PCI_MEM_BUS 0x10000000 -#define SC520_PCI_MEM_SIZE 0x17000000 - /* 0x28000000 - 0x3fffffff is used by the flash banks */ /* 0x40000000 - 0xffffffff is not adressable by the SC520 */ diff --git a/arch/i386/include/asm/ioctl.h b/arch/i386/include/asm/ioctl.h new file mode 100644 index 0000000..b279fe0 --- /dev/null +++ b/arch/i386/include/asm/ioctl.h @@ -0,0 +1 @@ +#include <asm-generic/ioctl.h> diff --git a/arch/i386/include/asm/ist.h b/arch/i386/include/asm/ist.h new file mode 100644 index 0000000..7e5dff1 --- /dev/null +++ b/arch/i386/include/asm/ist.h @@ -0,0 +1,34 @@ +#ifndef _ASM_X86_IST_H +#define _ASM_X86_IST_H + +/* + * Include file for the interface to IST BIOS + * Copyright 2002 Andy Grover <andrew.grover@intel.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2, or (at your option) any + * later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + + +#include <linux/types.h> + +struct ist_info { + __u32 signature; + __u32 command; + __u32 event; + __u32 perf_level; +}; + +#ifdef __KERNEL__ + +extern struct ist_info ist_info; + +#endif /* __KERNEL__ */ +#endif /* _ASM_X86_IST_H */ diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index 521fd35..ce097a3 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -43,6 +43,8 @@ int cpu_init_interrupts(void); int board_init(void); int dram_init(void); +void setup_pcat_compatibility(void); + void isa_unmap_rom(u32 addr); u32 isa_map_rom(u32 bus_addr, int size); diff --git a/arch/i386/include/asm/unaligned.h b/arch/i386/include/asm/unaligned.h new file mode 100644 index 0000000..6cecbbb --- /dev/null +++ b/arch/i386/include/asm/unaligned.h @@ -0,0 +1 @@ +#include <asm-generic/unaligned.h> diff --git a/arch/i386/include/asm/video/edid.h b/arch/i386/include/asm/video/edid.h new file mode 100644 index 0000000..928c342 --- /dev/null +++ b/arch/i386/include/asm/video/edid.h @@ -0,0 +1,16 @@ +#ifndef __linux_video_edid_h__ +#define __linux_video_edid_h__ + +#if !defined(__KERNEL__) || defined(CONFIG_X86) + +struct edid_info { + unsigned char dummy[128]; +}; + +#ifdef __KERNEL__ +extern struct edid_info edid_info; +#endif /* __KERNEL__ */ + +#endif + +#endif /* __linux_video_edid_h__ */ diff --git a/arch/i386/lib/bios_setup.c b/arch/i386/lib/bios_setup.c index 6491e52..a92b77e 100644 --- a/arch/i386/lib/bios_setup.c +++ b/arch/i386/lib/bios_setup.c @@ -141,7 +141,7 @@ static void setvector(int vector, u16 segment, void *handler) int bios_setup(void) { - ulong i386boot_bios = (ulong)&_i386boot_bios; + ulong i386boot_bios = (ulong)&_i386boot_bios + gd->reloc_off; ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; static int done=0; diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index f3b6348..3f849f6 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -37,6 +37,7 @@ #include <malloc.h> #include <net.h> #include <ide.h> +#include <serial.h> #include <asm/u-boot-i386.h> #include <elf.h> @@ -52,7 +53,9 @@ extern ulong _i386boot_rel_dyn_start; extern ulong _i386boot_rel_dyn_end; extern ulong _i386boot_bss_start; extern ulong _i386boot_bss_size; -void ram_bootstrap (void *); + +void ram_bootstrap (void *, ulong); + const char version_string[] = U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; @@ -147,7 +150,6 @@ static void display_flash_config (ulong size) typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = { - serial_init, cpu_init_r, /* basic cpu dependent setup */ board_early_init_r, /* basic board dependent setup */ dram_init, /* configure available RAM banks */ @@ -162,6 +164,7 @@ init_fnc_t *init_sequence[] = { NULL, }; +static gd_t gd_data; gd_t *gd; /* @@ -174,21 +177,18 @@ void board_init_f (ulong stack_limit) Elf32_Rel *rel_dyn_start = (Elf32_Rel *)&_i386boot_rel_dyn_start; Elf32_Rel *rel_dyn_end = (Elf32_Rel *)&_i386boot_rel_dyn_end; void *bss_start = &_i386boot_bss_start; - void *bss_size = &_i386boot_bss_size; + ulong bss_size = (ulong)&_i386boot_bss_size; - size_t uboot_size; - void *ram_start; + ulong uboot_size; + void *dest_addr; ulong rel_offset; Elf32_Rel *re; - void (*start_func)(void *); - - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); + void (*start_func)(void *, ulong); - uboot_size = (size_t)u_boot_cmd_end - (size_t)text_start; - ram_start = (void *)stack_limit - (uboot_size + (ulong)bss_size); - rel_offset = text_start - ram_start; + uboot_size = (ulong)u_boot_cmd_end - (ulong)text_start; + dest_addr = (void *)stack_limit - (uboot_size + (ulong)bss_size); + rel_offset = text_start - dest_addr; start_func = ram_bootstrap - rel_offset; /* First stage CPU initialization */ @@ -200,10 +200,10 @@ void board_init_f (ulong stack_limit) hang(); /* Copy U-Boot into RAM */ - memcpy(ram_start, text_start, (size_t)uboot_size); + memcpy(dest_addr, text_start, uboot_size); /* Clear BSS */ - memset(bss_start - rel_offset, 0, (size_t)bss_size); + memset(bss_start - rel_offset, 0, bss_size); /* Perform relocation adjustments */ for (re = rel_dyn_start; re < rel_dyn_end; re++) @@ -213,27 +213,39 @@ void board_init_f (ulong stack_limit) *(ulong *)(re->r_offset - rel_offset) -= (Elf32_Addr)rel_offset; } - start_func(ram_start); - - /* NOTREACHED - relocate_code() does not return */ + /* Enter the relocated U-Boot! */ + start_func(dest_addr, rel_offset); + /* NOTREACHED - board_init_f() does not return */ while(1); } /* - * All attempts to jump straight from board_init_f() to board_init_r() - * have failed, hence this special 'bootstrap' function. + * We cannot initialize gd_data in board_init_f() because we would be + * attempting to write to flash (I have even tried using manual relocation + * adjustments on pointers but it just won't work) and board_init_r() does + * not have enough arguments to allow us to pass the relocation offset + * straight up. This bootstrap function (which runs in RAM) is used to + * setup gd_data in order to pass the relocation offset to the rest of + * U-Boot. + * + * TODO: The compiler optimization barrier is intended to stop GCC from + * optimizing this function into board_init_f(). It seems to work without + * it, but I've left it in to be sure. I think also that the barrier in + * board_init_r() is no longer needed, but left it in 'just in case' */ -void ram_bootstrap (void *ram_start) +void ram_bootstrap (void *dest_addr, ulong rel_offset) { - static gd_t gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); - board_init_r(&gd_data, (ulong)ram_start); + /* tell others: relocation done */ + gd_data.reloc_off = rel_offset; + gd_data.flags |= GD_FLG_RELOC; + + board_init_r(&gd_data, (ulong)dest_addr); } -void board_init_r(gd_t *id, ulong ram_start) +void board_init_r(gd_t *id, ulong dest_addr) { char *s; int i; @@ -247,16 +259,13 @@ void board_init_r(gd_t *id, ulong ram_start) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); - memset (gd, 0, sizeof (gd_t)); gd->bd = &bd_data; memset (gd->bd, 0, sizeof (bd_t)); show_boot_progress(0x22); gd->baudrate = CONFIG_BAUDRATE; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - mem_malloc_init((((ulong)ram_start - CONFIG_SYS_MALLOC_LEN)+3)&~3, + mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3, CONFIG_SYS_MALLOC_LEN); for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) { @@ -268,6 +277,9 @@ void board_init_r(gd_t *id, ulong ram_start) } show_boot_progress(0x23); +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif /* configure available FLASH banks */ size = flash_init(); display_flash_config(size); @@ -280,8 +292,10 @@ void board_init_r(gd_t *id, ulong ram_start) show_boot_progress(0x26); +#ifdef CONFIG_CMD_NET /* IP Address */ bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr"); +#endif #if defined(CONFIG_PCI) /* @@ -420,10 +434,17 @@ void hang (void) unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[]) { /* - * TODO: Test this function - changed to fix compiler error. - * Original code was: - * return (entry >> 1) (argc, argv); - * with a comment about Nios function pointers are address >> 1 + * x86 does not use a dedicated register to pass the pointer + * to the global_data */ + argv[-1] = (char *)gd; + return (entry) (argc, argv); } + +void setup_pcat_compatibility(void) + __attribute__((weak, alias("__setup_pcat_compatibility"))); + +void __setup_pcat_compatibility(void) +{ +} diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c index 3c3c1fc..b3f5123 100644 --- a/arch/i386/lib/realmode.c +++ b/arch/i386/lib/realmode.c @@ -37,7 +37,7 @@ extern char realmode_enter; int realmode_setup(void) { - ulong i386boot_realmode = (ulong)&_i386boot_realmode; + ulong i386boot_realmode = (ulong)&_i386boot_realmode + gd->reloc_off; ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size; /* copy the realmode switch code */ diff --git a/arch/i386/lib/zimage.c b/arch/i386/lib/zimage.c index c3b4e59..b39615a 100644 --- a/arch/i386/lib/zimage.c +++ b/arch/i386/lib/zimage.c @@ -34,6 +34,8 @@ #include <asm/zimage.h> #include <asm/realmode.h> #include <asm/byteorder.h> +#include <asm/bootparam.h> +#include <asm/ic/sc520.h> /* * Memory lay-out: @@ -90,48 +92,56 @@ void *load_zimage(char *image, unsigned long kernel_size, int big_image; void *load_address; + struct setup_header *hdr = (struct setup_header *)(image + SETUP_SECTS_OFF); setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */ - if (KERNEL_MAGIC != *(u16*)(image + BOOT_FLAG_OFF)) { - printf("Error: Invalid kernel magic (found 0x%04x, expected 0xaa55)\n", - *(u16*)(image + BOOT_FLAG_OFF)); + if (KERNEL_MAGIC != hdr->boot_flag) { + printf("Error: Invalid Boot Flag (found 0x%04x, expected 0x%04x)\n", + hdr->boot_flag, KERNEL_MAGIC); return 0; + } else { + printf("Valid Boot Flag\n"); } - /* determine boot protocol version */ - if (KERNEL_V2_MAGIC == *(u32*)(image+HEADER_OFF)) { - bootproto = *(u16*)(image+VERSION_OFF); + if (KERNEL_V2_MAGIC == hdr->header) { + printf("Magic signature found\n"); + + bootproto = hdr->version; } else { /* Very old kernel */ + printf("Magic signature not found\n"); bootproto = 0x0100; } /* determine size of setup */ - if (0 == *(u8*)(image + SETUP_SECTS_OFF)) { + if (0 == hdr->setup_sects) { + printf("Setup Sectors = 0 (defaulting to 4)\n"); setup_size = 5 * 512; } else { - setup_size = (*(u8*)(image + SETUP_SECTS_OFF) + 1) * 512; + setup_size = (hdr->setup_sects + 1) * 512; } + printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size); + if (setup_size > SETUP_MAX_SIZE) { printf("Error: Setup is too large (%d bytes)\n", setup_size); } /* Determine image type */ - big_image = (bootproto >= 0x0200) && (*(u8*)(image + LOADFLAGS_OFF) & BIG_KERNEL_FLAG); + big_image = (bootproto >= 0x0200) && (hdr->loadflags & BIG_KERNEL_FLAG); - /* Derermine load address */ - load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR:ZIMAGE_LOAD_ADDR); + /* Determine load address */ + load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR : ZIMAGE_LOAD_ADDR); /* load setup */ + printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n", (ulong)setup_base, setup_size); memmove(setup_base, image, setup_size); printf("Using boot protocol version %x.%02x\n", (bootproto & 0xff00) >> 8, bootproto & 0xff); - if (bootproto == 0x0100) { *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; @@ -154,48 +164,58 @@ void *load_zimage(char *image, unsigned long kernel_size, memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size); } + /* We are now setting up the real-mode version of the header */ + hdr = (struct setup_header *)(setup_base + SETUP_SECTS_OFF); + if (bootproto >= 0x0200) { - *(u8*)(setup_base + TYPE_OF_LOADER_OFF) = 0xff; - printf("Linux kernel version %s\n", - (char*)(setup_base + SETUP_START_OFFSET + - *(u16*)(setup_base + START_SYS_OFF + 2))); + hdr->type_of_loader = 8; + + if (hdr->setup_sects >= 15) + printf("Linux kernel version %s\n", (char *) + (setup_base + (hdr->kernel_version + 0x200))); + else + printf("Setup Sectors < 15 - Cannot print kernel version.\n"); if (initrd_addr) { printf("Initial RAM disk at linear address 0x%08lx, size %ld bytes\n", initrd_addr, initrd_size); - *(u32*)(setup_base + RAMDISK_IMAGE_OFF) = initrd_addr; - *(u32*)(setup_base + RAMDISK_SIZE_OFF)=initrd_size; + hdr->ramdisk_image = initrd_addr; + hdr->ramdisk_size = initrd_size; } } if (bootproto >= 0x0201) { - *(u16*)(setup_base + HEAP_END_PTR_OFF) = HEAP_END_OFFSET; - - /* CAN_USE_HEAP */ - *(u8*)(setup_base + LOADFLAGS_OFF) = - *(u8*)(setup_base + LOADFLAGS_OFF) | HEAP_FLAG; + hdr->heap_end_ptr = HEAP_END_OFFSET; + hdr->loadflags |= HEAP_FLAG; } if (bootproto >= 0x0202) { - *(u32*)(setup_base + CMD_LINE_PTR_OFF) = (u32)setup_base + COMMAND_LINE_OFFSET; + hdr->cmd_line_ptr = (u32)setup_base + COMMAND_LINE_OFFSET; } else if (bootproto >= 0x0200) { + *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - *(u16*)(setup_base + SETUP_MOVE_SIZE_OFF) = 0x9100; + + hdr->setup_move_size = 0x9100; } + if (bootproto >= 0x0204) + kernel_size = hdr->syssize * 16; + else + kernel_size -= setup_size; + if (big_image) { - if ((kernel_size - setup_size) > BZIMAGE_MAX_SIZE) { + if ((kernel_size) > BZIMAGE_MAX_SIZE) { printf("Error: bzImage kernel too big! (size: %ld, max: %d)\n", - kernel_size - setup_size, BZIMAGE_MAX_SIZE); + kernel_size, BZIMAGE_MAX_SIZE); return 0; } - } else if ((kernel_size - setup_size) > ZIMAGE_MAX_SIZE) { + } else if ((kernel_size) > ZIMAGE_MAX_SIZE) { printf("Error: zImage kernel too big! (size: %ld, max: %d)\n", - kernel_size - setup_size, ZIMAGE_MAX_SIZE); + kernel_size, ZIMAGE_MAX_SIZE); return 0; } @@ -203,10 +223,10 @@ void *load_zimage(char *image, unsigned long kernel_size, build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot); printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ', - (u32)load_address, kernel_size - setup_size); + (u32)load_address, kernel_size); - memmove(load_address, image + setup_size, kernel_size - setup_size); + memmove(load_address, image + setup_size, kernel_size); /* ready for booting */ return setup_base; @@ -218,8 +238,51 @@ void boot_zimage(void *setup_base) memset(®s, 0, sizeof(struct pt_regs)); regs.xds = (u32)setup_base >> 4; - regs.xss = 0x9000; + regs.xes = regs.xds; + regs.xss = regs.xds; regs.esp = 0x9000; regs.eflags = 0; enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s); } + +int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + void *base_ptr; + void *bzImage_addr; + ulong bzImage_size = 0; + + disable_interrupts(); + + /* Setup board for maximum PC/AT Compatibility */ + setup_pcat_compatibility(); + + /* argv[1] holds the address of the bzImage */ + bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16); + + if (argc == 3) + bzImage_size = simple_strtoul(argv[2], NULL, 16); + + /* Lets look for*/ + base_ptr = load_zimage (bzImage_addr, bzImage_size, 0, 0, 0); + + if (NULL == base_ptr) { + printf ("## Kernel loading failed ...\n"); + } else { + printf ("## Transferring control to Linux (at address %08x) ...\n", + (u32)base_ptr); + + /* we assume that the kernel is in place */ + printf("\nStarting kernel ...\n\n"); + + boot_zimage(base_ptr); + /* does not return */ + } + + return -1; +} + +U_BOOT_CMD( + zboot, 3, 0, do_zboot, + "Boot bzImage", + "" +); diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index 9cfdb0f..28926e0 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -37,11 +37,11 @@ COBJS-y += interrupts.o COBJS-y += iopin.o COBJS-y += serial.o COBJS-y += speed.o -COBJS-${CONFIG_FSL_DIU_FB} += diu.o -COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o -COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o -COBJS-${CONFIG_CMD_IDE} += ide.o -COBJS-${CONFIG_IIM} += iim.o +COBJS-$(CONFIG_FSL_DIU_FB) += diu.o +COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o +COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o +COBJS-$(CONFIG_CMD_IDE) += ide.o +COBJS-$(CONFIG_IIM) += iim.o COBJS-$(CONFIG_PCI) += pci.o COBJS := $(COBJS-y) diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c index b20234d..44b8a7a 100644 --- a/arch/powerpc/cpu/mpc5xxx/cpu.c +++ b/arch/powerpc/cpu/mpc5xxx/cpu.c @@ -154,26 +154,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); - - *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); - - if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) - return 0; - else - return (*save_addr & 0x0000ffff); -} -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - #ifdef CONFIG_MPC5xxx_FEC /* Default initializations for FEC controllers. To override, * create a board-specific function called: diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c index 992e0ff..5df9735 100644 --- a/arch/powerpc/cpu/mpc8220/fec.c +++ b/arch/powerpc/cpu/mpc8220/fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.c, @@ -27,10 +27,6 @@ static void tfifo_print (char *devname, mpc8220_fec_priv * fec); static void rfifo_print (char *devname, mpc8220_fec_priv * fec); #endif /* DEBUG */ -#ifdef DEBUG -static u32 local_crc32 (char *string, unsigned int crc_value, int len); -#endif - typedef struct { u8 data[1500]; /* actual data */ int length; /* actual length */ @@ -962,39 +958,4 @@ int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) return 0; } -#ifdef DEBUG -static u32 local_crc32 (char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - return crc; -} -#endif /* DEBUG */ - #endif /* CONFIG_MPC8220_FEC */ diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c index 111a67c..c522bc5 100644 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ b/arch/powerpc/cpu/mpc8260/commproc.c @@ -195,27 +195,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 8b98a57..d3be909 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -304,33 +304,3 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -#if !defined(CONFIG_MPC8360) -#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented" -#endif - -#if !defined(CONFIG_BOOTCOUNT_ADDR) -#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long)) -#endif - -#include <asm/io.h> - -void bootcount_store (ulong a) -{ - void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); - out_be32 (reg, a); - out_be32 (reg + 4, BOOTCOUNT_MAGIC); -} - -ulong bootcount_load (void) -{ - void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); - - if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC) - return 0; - else - return in_be32 (reg); -} -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 75b4522..f3b67ae 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -65,16 +65,16 @@ void cpu_init_f (volatile immap_t * im) { __be32 acr_mask = #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ - (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | + ACR_PIPE_DEP | #endif #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ - (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | + ACR_RPTCNT | #endif #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ - (ACR_APARK << ACR_APARK_SHIFT) | + ACR_APARK | #endif #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ - (ACR_PARKM << ACR_PARKM_SHIFT) | + ACR_PARKM | #endif 0; __be32 acr_val = @@ -93,16 +93,16 @@ void cpu_init_f (volatile immap_t * im) 0; __be32 spcr_mask = #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ - (SPCR_OPT << SPCR_OPT_SHIFT) | + SPCR_OPT | #endif #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ - (SPCR_TSECEP << SPCR_TSECEP_SHIFT) | + SPCR_TSECEP | #endif #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | + SPCR_TSEC1EP | #endif #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | + SPCR_TSEC2EP | #endif 0; __be32 spcr_val = @@ -121,34 +121,34 @@ void cpu_init_f (volatile immap_t * im) 0; __be32 sccr_mask = #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ - (SCCR_ENCCM << SCCR_ENCCM_SHIFT) | + SCCR_ENCCM | #endif #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ - (SCCR_PCICM << SCCR_PCICM_SHIFT) | + SCCR_PCICM | #endif #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ - (SCCR_TSECCM << SCCR_TSECCM_SHIFT) | + SCCR_TSECCM | #endif #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ - (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | + SCCR_TSEC1CM | #endif #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ - (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | + SCCR_TSEC2CM | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ - (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | + SCCR_TSEC1ON | #endif #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ - (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | + SCCR_TSEC2ON | #endif #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ - (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | + SCCR_USBMPHCM | #endif #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ - (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | + SCCR_USBDRCM | #endif #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ - (SCCR_SATACM << SCCR_SATACM_SHIFT) | + SCCR_SATACM | #endif 0; __be32 sccr_val = diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index a7c8079..c7d85a8 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -507,7 +507,7 @@ init_e300_core: /* time t 10 */ lis r3, CONFIG_SYS_IMMR@h #if defined(CONFIG_WATCHDOG) - /* Initialise the Wathcdog values and reset it (if req) */ + /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ lis r4, CONFIG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) @@ -520,7 +520,7 @@ init_e300_core: /* time t 10 */ li r4, -0x55C7 sth r4, SWSRR@l(r3) #else - /* Disable Wathcdog */ + /* Disable Watchdog */ /*-------------------*/ lwz r4, SWCRR(r3) /* Check to see if its enabled for disabling @@ -739,6 +739,7 @@ setup_bats: * Note: requires that all cache bits in * HID0 are in the low half word. */ +#ifndef CONFIG_NAND_SPL .globl icache_enable icache_enable: mfspr r3, HID0 @@ -767,6 +768,7 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr +#endif /* !CONFIG_NAND_SPL */ .globl dcache_enable dcache_enable: diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e578b29..99431dc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -30,9 +30,11 @@ #include <watchdog.h> #include <asm/processor.h> #include <ioports.h> +#include <sata.h> #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -418,3 +420,13 @@ void arch_preboot_os(void) setup_ivors(); } + +#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) +int sata_initialize(void) +{ + if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) + return __sata_initialize(); + + return 1; +} +#endif diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index cb6a6f0..7e72f5f 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -1,17 +1,31 @@ /* - * Copyright (C) 2008 Freescale Semicondutor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include <config.h> #include <common.h> #include <asm/io.h> #include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> /* PORDEVSR register */ #define GUTS_PORDEVSR_OFFS 0xc @@ -52,6 +66,61 @@ #define FSL_SRDSCR3_LANEE_SGMII 0x00000000 #define FSL_SRDSCR3_LANEE_SATA 0x00150005 + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 2 + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {SATA1, SATA2}, + [0x3] = {SATA1, NONE}, + [0x4] = {SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {SGMII_TSEC1, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int i; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> + GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg); + + if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return 0; + } + + if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds1_cfg][i] == device) + return 1; + } + for (i = 0; i < SRDS2_MAX_LANES; i++) { + if (serdes2_cfg_tbl[srds2_cfg][i] == device) + return 1; + } + + return 0; +} + void fsl_serdes_init(void) { void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/arch/powerpc/cpu/mpc8xx/commproc.c b/arch/powerpc/cpu/mpc8xx/commproc.c index a87a0dc..2c85377 100644 --- a/arch/powerpc/cpu/mpc8xx/commproc.c +++ b/arch/powerpc/cpu/mpc8xx/commproc.c @@ -103,29 +103,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + - CPM_BOOTCOUNT_ADDR ); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + - CPM_BOOTCOUNT_ADDR ); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index d9d0fa7..dcb37ce 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh) * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 * Not certain if any good value exists for CL=2 */ - /* CL2 CL3 CL4 CL5 CL6 */ -unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 }; + /* CL2 CL3 CL4 CL5 CL6 CL7*/ +unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; unsigned int compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c index 85995ca..186936f 100644 --- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c +++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c @@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] = #elif defined(CONFIG_MPC8536) static struct pci_info pci_config_info[] = { - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, }; #elif defined(CONFIG_MPC8544) static struct pci_info pci_config_info[] = diff --git a/arch/powerpc/cpu/ppc4xx/commproc.c b/arch/powerpc/cpu/ppc4xx/commproc.c index a1696d3..6bf95e6 100644 --- a/arch/powerpc/cpu/ppc4xx/commproc.c +++ b/arch/powerpc/cpu/ppc4xx/commproc.c @@ -51,27 +51,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index dfe8f79..03ae6a7 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -245,6 +245,7 @@ #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ +#define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */ #define MxMR_OP_NORM 0x00000000 /* Normal Operation */ #define MxMR_OP_WARR 0x10000000 /* Write to Array */ #define MxMR_OP_RARR 0x20000000 /* Read from Array */ diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 6da4b6f..d4839f4 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -1,21 +1,48 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef __FSL_SERDES_H #define __FSL_SERDES_H #include <config.h> -#define FSL_SERDES_CLK_100 (0 << 28) -#define FSL_SERDES_CLK_125 (1 << 28) -#define FSL_SERDES_CLK_150 (3 << 28) -#define FSL_SERDES_PROTO_SATA 0 -#define FSL_SERDES_PROTO_PEX 1 -#define FSL_SERDES_PROTO_PEX_X2 2 -#define FSL_SERDES_PROTO_SGMII 3 -#define FSL_SERDES_VDD_1V 1 +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + SRIO1, + SRIO2, + SGMII_FM1, + SGMII_FM2, + SGMII_TSEC1, + SGMII_TSEC2, + SGMII_TSEC3, + SGMII_TSEC4, + XAUI_FM1, + XAUI_FM2, + AURORA, +}; -#ifdef CONFIG_FSL_SERDES -extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd); -#else -static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {} -#endif /* CONFIG_FSL_SERDES */ +int is_serdes_configured(enum srds_prtcl device); #endif /* __FSL_SERDES_H */ diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 334e457..5f85502 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -33,6 +33,7 @@ SOBJS-y += reloc.o COBJS-y += bat_rw.o COBJS-y += board.o COBJS-y += bootm.o +COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o COBJS-y += cache.o COBJS-y += extable.o COBJS-y += interrupts.o diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c new file mode 100644 index 0000000..338c848 --- /dev/null +++ b/arch/powerpc/lib/bootcount.c @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +/* + * Only override CONFIG_SYS_BOOTCOUNT_ADDR if not already defined. This + * way, some boards can define it directly in their config header. + */ +#if !defined(CONFIG_SYS_BOOTCOUNT_ADDR) + +#if defined(CONFIG_MPC5xxx) +#define CONFIG_SYS_BOOTCOUNT_ADDR (MPC5XXX_CDM_BRDCRMB) +#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD +#endif /* defined(CONFIG_MPC5xxx) */ + +#if defined(CONFIG_8xx) +#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \ + CPM_BOOTCOUNT_ADDR) +#endif /* defined(CONFIG_8xx) */ + +#if defined(CONFIG_MPC8260) +#include <asm/cpm_8260.h> + +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) +#endif /* defined(CONFIG_MPC8260) */ + +#if defined(CONFIG_MPC8360) +#include <asm/immap_qe.h> + +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ + QE_MURAM_SIZE - 2 * sizeof(u32)) +#endif /* defined(CONFIG_MPC8360) */ + +#if defined(CONFIG_4xx) +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \ + CONFIG_SYS_BOOTCOUNT_ADDR) +#endif /* defined(CONFIG_4xx) */ + +#endif /* !defined(CONFIG_SYS_BOOTCOUNT_ADDR) */ + +void bootcount_store(ulong a) +{ + void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR; + +#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) + out_be32(reg, (BOOTCOUNT_MAGIC & 0xffff0000) | a); +#else + out_be32(reg, a); + out_be32(reg + 4, BOOTCOUNT_MAGIC); +#endif +} + +ulong bootcount_load(void) +{ + void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR; + +#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) + u32 tmp = in_be32(reg); + + if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return (tmp & 0x0000ffff); +#else + if (in_be32(reg + 4) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32(reg); +#endif +} diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 0685a93..6702df5 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -163,8 +163,8 @@ void arch_lmb_reserve(struct lmb *lmb) sp = get_sp(); debug ("## Current stack ends at 0x%08lx\n", sp); - /* adjust sp by 1K to be safe */ - sp -= 1024; + /* adjust sp by 4K to be safe */ + sp -= 4096; lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); return ; diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index ba47ca1..c028a53 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -146,14 +146,7 @@ void mv_phy_88e1121_init(char *name) miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); /* reset the phy */ - if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __FUNCTION__); - return; - } - if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __FUNCTION__); - return; - } + miiphy_reset(name, devadr); printf("88E1121 Initialized on %s\n", name); } diff --git a/board/barco/barco.c b/board/barco/barco.c index d7a0078..c5fe8c4 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -340,10 +340,6 @@ void serial_puts (const char *c) { return; } -void serial_addr (unsigned int i) -{ - return; -} int serial_getc (void) { return 0; diff --git a/board/eNET/config.mk b/board/eNET/config.mk index dcde7fc..63a58fd 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x38040000 +TEXT_BASE = 0x06000000 CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing PLATFORM_RELFLAGS += -fvisibility=hidden PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 6d0b15a..7f0e257 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -24,6 +24,8 @@ #include <common.h> #include <asm/io.h> #include <asm/ic/sc520.h> +#include <net.h> +#include <netdev.h> #ifdef CONFIG_HW_WATCHDOG #include <watchdog.h> @@ -43,10 +45,13 @@ DECLARE_GLOBAL_DATA_PTR; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; +static void enet_timer_isr(void); +static void enet_toggle_run_led(void); + void init_sc520_enet (void) { /* Set CPU Speed to 100MHz */ - sc520_mmcr->cpuctl = 0x01; + writeb(0x01, &sc520_mmcr->cpuctl); /* wait at least one millisecond */ asm("movl $0x2000,%%ecx\n" @@ -55,7 +60,7 @@ void init_sc520_enet (void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - sc520_mmcr->dbctl = 0x11; + writeb(0x11, &sc520_mmcr->dbctl); /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -70,51 +75,52 @@ int board_early_init_f(void) { init_sc520_enet(); - sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */ - sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */ - sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */ - sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */ - sc520_mmcr->gprdoff = 0x01; /* GP Read offset */ - sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */ - sc520_mmcr->gpwroff = 0x01; /* GP Write offset */ - - sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */ - sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */ - sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */ - sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */ - sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */ - sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */ - sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */ - - sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ - sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ - sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ - sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ - sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */ - sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ - sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ - sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */ - sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */ - sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */ - sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */ - sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */ -/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */ -/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ + writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ + writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ + writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */ + writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */ + writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */ + writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */ + + writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */ + writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */ + writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */ + writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */ + writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */ + writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ + writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */ + + writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ + writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ + writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ + writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ + writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */ + writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ + writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ + writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */ + writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */ + writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ + writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */ + writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */ +/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */ +/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ /* Disable Watchdog */ - sc520_mmcr->wdtmrctl = 0x3333; - sc520_mmcr->wdtmrctl = 0xcccc; - sc520_mmcr->wdtmrctl = 0x0000; + writew(0x3333, &sc520_mmcr->wdtmrctl); + writew(0xcccc, &sc520_mmcr->wdtmrctl); + writew(0x0000, &sc520_mmcr->wdtmrctl); /* Chip Select Configuration */ - sc520_mmcr->bootcsctl = 0x0033; - sc520_mmcr->romcs1ctl = 0x0615; - sc520_mmcr->romcs2ctl = 0x0615; + writew(0x0033, &sc520_mmcr->bootcsctl); + writew(0x0615, &sc520_mmcr->romcs1ctl); + writew(0x0615, &sc520_mmcr->romcs2ctl); - sc520_mmcr->adddecctl = 0x02; - sc520_mmcr->uart1ctl = 0x07; - sc520_mmcr->sysarbctl = 0x06; - sc520_mmcr->sysarbmenb = 0x0003; + writeb(0x00, &sc520_mmcr->adddecctl); + writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x07, &sc520_mmcr->uart2ctl); + writeb(0x06, &sc520_mmcr->sysarbctl); + writew(0x0003, &sc520_mmcr->sysarbmenb); return 0; } @@ -157,6 +163,10 @@ int last_stage_init(void) major = minor = 0; + outb(0x00, LED_LATCH_ADDRESS); + + register_timer_isr (enet_timer_isr); + printf("Serck Controls eNET\n"); return 0; @@ -172,3 +182,84 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) } else return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +void setup_pcat_compatibility() +{ + /* disable global interrupt mode */ + writeb(0x40, &sc520_mmcr->picicr); + + /* set all irqs to edge */ + writeb(0x00, &sc520_mmcr->pic_mode[0]); + writeb(0x00, &sc520_mmcr->pic_mode[1]); + writeb(0x00, &sc520_mmcr->pic_mode[2]); + + /* + * active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins + */ + writew(0x0000,&sc520_mmcr->intpinpol); + + /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); + writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); + writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + + /* Disable all other interrupt sources */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); +} + +void enet_timer_isr(void) +{ + static long enet_ticks = 0; + + enet_ticks++; + + /* Toggle Watchdog every 100ms */ + if ((enet_ticks % 100) == 0) + hw_watchdog_reset(); + + /* Toggle Run LED every 500ms */ + if ((enet_ticks % 500) == 0) + enet_toggle_run_led(); +} + +void hw_watchdog_reset(void) +{ + /* Watchdog Reset must be atomic */ + long flag = disable_interrupts(); + + if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT) + sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT; + else + sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT; + + if (flag) + enable_interrupts(); +} + +void enet_toggle_run_led(void) +{ + unsigned char leds_state= inb(LED_LATCH_ADDRESS); + if (leds_state & LED_RUN_BITMASK) + outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); + else + outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); +} diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index e80a8fe..fefb1a4 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -93,3 +93,36 @@ void pci_init_board(void) { pci_sc520_init(&enet_hose); } + +int pci_set_regions(struct pci_controller *hose) +{ + /* System memory space */ + pci_set_region(hose->regions + 0, + SC520_PCI_MEMORY_BUS, + SC520_PCI_MEMORY_PHYS, + SC520_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 1, + SC520_ISA_MEM_BUS, + SC520_ISA_MEM_PHYS, + SC520_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 2, + SC520_PCI_IO_BUS, + SC520_PCI_IO_PHYS, + SC520_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 3, + SC520_ISA_IO_BUS, + SC520_ISA_IO_PHYS, + SC520_ISA_IO_SIZE, + PCI_REGION_IO); + + return 4; +} diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h index 42474a6..dec2cd8 100644 --- a/board/eNET/hardware.h +++ b/board/eNET/hardware.h @@ -31,5 +31,6 @@ #define LED_RX_BITMASK 0x08 #define LED_TX_BITMASK 0x10 #define LED_ERR_BITMASK 0x20 +#define WATCHDOG_PIO_BIT 0x8000 #endif /* HARDWARE_H_ */ diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index 0d74021..7b0ffaa 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,7 +27,7 @@ ENTRY(_start) SECTIONS { - . = 0x38040000; /* Location of bootcode in flash */ + . = 0x06000000; /* Location of bootcode in flash */ _i386boot_text_start = .; .text : { *(.text); } @@ -97,14 +97,13 @@ SECTIONS * at reset and the code have to fit. * The fff0 offset of resetvec is important, however. */ - . = 0xfffffe00; - .start32 : AT (0x3807fe00) { *(.start32); } + .start32 : AT (0x0603fe00) { *(.start32); } . = 0xf800; - .start16 : AT (0x3807f800) { *(.start16); } + .start16 : AT (0x0603f800) { *(.start16); } . = 0xfff0; - .resetvec : AT (0x3807fff0) { *(.resetvec); } + .resetvec : AT (0x0603fff0) { *(.resetvec); } _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 2ae4cbd..a199d46 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -1090,3 +1090,15 @@ U_BOOT_CMD( "Show Marvell strapping register", "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)" ); + +int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER)); + + return 0; +} + +U_BOOT_CMD( + pldver, 1, 1, do_pldver, + "Show PLD version", + "Show PLD version)"); diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 4c03630..5347958 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -538,14 +538,14 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) break; /*------------------------------------------------------------------------------------------------------------------------------*/ -#ifdef CONFIG_ECC +#ifdef CONFIG_MV64360_ECC case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; DP (printf ("Error Check Type (0=NONE): %d\n", dimmInfo->errorCheckType)); break; -#endif +#endif /* of ifdef CONFIG_MV64360_ECC */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ @@ -1254,6 +1254,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) ulong tmp; ulong tmp_sdram_mode = 0; /* 0x141c */ ulong tmp_dunit_control_low = 0; /* 0x1404 */ + uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG; int i; /* sanity checking */ @@ -1269,7 +1270,6 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) DP (printf ("Module is registered, but we do not support registered Modules !!!\n")); - /* delay line */ set_dfcdlInit (); /* may be its not needed */ DP (printf ("Delay line set done\n")); @@ -1281,8 +1281,16 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); } +#ifdef CONFIG_MV64360_ECC + if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) { + /* DRAM has ECC, so turn it on */ + sdram_config_reg |= BIT18; + DP(printf("Enabling ECC\n")); + } +#endif /* of ifdef CONFIG_MV64360_ECC */ + /* SDRAM configuration */ - GT_REG_WRITE (SDRAM_CONFIG, 0x58200400); + GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg); DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); /* SDRAM open pages controll keep open as much as I can */ @@ -1598,7 +1606,84 @@ dram_size(long int *base, long int maxsize) return maxsize; } -/* ------------------------------------------------------------------------- */ +#ifdef CONFIG_MV64360_ECC +/* + * mv_dma_is_channel_active: + * Checks if a engine is busy. + */ +int mv_dma_is_channel_active(int engine) +{ + ulong data; + + data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); + if (data & BIT14) /* activity status */ + return 1; + + return 0; +} + +/* + * mv_dma_set_memory_space: + * Set a DMA memory window for the DMA's address decoding map. + */ +int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target, + ulong mem_space_attr, ulong base_address, + ulong size) +{ + ulong temp; + + /* The base address must be aligned to the size. */ + if (base_address % size != 0) + return 0; + + if (size >= 0x10000) { + size &= 0xffff0000; + base_address = (base_address & 0xffff0000); + /* Set the new attributes */ + GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8, + (base_address | mem_space_target | + mem_space_attr)); + GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8), + (size - 1) & 0xffff0000); + temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG); + GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG, + (temp & ~(BIT0 << mem_space))); + return 1; + } + + return 0; +} + + +/* + * mv_dma_transfer: + * Transfer data from source_addr to dest_addr on one of the 4 DMA channels. + */ +int mv_dma_transfer(int engine, ulong source_addr, + ulong dest_addr, ulong bytes, ulong command) +{ + ulong eng_off_reg; /* Engine Offset Register */ + + if (bytes > 0xffff) + command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ + + command = command | ((command >> 6) & 0x7); + eng_off_reg = engine * 4; + GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg, + bytes); + GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg, + source_addr); + GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg, + dest_addr); + command |= BIT12 /* DMA_CHANNEL_ENABLE */ + | BIT9; /* DMA_NON_CHAIN_MODE */ + + /* Activate DMA engine By writting to mv_dma_control_register */ + GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command); + + return 1; +} +#endif /* of ifdef CONFIG_MV64360_ECC */ /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ @@ -1607,10 +1692,13 @@ initdram(int board_type) { int s0 = 0, s1 = 0; int checkbank[4] = { [0 ... 3] = 0 }; - ulong bank_no, realsize, total, check; + ulong realsize, total, check; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; - int nhr; + int bank_no, nhr; +#ifdef CONFIG_MV64360_ECC + ulong dest, mem_space_attr; +#endif /* of ifdef CONFIG_MV64360_ECC */ /* first, use the SPD to get info about the SDRAM/ DDRRAM */ @@ -1668,6 +1756,28 @@ initdram(int board_type) realsize = dram_size((long int *)total, check); memory_map_bank(bank_no, total, realsize); +#ifdef CONFIG_MV64360_ECC + if (((dimmInfo1.errorCheckType != 0) && + ((dimmInfo2.errorCheckType != 0) || + (dimmInfo2.numOfModuleBanks == 0))) && + (CPCI750_ECC_TEST)) { + printf("ECC Initialization of Bank %d:", bank_no); + mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8; + mv_dma_set_memory_space(0, 0, mem_space_attr, total, + realsize); + for (dest = total; dest < total + realsize; + dest += _8M) { + mv_dma_transfer(0, total, dest, _8M, + BIT8 | /* DMA_DTL_128BYTES */ + BIT3 | /* DMA_HOLD_SOURCE_ADDR */ + BIT11); /* DMA_BLOCK_TRANSFER_MODE */ + while (mv_dma_is_channel_active(0)) + ; + } + printf(" PASS\n"); + } +#endif /* of ifdef CONFIG_MV64360_ECC */ + total += realsize; } @@ -1700,3 +1810,30 @@ int set_dfcdlInit (void) return (0); } + +int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int ecc_counter; + unsigned int ecc_addr; + + GT_REG_READ(0x1458, &ecc_counter); + GT_REG_READ(0x1450, &ecc_addr); + GT_REG_WRITE(0x1450, 0); + + printf("Error Counter since Reset: %8d\n", ecc_counter); + printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8); + if (ecc_addr & 0x01) + printf("double"); + else + printf("single"); + printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1)); + + return 0; +} + + +U_BOOT_CMD( + show_ecc, 1, 1, do_show_ecc, + "Show Marvell MV64360 ECC Info", + "Show Marvell MV64360 ECC Counter and last error." +); diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 0fb4efa..0a4dbaa 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -25,4 +25,4 @@ # esd PLU405 boards # -TEXT_BASE = 0xFFFA0000 +TEXT_BASE = 0xFFF80000 diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 620eb16..df289aa 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,18 +29,18 @@ endif LIB = $(obj)lib$(VENDOR).a -COBJS-${CONFIG_FSL_CADMUS} += cadmus.o -COBJS-${CONFIG_FSL_VIA} += cds_via.o -COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o -COBJS-${CONFIG_FSL_PIXIS} += pixis.o -COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o -COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o -COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o -COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o +COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o +COBJS-$(CONFIG_FSL_VIA) += cds_via.o +COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o fsl_logo_bmp.o +COBJS-$(CONFIG_FSL_PIXIS) += pixis.o +COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o +COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o -COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o -COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o -COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o +COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o +COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o +COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index cbee8fe..e740ad8 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010 Freescale Semiconductor, Inc. * York Sun <yorksun@freescale.com> * * FSL DIU Framebuffer driver @@ -26,6 +26,7 @@ #include <common.h> #include <i2c.h> #include <malloc.h> +#include <asm/io.h> #include "fsl_diu_fb.h" @@ -267,9 +268,9 @@ int fsl_diu_init(int xres, memset(info->screen_base, 0, info->smem_len); - dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; - dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; - dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; + out_be32(&dr.diu_reg->desc[0], (int)&dummy_ad); + out_be32(&dr.diu_reg->desc[1], (int)&dummy_ad); + out_be32(&dr.diu_reg->desc[2], (int)&dummy_ad); debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); debug("dummy desc[0] = 0x%x\n", hw->desc[0]); @@ -331,26 +332,26 @@ int fsl_diu_init(int xres, /* Program DIU registers */ - hw->gamma = (unsigned int) gamma.paddr; - hw->cursor= (unsigned int) cursor.paddr; - hw->bgnd = 0x007F7F7F; /* BGND */ - hw->bgnd_wb = 0; /* BGND_WB */ - hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */ - hw->wb_size = 0; /* WB SIZE */ - hw->wb_mem_addr = 0; /* WB MEM ADDR */ - hw->hsyn_para = var->left_margin << 22 | /* BP_H */ + out_be32(&hw->gamma, (int)gamma.paddr); + out_be32(&hw->cursor, (int)cursor.paddr); + out_be32(&hw->bgnd, 0x007F7F7F); + out_be32(&hw->bgnd_wb, 0); /* BGND_WB */ + out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */ + out_be32(&hw->wb_size, 0); /* WB SIZE */ + out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */ + out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */ var->hsync_len << 11 | /* PW_H */ - var->right_margin; /* FP_H */ - hw->vsyn_para = var->upper_margin << 22 | /* BP_V */ - var->vsync_len << 11 | /* PW_V */ - var->lower_margin; /* FP_V */ + var->right_margin); /* FP_H */ - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ - hw->thresholds = 0x00037800; /* The Thresholds */ - hw->int_status = 0; /* INTERRUPT STATUS */ - hw->int_mask = 0; /* INT MASK */ - hw->plut = 0x01F5F666; + out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */ + var->vsync_len << 11 | /* PW_V */ + var->lower_margin); /* FP_V */ + out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */ + out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */ + out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */ + out_be32(&hw->int_mask, 0); /* INT MASK */ + out_be32(&hw->plut, 0x01F5F666); /* Pixel Clock configuration */ debug("DIU pixclock in ps - %d\n", var->pixclock); diu_set_pixel_clock(var->pixclock); @@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info) struct diu_ad *ad = &fsl_diu_fb_ad; debug("Entered: enable_panel\n"); - if (hw->desc[0] != (unsigned int)ad) - hw->desc[0] = (unsigned int)ad; + if (in_be32(&hw->desc[0]) != (unsigned)ad) + out_be32(&hw->desc[0], (unsigned)ad); debug("desc[0] = 0x%x\n", hw->desc[0]); return 0; } @@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info) struct diu *hw = dr.diu_reg; debug("Entered: disable_panel\n"); - if (hw->desc[0] != (unsigned int)&dummy_ad) - hw->desc[0] = (unsigned int)&dummy_ad; + if (in_be32(&hw->desc[0]) != (unsigned)&dummy_ad) + out_be32(&hw->desc[0], (unsigned)&dummy_ad); return 0; } @@ -443,7 +444,7 @@ static void enable_lcdc(void) debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); if (!fb_enabled) { - hw->diu_mode = dr.mode; + out_be32(&hw->diu_mode, dr.mode); fb_enabled++; } debug("diu_mode = %d\n", hw->diu_mode); @@ -455,7 +456,7 @@ static void disable_lcdc(void) debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); if (fb_enabled) { - hw->diu_mode = 0; + out_be32(&hw->diu_mode, 0); fb_enabled = 0; } } diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 1f11563..61b7454 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -28,15 +28,7 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 253ed18..1968106 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,6 +30,7 @@ #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> #include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd.h> #include <miiphy.h> #include <libfdt.h> @@ -219,9 +220,13 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", @@ -239,9 +244,13 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", @@ -259,9 +268,13 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", @@ -285,6 +298,10 @@ void pci_init_board(void) pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_PCI); + set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCI); SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", @@ -481,17 +498,6 @@ get_board_ddr_clk(ulong dummy) } #endif -int sata_initialize(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - if (sdrs2_io_sel & 0x04) - return 1; - - return __sata_initialize(); -} - int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET @@ -540,15 +546,23 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#else + ft_fsl_pci_setup(blob, "pci0", NULL); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#else + ft_fsl_pci_setup(blob, "pci1", NULL); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#else + ft_fsl_pci_setup(blob, "pci2", NULL); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); +#else + ft_fsl_pci_setup(blob, "pci3", NULL); #endif #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index 930a206..847edaf 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -27,7 +27,7 @@ COBJS-y += $(BOARD).o COBJS-$(CONFIG_FSL_DDR2) += ddr.o COBJS-y += law.o -COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o +COBJS-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/korat/korat.c b/board/korat/korat.c index d5260dc..e5ec694 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2009 + * (C) Copyright 2007-2010 * Larry Johnson, lrj@acm.org * * (C) Copyright 2006-2007 @@ -417,7 +417,7 @@ int misc_init_r(void) * then connect the CompactFlash controller to the PowerPC USB * port. */ - printf("Attaching CompactFalsh controller to PPC USB\n"); + printf("Attaching CompactFlash controller to PPC USB\n"); out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10); } else { @@ -425,7 +425,7 @@ int misc_init_r(void) printf("Warning: \"korat_usbcf\" is not set to a legal " "value (\"ppc\" or \"pci\")\n"); - printf("Attaching CompactFalsh controller to PCI USB\n"); + printf("Attaching CompactFlash controller to PCI USB\n"); } if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index 504935f..12c7cb6 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -32,12 +32,13 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) + @mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img ######################################################################### diff --git a/board/matrix_vision/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/bootscript index dc385fd..dc385fd 100644 --- a/board/matrix_vision/mvblm7/mvblm7_autoscript +++ b/board/matrix_vision/mvblm7/bootscript diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index b179e6d..2817fe0 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -36,13 +36,13 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) - @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img + @mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img ######################################################################### diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 3e917a9..f9b103e 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -55,11 +55,11 @@ SECTIONS { /* WARNING - the following is hand-optimized to fit within */ /* the first two sectors (=8KB) of our S29GL flash chip */ - arch/powerpc/cpu/mpc5xxx/start.o (.text) - arch/powerpc/cpu/mpc5xxx/traps.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/cache.o (.text) - arch/powerpc/lib/time.o (.text) + arch/powerpc/cpu/mpc5xxx/start.o (.text) + arch/powerpc/cpu/mpc5xxx/traps.o (.text) + lib/crc32.o (.text) + arch/powerpc/lib/cache.o (.text) + arch/powerpc/lib/time.o (.text) /* This is only needed to force failure if size of above code will ever */ /* increase and grow into reserved space. */ diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile new file mode 100644 index 0000000..dad0457 --- /dev/null +++ b/board/mosaixtech/icon/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009-2010 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o +SOBJS = init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c new file mode 100644 index 0000000..b9dd447 --- /dev/null +++ b/board/mosaixtech/icon/chip_config.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/ppc4xx_config.h> + +struct ppc4xx_config ppc4xx_config_val[] = { + { + "400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83", + { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66", + { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", + { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } + }, + { + "800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17", + { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } + }, +}; + +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk new file mode 100644 index 0000000..b2748ce --- /dev/null +++ b/board/mosaixtech/icon/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2009-2010 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFA0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c new file mode 100644 index 0000000..fbace9e --- /dev/null +++ b/board/mosaixtech/icon/icon.c @@ -0,0 +1,319 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ppc4xx.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/4xx_pcie.h> +#include <asm/errno.h> +#include <asm/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + unsigned long mfr; + + /* + * Interrupt controller setup for the ICON 440SPe board. + * + *-------------------------------------------------------------------- + * IRQ | Source | Pol. | Sensi.| Crit. + *--------+-----------------------------------+-------+-------+------- + * IRQ 00 | UART0 | High | Level | Non + * IRQ 01 | UART1 | High | Level | Non + * IRQ 02 | IIC0 | High | Level | Non + * IRQ 03 | IIC1 | High | Level | Non + * IRQ 04 | PCI0X0 MSG IN | High | Level | Non + * IRQ 05 | PCI0X0 CMD Write | High | Level | Non + * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non + * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non + * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non + * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non + * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non + * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit + * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non + * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non + * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non + * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non + * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non + * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit + * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non + * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non + * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non + * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non + * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non + * IRQ 23 | I2O Inbound Doorbell | High | Level | Non + * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non + * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non + * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non + * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non + * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non + * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non + * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non + * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. + *-------------------------------------------------------------------- + * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non + * IRQ 33 | MAL Serr | High | Level | Non + * IRQ 34 | MAL Txde | High | Level | Non + * IRQ 35 | MAL Rxde | High | Level | Non + * IRQ 36 | DMC CE or DMC UE | High | Level | Non + * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non + * IRQ 38 | MAL TX EOB | High | Level | Non + * IRQ 39 | MAL RX EOB | High | Level | Non + * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non + * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non + * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non + * IRQ 43 | L2 Cache | Risin | Edge | Non + * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non + * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non + * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non + * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non + * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non + * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non + * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non + * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non + * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non + * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non + * IRQ 54 | DMA Error | High | Level | Non + * IRQ 55 | DMA I2O Error | High | Level | Non + * IRQ 56 | Serial ROM | High | Level | Non + * IRQ 57 | PCIX0 Error | High | Edge | Non + * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non + * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non + * IRQ 60 | EMAC0 Interrupt | High | Level | Non + * IRQ 61 | EMAC0 Wake-up | High | Level | Non + * IRQ 62 | Reserved | High | Level | Non + * IRQ 63 | XOR | High | Level | Non + *-------------------------------------------------------------------- + * IRQ 64 | PE0 AL | High | Level | Non + * IRQ 65 | PE0 VPD Access | Risin | Edge | Non + * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non + * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non + * IRQ 68 | PE0 TCR | High | Level | Non + * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non + * IRQ 70 | PE0 DCR Error | High | Level | Non + * IRQ 71 | Reserved | N/A | N/A | Non + * IRQ 72 | PE1 AL | High | Level | Non + * IRQ 73 | PE1 VPD Access | Risin | Edge | Non + * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non + * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non + * IRQ 76 | PE1 TCR | High | Level | Non + * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non + * IRQ 78 | PE1 DCR Error | High | Level | Non + * IRQ 79 | Reserved | N/A | N/A | Non + * IRQ 80 | PE2 AL | High | Level | Non + * IRQ 81 | PE2 VPD Access | Risin | Edge | Non + * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non + * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non + * IRQ 84 | PE2 TCR | High | Level | Non + * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non + * IRQ 86 | PE2 DCR Error | High | Level | Non + * IRQ 87 | Reserved | N/A | N/A | Non + * IRQ 88 | External IRQ(5) | Progr | Progr | Non + * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non + * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non + * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non + * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non + * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non + * IRQ 94 | Reserved | N/A | N/A | Non + * IRQ 95 | Reserved | N/A | N/A | Non + *-------------------------------------------------------------------- + * IRQ 96 | PE0 INTA | High | Level | Non + * IRQ 97 | PE0 INTB | High | Level | Non + * IRQ 98 | PE0 INTC | High | Level | Non + * IRQ 99 | PE0 INTD | High | Level | Non + * IRQ 100| PE1 INTA | High | Level | Non + * IRQ 101| PE1 INTB | High | Level | Non + * IRQ 102| PE1 INTC | High | Level | Non + * IRQ 103| PE1 INTD | High | Level | Non + * IRQ 104| PE2 INTA | High | Level | Non + * IRQ 105| PE2 INTB | High | Level | Non + * IRQ 106| PE2 INTC | High | Level | Non + * IRQ 107| PE2 INTD | Risin | Edge | Non + * IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non + * IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non + * IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non + * IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non + * IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non + * IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non + * IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non + * IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non + * IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non + * IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non + * IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non + * IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non + * IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non + * IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non + * IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non + * IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non + * IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non + * IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non + * IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non + * IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non + */ + + /* + * Put UICs in PowerPC 440SPe mode. + * Initialise UIC registers. Clear all interrupts. Disable all + * interrupts. Set critical interrupt values. Set interrupt polarities. + * Set interrupt trigger levels. Make bit 0 High priority. Clear all + * interrupts again. + */ + mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ + mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */ + mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */ + mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/ + + mfsdr(SDR0_MFR, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(SDR0_MFR, mfr); + + mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); + + out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR); + out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR); + out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR); + + return 0; +} + +int board_early_init_r(void) +{ + /* + * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.ec00.0000 + */ + + /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */ + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + + /* Remove TLB entry of boot EBC mapping */ + remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); + + /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */ + program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); + + /* + * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address + * 0xfc00.0000 is possible + */ + + /* + * Clear potential errors resulting from auto-calibration. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: ICON"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + * + * Tested successfully with the following SODIMM: + * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) + * + * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state, + * directly after power-up. Only after running for more than 10 minutes + * real stable auto-calibration windows could be found. + */ +u32 ddr_wrdtr(u32 default_val) +{ + return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV; +} + +u32 ddr_clktr(u32 default_val) +{ + return SDRAM_CLKTR_CLKP_180_DEG_ADV; +} + +/* + * Override the weak default implementation and return the + * last PCIe slot number (max number - 1). + */ +int board_pcie_last(void) +{ + /* Only 2 PCIe ports used on ICON, so the last one is 1 */ + return 1; +} diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S new file mode 100644 index 0000000..70ed6ce --- /dev/null +++ b/board/mosaixtech/icon/init.S @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/* + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + */ + + .section .bootpg,"ax" + + .globl tlbtab +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to + * use the speed up boot process. It is patched after relocation to + * enable SA_I. + */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) /* TLB 0 */ + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, + AC_RWX | SA_I) + + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, + CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, + AC_RW | SA_IG) + tlbtab_end diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index 1044de2..cb30b48 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -29,16 +29,17 @@ #include <mpc83xx.h> #include <ns16550.h> #include <nand.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_NAND_SPL int checkboard(void) { puts("Board: Sheldon Instruments SIMPC8313\n"); return 0; } -#ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -91,6 +92,40 @@ void pci_init_board(void) int misc_init_r(void) { int rc = 0; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + fsl_lbus_t *lbus = &immap->lbus; + u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ + + /* UPM Table Configuration Code */ + static uint UPMATable[] = { + /* Read Single-Beat (RSS) */ + 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Read Burst (RBS) */ + 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c, + 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Write Single-Beat (WSS) */ + 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Write Burst (WBS) */ + 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00, + 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c, + 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Refresh Timer (RTS) */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + /* Exception Condition (EXS) */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 + }; + + upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); + + /* Set LUPWAIT to be active low and enabled */ + out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS); return rc; } diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 452686d..da06009 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -344,11 +344,8 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) printf (" XIP %s ... ", type_name); } else { printf (" Loading %s ... ", type_name); - - if (load != image_start) { - memmove_wd ((void *)load, - (void *)image_start, image_len, CHUNKSZ); - } + memmove_wd ((void *)load, (void *)image_start, + image_len, CHUNKSZ); } *load_end = load + image_len; puts("OK\n"); diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 3773412..6361c4e 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -34,7 +34,7 @@ #if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS) #include <jffs2/jffs2.h> -/* parition handling routines */ +/* partition handling routines */ int mtdparts_init(void); int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); int find_dev_and_part(const char *id, struct mtd_device **dev, @@ -368,7 +368,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_first = part->offset + info->start[0]; addr_last = addr_first + part->size - 1; - printf ("Erase Flash Parition %s, " + printf ("Erase Flash Partition %s, " "bank %ld, 0x%08lx - 0x%08lx ", argv[1], bank, addr_first, addr_last); @@ -576,7 +576,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_first = part->offset + info->start[0]; addr_last = addr_first + part->size - 1; - printf ("%sProtect Flash Parition %s, " + printf ("%sProtect Flash Partition %s, " "bank %ld, 0x%08lx - 0x%08lx\n", p ? "" : "Un", argv[1], bank, addr_first, addr_last); diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 0b5f747..116e637 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -103,16 +103,6 @@ #include <onenand_uboot.h> #endif -/* enable/disable debugging messages */ -#define DEBUG_MTDPARTS -#undef DEBUG_MTDPARTS - -#ifdef DEBUG_MTDPARTS -# define DEBUGF(fmt, args...) printf(fmt ,##args) -#else -# define DEBUGF(fmt, args...) -#endif - /* special size referring to all the remaining space in a partition */ #define SIZE_REMAINING 0xFFFFFFFF @@ -243,7 +233,7 @@ static void index_partitions(void) struct list_head *dentry; struct mtd_device *dev; - DEBUGF("--- index partitions ---\n"); + debug("--- index partitions ---\n"); if (current_mtd_dev) { mtddevnum = 0; @@ -261,12 +251,12 @@ static void index_partitions(void) part = mtd_part_info(current_mtd_dev, current_mtd_partnum); setenv("mtddevname", part->name); - DEBUGF("=> mtddevnum %d,\n=> mtddevname %s\n", mtddevnum, part->name); + debug("=> mtddevnum %d,\n=> mtddevname %s\n", mtddevnum, part->name); } else { setenv("mtddevnum", NULL); setenv("mtddevname", NULL); - DEBUGF("=> mtddevnum NULL\n=> mtddevname NULL\n"); + debug("=> mtddevnum NULL\n=> mtddevname NULL\n"); } } @@ -277,7 +267,7 @@ static void current_save(void) { char buf[16]; - DEBUGF("--- current_save ---\n"); + debug("--- current_save ---\n"); if (current_mtd_dev) { sprintf(buf, "%s%d,%d", MTD_DEV_TYPE(current_mtd_dev->id->type), @@ -286,12 +276,12 @@ static void current_save(void) setenv("partition", buf); strncpy(last_partition, buf, 16); - DEBUGF("=> partition %s\n", buf); + debug("=> partition %s\n", buf); } else { setenv("partition", NULL); last_partition[0] = '\0'; - DEBUGF("=> partition NULL\n"); + debug("=> partition NULL\n"); } index_partitions(); } @@ -505,7 +495,7 @@ static int part_sort_add(struct mtd_device *dev, struct part_info *part) part->dev = dev; if (list_empty(&dev->parts)) { - DEBUGF("part_sort_add: list empty\n"); + debug("part_sort_add: list empty\n"); list_add(&part->link, &dev->parts); dev->num_parts++; index_partitions(); @@ -598,7 +588,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i /* fetch the partition size */ if (*p == '-') { /* assign all remaining space to this partition */ - DEBUGF("'-': remaining size assigned\n"); + debug("'-': remaining size assigned\n"); size = SIZE_REMAINING; p++; } else { @@ -683,7 +673,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i part->name[name_len - 1] = '\0'; INIT_LIST_HEAD(&part->link); - DEBUGF("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n", + debug("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n", part->name, part->size, part->offset, part->mask_flags); @@ -837,14 +827,16 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_ u32 offset; int err = 1; - p = mtd_dev; + debug("===device_parse===\n"); + + assert(retdev); *retdev = NULL; - *ret = NULL; - DEBUGF("===device_parse===\n"); + if (ret) + *ret = NULL; /* fetch <mtd-id> */ - mtd_id = p; + mtd_id = p = mtd_dev; if (!(p = strchr(mtd_id, ':'))) { printf("no <mtd-id> identifier\n"); return 1; @@ -858,11 +850,11 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_ return 1; } - DEBUGF("dev type = %d (%s), dev num = %d, mtd-id = %s\n", + debug("dev type = %d (%s), dev num = %d, mtd-id = %s\n", id->type, MTD_DEV_TYPE(id->type), id->num, id->mtd_id); pend = strchr(p, ';'); - DEBUGF("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p); + debug("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p); /* parse partitions */ @@ -908,17 +900,20 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_ return 1; } - DEBUGF("\ntotal partitions: %d\n", num_parts); + debug("\ntotal partitions: %d\n", num_parts); /* check for next device presence */ if (p) { if (*p == ';') { - *ret = ++p; + if (ret) + *ret = ++p; } else if (*p == '\0') { - *ret = p; + if (ret) + *ret = p; } else { printf("unexpected character '%c' at the end of device\n", *p); - *ret = NULL; + if (ret) + *ret = NULL; return 1; } } @@ -946,7 +941,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_ *retdev = dev; - DEBUGF("===\n\n"); + debug("===\n\n"); return 0; } @@ -998,13 +993,13 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_ struct list_head *entry; struct mtdids *id; - DEBUGF("--- id_find_by_mtd_id: '%.*s' (len = %d)\n", + debug("--- id_find_by_mtd_id: '%.*s' (len = %d)\n", mtd_id_len, mtd_id, mtd_id_len); list_for_each(entry, &mtdids) { id = list_entry(entry, struct mtdids, link); - DEBUGF("entry: '%s' (len = %d)\n", + debug("entry: '%s' (len = %d)\n", id->mtd_id, strlen(id->mtd_id)); if (mtd_id_len != strlen(id->mtd_id)) @@ -1074,7 +1069,7 @@ static int generate_mtdparts(char *buf, u32 buflen) u32 size, offset, len, part_cnt; u32 maxlen = buflen - 1; - DEBUGF("--- generate_mtdparts ---\n"); + debug("--- generate_mtdparts ---\n"); if (list_empty(&devices)) { buf[0] = '\0'; @@ -1216,7 +1211,7 @@ static void list_partitions(void) struct mtd_device *dev; int part_num; - DEBUGF("\n---list_partitions---\n"); + debug("\n---list_partitions---\n"); list_for_each(dentry, &devices) { dev = list_entry(dentry, struct mtd_device, link); printf("\ndevice %s%d <%s>, # parts = %d\n", @@ -1281,7 +1276,7 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, u8 type, dnum, pnum; const char *p; - DEBUGF("--- find_dev_and_part ---\nid = %s\n", id); + debug("--- find_dev_and_part ---\nid = %s\n", id); list_for_each(dentry, &devices) { *part_num = 0; @@ -1342,7 +1337,7 @@ static int delete_partition(const char *id) if (find_dev_and_part(id, &dev, &pnum, &part) == 0) { - DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n", + debug("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum, part->name, part->size, part->offset); @@ -1373,7 +1368,7 @@ static int parse_mtdparts(const char *const mtdparts) struct mtd_device *dev; int err = 1; - DEBUGF("\n---parse_mtdparts---\nmtdparts = %s\n\n", p); + debug("\n---parse_mtdparts---\nmtdparts = %s\n\n", p); /* delete all devices and partitions */ if (mtd_devices_init() != 0) { @@ -1395,7 +1390,7 @@ static int parse_mtdparts(const char *const mtdparts) if ((device_parse(p, &p, &dev) != 0) || (!dev)) break; - DEBUGF("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), + debug("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, dev->id->mtd_id); /* check if parsed device is already on the list */ @@ -1436,12 +1431,12 @@ static int parse_mtdids(const char *const ids) u32 size; int ret = 1; - DEBUGF("\n---parse_mtdids---\nmtdids = %s\n\n", ids); + debug("\n---parse_mtdids---\nmtdids = %s\n\n", ids); /* clean global mtdids list */ list_for_each_safe(entry, n, &mtdids) { id_tmp = list_entry(entry, struct mtdids, link); - DEBUGF("mtdids del: %d %d\n", id_tmp->type, id_tmp->num); + debug("mtdids del: %d %d\n", id_tmp->type, id_tmp->num); list_del(entry); free(id_tmp); } @@ -1507,7 +1502,7 @@ static int parse_mtdids(const char *const ids) id->mtd_id[mtd_id_len - 1] = '\0'; INIT_LIST_HEAD(&id->link); - DEBUGF("+ id %s%d\t%16d bytes\t%s\n", + debug("+ id %s%d\t%16d bytes\t%s\n", MTD_DEV_TYPE(id->type), id->num, id->size, id->mtd_id); @@ -1541,7 +1536,7 @@ int mtdparts_init(void) int ids_changed; char tmp_ep[PARTITION_MAXLEN]; - DEBUGF("\n---mtdparts_init---\n"); + debug("\n---mtdparts_init---\n"); if (!initialized) { INIT_LIST_HEAD(&mtdids); INIT_LIST_HEAD(&devices); @@ -1562,18 +1557,18 @@ int mtdparts_init(void) if (current_partition) strncpy(tmp_ep, current_partition, PARTITION_MAXLEN); - DEBUGF("last_ids : %s\n", last_ids); - DEBUGF("env_ids : %s\n", ids); - DEBUGF("last_parts: %s\n", last_parts); - DEBUGF("env_parts : %s\n\n", parts); + debug("last_ids : %s\n", last_ids); + debug("env_ids : %s\n", ids); + debug("last_parts: %s\n", last_parts); + debug("env_parts : %s\n\n", parts); - DEBUGF("last_partition : %s\n", last_partition); - DEBUGF("env_partition : %s\n", current_partition); + debug("last_partition : %s\n", last_partition); + debug("env_partition : %s\n", current_partition); /* if mtdids varible is empty try to use defaults */ if (!ids) { if (mtdids_default) { - DEBUGF("mtdids variable not defined, using default\n"); + debug("mtdids variable not defined, using default\n"); ids = mtdids_default; setenv("mtdids", (char *)ids); } else { @@ -1629,7 +1624,7 @@ int mtdparts_init(void) current_mtd_partnum = 0; current_save(); - DEBUGF("mtdparts_init: current_mtd_dev = %s%d, current_mtd_partnum = %d\n", + debug("mtdparts_init: current_mtd_dev = %s%d, current_mtd_partnum = %d\n", MTD_DEV_TYPE(current_mtd_dev->id->type), current_mtd_dev->id->num, current_mtd_partnum); } @@ -1648,7 +1643,7 @@ int mtdparts_init(void) struct mtd_device *cdev; u8 pnum; - DEBUGF("--- getting current partition: %s\n", tmp_ep); + debug("--- getting current partition: %s\n", tmp_ep); if (find_dev_and_part(tmp_ep, &cdev, &pnum, &p) == 0) { current_mtd_dev = cdev; @@ -1656,7 +1651,7 @@ int mtdparts_init(void) current_save(); } } else if (getenv("partition") == NULL) { - DEBUGF("no partition variable set, setting...\n"); + debug("no partition variable set, setting...\n"); current_save(); } @@ -1680,7 +1675,7 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part if (!dev) return NULL; - DEBUGF("\n--- mtd_part_info: partition number %d for device %s%d (%s)\n", + debug("\n--- mtd_part_info: partition number %d for device %s%d (%s)\n", part_num, MTD_DEV_TYPE(dev->id->type), dev->id->num, dev->id->mtd_id); @@ -1816,12 +1811,12 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } sprintf(tmpbuf, "%s:%s(%s)%s", id->mtd_id, argv[3], argv[4], argv[5] ? argv[5] : ""); - DEBUGF("add tmpbuf: %s\n", tmpbuf); + debug("add tmpbuf: %s\n", tmpbuf); if ((device_parse(tmpbuf, NULL, &dev) != 0) || (!dev)) return 1; - DEBUGF("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), + debug("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, dev->id->mtd_id); if ((dev_tmp = device_find(dev->id->type, dev->id->num)) == NULL) { @@ -1845,7 +1840,7 @@ int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* mtdparts del part-id */ if ((argc == 3) && (strcmp(argv[1], "del") == 0)) { - DEBUGF("del: part-id = %s\n", argv[2]); + debug("del: part-id = %s\n", argv[2]); return delete_partition(argv[2]); } diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 9b0c930..f611fd7 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -19,7 +19,7 @@ #if defined(CONFIG_CMD_MTDPARTS) -/* parition handling routines */ +/* partition handling routines */ int mtdparts_init(void); int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); int find_dev_and_part(const char *id, struct mtd_device **dev, diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 565257c..2646ae9 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -330,154 +330,231 @@ static int onenand_dump(struct mtd_info *mtd, ulong off, int only_oob) return 0; } -int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +static int do_onenand_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - struct onenand_chip *this; - int blocksize; + printf("%s\n", mtd->name); + return 0; +} + +static int do_onenand_bad(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong ofs; + + mtd = &onenand_mtd; + /* Currently only one OneNAND device is supported */ + printf("\nDevice %d bad blocks:\n", 0); + for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) { + if (mtd->block_isbad(mtd, ofs)) + printf(" %08x\n", (u32)ofs); + } + + return 0; +} + +static int do_onenand_read(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char *s; + int oob = 0; ulong addr, ofs; - size_t len, retlen = 0; + size_t len; int ret = 0; - char *cmd, *s; + size_t retlen = 0; - mtd = &onenand_mtd; - this = mtd->priv; - blocksize = (1 << this->erase_shift); + if (argc < 3) + { + cmd_usage(cmdtp); + return 1; + } - cmd = argv[1]; + s = strchr(argv[0], '.'); + if ((s != NULL) && (!strcmp(s, ".oob"))) + oob = 1; - switch (argc) { - case 0: - case 1: - goto usage; + addr = (ulong)simple_strtoul(argv[1], NULL, 16); - case 2: - if (strcmp(cmd, "info") == 0) { - printf("%s\n", mtd->name); - return 0; - } + printf("\nOneNAND read: "); + if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0) + return 1; - if (strcmp(cmd, "bad") == 0) { - /* Currently only one OneNAND device is supported */ - printf("\nDevice %d bad blocks:\n", 0); - for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) { - if (mtd->block_isbad(mtd, ofs)) - printf(" %08x\n", (u32)ofs); - } + ret = onenand_block_read(ofs, len, &retlen, (u8 *)addr, oob); - return 0; - } + printf(" %d bytes read: %s\n", retlen, ret ? "ERROR" : "OK"); - default: - /* At least 4 args */ + return ret == 0 ? 0 : 1; +} - /* - * Syntax is: - * 0 1 2 3 4 - * onenand erase [force] [off size] - */ - if ((strcmp(cmd, "erase") == 0) || (strcmp(cmd, "test") == 0)) { - int force = argc > 2 && !strcmp("force", argv[2]); - int o = force ? 3 : 2; - int erase; +static int do_onenand_write(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, ofs; + size_t len; + int ret = 0; + size_t retlen = 0; - erase = strcmp(cmd, "erase") == 0; /* 1 = erase, 0 = test */ - printf("\nOneNAND %s: ", erase ? "erase" : "test"); + if (argc < 3) + { + cmd_usage(cmdtp); + return 1; + } - /* skip first two or three arguments, look for offset and size */ - if (arg_off_size(argc - o, argv + o, &ofs, &len) != 0) - return 1; + addr = (ulong)simple_strtoul(argv[1], NULL, 16); + + printf("\nOneNAND write: "); + if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0) + return 1; - if (erase) - ret = onenand_block_erase(ofs, len, force); - else - ret = onenand_block_test(ofs, len); + ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr); - printf("%s\n", ret ? "ERROR" : "OK"); + printf(" %d bytes written: %s\n", retlen, ret ? "ERROR" : "OK"); - return ret == 0 ? 0 : 1; + return ret == 0 ? 0 : 1; +} + +static int do_onenand_erase(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong ofs; + int ret = 0; + size_t len; + int force; + + /* + * Syntax is: + * 0 1 2 3 4 + * onenand erase [force] [off size] + */ + argc--; + argv++; + if (argc) + { + if (!strcmp("force", argv[0])) + { + force = 1; + argc--; + argv++; } + } + printf("\nOneNAND erase: "); - if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { - int read; - int oob = 0; + /* skip first two or three arguments, look for offset and size */ + if (arg_off_size(argc, argv, &ofs, &len) != 0) + return 1; - if (argc < 4) - goto usage; + ret = onenand_block_erase(ofs, len, force); - addr = (ulong)simple_strtoul(argv[2], NULL, 16); + printf("%s\n", ret ? "ERROR" : "OK"); - read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ - printf("\nOneNAND %s: ", read ? "read" : "write"); - if (arg_off_size(argc - 3, argv + 3, &ofs, &len) != 0) - return 1; + return ret == 0 ? 0 : 1; +} - s = strchr(cmd, '.'); - if ((s != NULL) && (!strcmp(s, ".oob"))) - oob = 1; +static int do_onenand_test(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong ofs; + int ret = 0; + size_t len; - if (read) { - ret = onenand_block_read(ofs, len, &retlen, - (u8 *)addr, oob); - } else { - ret = onenand_block_write(ofs, len, &retlen, - (u8 *)addr); - } + /* + * Syntax is: + * 0 1 2 3 4 + * onenand test [force] [off size] + */ - printf(" %d bytes %s: %s\n", retlen, - read ? "read" : "written", ret ? "ERROR" : "OK"); + printf("\nOneNAND test: "); - return ret == 0 ? 0 : 1; - } + /* skip first two or three arguments, look for offset and size */ + if (arg_off_size(argc - 1, argv + 1, &ofs, &len) != 0) + return 1; - if (strcmp(cmd, "markbad") == 0) { - argc -= 2; - argv += 2; - - if (argc <= 0) - goto usage; - - while (argc > 0) { - addr = simple_strtoul(*argv, NULL, 16); - - if (mtd->block_markbad(mtd, addr)) { - printf("block 0x%08lx NOT marked " - "as bad! ERROR %d\n", - addr, ret); - ret = 1; - } else { - printf("block 0x%08lx successfully " - "marked as bad\n", - addr); - } - --argc; - ++argv; - } - return ret; - } + ret = onenand_block_test(ofs, len); - if (strncmp(cmd, "dump", 4) == 0) { - if (argc < 3) - goto usage; + printf("%s\n", ret ? "ERROR" : "OK"); - s = strchr(cmd, '.'); - ofs = (int)simple_strtoul(argv[2], NULL, 16); + return ret == 0 ? 0 : 1; +} - if (s != NULL && strcmp(s, ".oob") == 0) - ret = onenand_dump(mtd, ofs, 1); - else - ret = onenand_dump(mtd, ofs, 0); +static int do_onenand_dump(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong ofs; + int ret = 0; + char *s; - return ret == 0 ? 1 : 0; - } + if (argc < 2) + { + cmd_usage(cmdtp); + return 1; + } + + s = strchr(argv[0], '.'); + ofs = (int)simple_strtoul(argv[1], NULL, 16); + + if (s != NULL && strcmp(s, ".oob") == 0) + ret = onenand_dump(mtd, ofs, 1); + else + ret = onenand_dump(mtd, ofs, 0); - break; + return ret == 0 ? 1 : 0; +} + +static int do_onenand_markbad(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int ret = 0; + ulong addr; + + argc -= 2; + argv += 2; + + if (argc <= 0) + { + cmd_usage(cmdtp); + return 1; } - return 0; + while (argc > 0) { + addr = simple_strtoul(*argv, NULL, 16); + + if (mtd->block_markbad(mtd, addr)) { + printf("block 0x%08lx NOT marked " + "as bad! ERROR %d\n", + addr, ret); + ret = 1; + } else { + printf("block 0x%08lx successfully " + "marked as bad\n", + addr); + } + --argc; + ++argv; + } + return ret; +} + +static cmd_tbl_t cmd_onenand_sub[] = { + U_BOOT_CMD_MKENT(info, 1, 0, do_onenand_info, "", ""), + U_BOOT_CMD_MKENT(bad, 1, 0, do_onenand_bad, "", ""), + U_BOOT_CMD_MKENT(read, 4, 0, do_onenand_read, "", ""), + U_BOOT_CMD_MKENT(write, 4, 0, do_onenand_write, "", ""), + U_BOOT_CMD_MKENT(erase, 3, 0, do_onenand_erase, "", ""), + U_BOOT_CMD_MKENT(test, 3, 0, do_onenand_test, "", ""), + U_BOOT_CMD_MKENT(dump, 2, 0, do_onenand_dump, "", ""), + U_BOOT_CMD_MKENT(markbad, CONFIG_SYS_MAXARGS, 0, do_onenand_markbad, "", ""), +}; + +static int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + cmd_tbl_t *c; + + mtd = &onenand_mtd; + + /* Strip off leading 'onenand' command argument */ + argc--; + argv++; -usage: - cmd_usage(cmdtp); - return 1; + c = find_cmd_tbl(argv[0], &cmd_onenand_sub[0], ARRAY_SIZE(cmd_onenand_sub)); + + if (c) { + return c->cmd(cmdtp, flag, argc, argv); + } else { + cmd_usage(cmdtp); + return 1; + } } U_BOOT_CMD( @@ -486,7 +563,7 @@ U_BOOT_CMD( "info - show available OneNAND devices\n" "onenand bad - show bad blocks\n" "onenand read[.oob] addr off size\n" - "onenand write[.oob] addr off size\n" + "onenand write addr off size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" "onenand erase [force] [off size] - erase 'size' bytes from\n" diff --git a/common/cmd_usb.c b/common/cmd_usb.c index ee3755c..fcb5f76 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -516,6 +516,11 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) block_dev_desc_t *stor_dev; #endif + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + if ((strncmp(argv[1], "reset", 5) == 0) || (strncmp(argv[1], "start", 5) == 0)) { usb_stop(); diff --git a/common/command.c b/common/command.c index 0c66b7a..67ad692 100644 --- a/common/command.c +++ b/common/command.c @@ -188,6 +188,9 @@ static void install_auto_complete_handler(const char *cmd, void install_auto_complete(void) { +#if defined(CONFIG_CMD_EDITENV) + install_auto_complete_handler("editenv", var_complete); +#endif install_auto_complete_handler("printenv", var_complete); install_auto_complete_handler("setenv", var_complete); #if defined(CONFIG_CMD_RUN) diff --git a/common/ddr_spd.c b/common/ddr_spd.c index c058e4f..a7a30de 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -20,11 +20,15 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) * Check SPD revision supported * Rev 1.2 or less supported by this code */ - if (spd_rev > 0x12) { + if (spd_rev >= 0x20) { printf("SPD revision %02X not supported by this code\n", spd_rev); return 1; } + if (spd_rev > 0x13) { + printf("SPD revision %02X not verified by this code\n", + spd_rev); + } /* * Calculate checksum diff --git a/common/image.c b/common/image.c index 9e49713..8d4be14 100644 --- a/common/image.c +++ b/common/image.c @@ -450,6 +450,9 @@ phys_size_t getenv_bootm_size(void) void memmove_wd (void *to, void *from, size_t len, ulong chunksz) { + if (to == from) + return; + #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) while (len > 0) { size_t tail = (len > chunksz) ? chunksz : len; diff --git a/common/serial.c b/common/serial.c index 0682faa..fceabfa 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void) #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \ - || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ + || defined(CONFIG_SYS_SC520) #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; @@ -64,9 +64,17 @@ HOSTSTRIP = strip # ifeq ($(HOSTOS),darwin) -HOSTCC = cc -HOSTCFLAGS += -traditional-cpp -HOSTLDFLAGS += -multiply_defined suppress +# get major and minor product version (e.g. '10' and '6' for Snow Leopard) +DARWIN_MAJOR_VERSION = $(shell sw_vers -productVersion | cut -f 1 -d '.') +DARWIN_MINOR_VERSION = $(shell sw_vers -productVersion | cut -f 2 -d '.') + +before-snow-leopard = $(shell if [ $(DARWIN_MAJOR_VERSION) -le 10 -a \ + $(DARWIN_MINOR_VERSION) -le 5 ] ; then echo "$(1)"; else echo "$(2)"; fi ;) + +# Snow Leopards build environment has no longer restrictions as described above +HOSTCC = $(call before-snow-leopard, "cc", "gcc") +HOSTCFLAGS += $(call before-snow-leopard, "-traditional-cpp") +HOSTLDFLAGS += $(call before-snow-leopard, "-multiply_defined suppress") else HOSTCC = gcc endif diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND index 2b3326b..5018ae8 100644 --- a/doc/README.JFFS2_NAND +++ b/doc/README.JFFS2_NAND @@ -5,7 +5,7 @@ To ebable, use the following #define in the board configuration file: #define CONFIG_JFFS2_NAND 1 Configuration of partitions is similar to how this is done in U-Boot -for JFFS2 on top NOR flash. If a single parition is used, it can be +for JFFS2 on top NOR flash. If a single partition is used, it can be configured using the following #defines in the configuration file: #define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ diff --git a/doc/README.drivers.eth b/doc/README.drivers.eth index d0c3571..eb83038 100644 --- a/doc/README.drivers.eth +++ b/doc/README.drivers.eth @@ -70,6 +70,7 @@ int ape_register(bd_t *bis, int iobase) dev->halt = ape_halt; dev->send = ape_send; dev->recv = ape_recv; + dev->write_hwaddr = ape_write_hwaddr; eth_register(dev); @@ -102,11 +103,12 @@ not checking its state or doing random probing. ----------- Now that we've registered with the ethernet layer, we can start getting some -real work done. You will need four functions: +real work done. You will need five functions: int ape_init(struct eth_device *dev, bd_t *bis); int ape_send(struct eth_device *dev, volatile void *packet, int length); int ape_recv(struct eth_device *dev); int ape_halt(struct eth_device *dev); + int ape_write_hwaddr(struct eth_device *dev); The init function checks the hardware (probing/identifying) and gets it ready for send/recv operations. You often do things here such as resetting the MAC @@ -150,6 +152,9 @@ The halt function should turn off / disable the hardware and place it back in its reset state. It can be called at any time (before any call to the related init function), so make sure it can handle this sort of thing. +The write_hwaddr function should program the MAC address stored in dev->enetaddr +into the Ethernet controller. + So the call graph at this stage would look something like: some net operation (ping / tftp / whatever...) eth_init() diff --git a/doc/README.enetaddr b/doc/README.enetaddr index 94d800a..2d8e24f 100644 --- a/doc/README.enetaddr +++ b/doc/README.enetaddr @@ -33,11 +33,13 @@ Correct flow of setting up the MAC address (summarized): 1. Read from hardware in initialize() function 2. Read from environment in net/eth.c after initialize() 3. Give priority to the value in the environment if a conflict -4. Program hardware in the device's init() function. +4. Program the address into hardware if the following conditions are met: + a) The relevant driver has a 'write_addr' function + b) The user hasn't set an 'ethmacskip' environment variable + c) The address is valid (unicast, not all-zeros) -If somebody wants to subvert the design philosophy, this can be done -in the board-specific board_eth_init() function by calling eth_init() -after all the NICs have been registered. +Previous behavior had the MAC address always being programmed into hardware +in the device's init() function. ------- Usage diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 8878560..4b97a0e 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright (C) 2008,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * This program is free software; you can redistribute it and/or @@ -22,6 +22,7 @@ #include <command.h> #include <asm/io.h> #include <asm/processor.h> +#include <asm/fsl_serdes.h> #include <malloc.h> #include <libata.h> #include <fis.h> @@ -129,6 +130,17 @@ int init_sata(int dev) return -1; } +#ifdef CONFIG_MPC85xx + if ((dev == 0) && (!is_serdes_configured(SATA1))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } + if ((dev == 1) && (!is_serdes_configured(SATA2))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } +#endif + /* Allocate SATA device driver struct */ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t)); if (!sata) { diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index 73a78d2..b3a04d3 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -1,7 +1,7 @@ /* * i2c.c - driver for Blackfin on-chip TWI/I2C * - * Copyright (c) 2006-2008 Analog Devices Inc. + * Copyright (c) 2006-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -12,6 +12,35 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/twi.h> +/* Every register is 32bit aligned, but only 16bits in size */ +#define ureg(name) u16 name; u16 __pad_##name; +struct twi_regs { + ureg(clkdiv); + ureg(control); + ureg(slave_ctl); + ureg(slave_stat); + ureg(slave_addr); + ureg(master_ctl); + ureg(master_stat); + ureg(master_addr); + ureg(int_stat); + ureg(int_mask); + ureg(fifo_ctl); + ureg(fifo_stat); + char __pad[0x50]; + ureg(xmt_data8); + ureg(xmt_data16); + ureg(rcv_data8); + ureg(rcv_data16); +}; +#undef ureg + +/* U-Boot I2C framework allows only one active device at a time. */ +#ifdef TWI_CLKDIV +#define TWI0_CLKDIV TWI_CLKDIV +#endif +static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV; + #ifdef DEBUG # define dmemset(s, c, n) memset(s, c, n) #else @@ -19,29 +48,10 @@ #endif #define debugi(fmt, args...) \ debug( \ - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \ - "%-20s:%-3i: " fmt "\n", \ - bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \ + "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ + twi->master_stat, twi->fifo_stat, twi->int_stat, \ __func__, __LINE__, ## args) -#ifdef TWI0_CLKDIV -#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) -#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val) -#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) -#define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val) -#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8() -#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT() -#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val) -#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT() -#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val) -#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL() -#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val) -#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val) -#endif - #ifdef CONFIG_TWICLK_KHZ # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED #endif @@ -87,49 +97,48 @@ static int wait_for_completion(struct i2c_msg *msg) ulong timebase = get_timer(0); do { - int_stat = bfin_read_TWI_INT_STAT(); + int_stat = twi->int_stat; if (int_stat & XMTSERV) { debugi("processing XMTSERV"); - bfin_write_TWI_INT_STAT(XMTSERV); + twi->int_stat = XMTSERV; SSYNC(); if (msg->alen) { - bfin_write_TWI_XMT_DATA8(*(msg->abuf++)); + twi->xmt_data8 = *(msg->abuf++); --msg->alen; } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - bfin_write_TWI_XMT_DATA8(*(msg->buf++)); + twi->xmt_data8 = *(msg->buf++); --msg->len; } else { - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | - (msg->flags & I2C_M_COMBO ? RSTART | MDIR : STOP)); + twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP; SSYNC(); } } if (int_stat & RCVSERV) { debugi("processing RCVSERV"); - bfin_write_TWI_INT_STAT(RCVSERV); + twi->int_stat = RCVSERV; SSYNC(); if (msg->len) { - *(msg->buf++) = bfin_read_TWI_RCV_DATA8(); + *(msg->buf++) = twi->rcv_data8; --msg->len; } else if (msg->flags & I2C_M_STOP) { - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | STOP); + twi->master_ctl |= STOP; SSYNC(); } } if (int_stat & MERR) { debugi("processing MERR"); - bfin_write_TWI_INT_STAT(MERR); + twi->int_stat = MERR; SSYNC(); return msg->len; } if (int_stat & MCOMP) { debugi("processing MCOMP"); - bfin_write_TWI_INT_STAT(MCOMP); + twi->int_stat = MCOMP; SSYNC(); if (msg->flags & I2C_M_COMBO && msg->len) { - bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR); + twi->master_ctl = (twi->master_ctl & ~RSTART) | + (min(msg->len, 0xff) << 6) | MEN | MDIR; SSYNC(); } else break; @@ -172,55 +181,54 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); /* wait for things to settle */ - while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) + while (twi->master_stat & BUSBUSY) if (ctrlc()) return 1; /* Set Transmit device address */ - bfin_write_TWI_MASTER_ADDR(chip); + twi->master_addr = chip; /* Clear the FIFO before starting things */ - bfin_write_TWI_FIFO_CTL(XMTFLUSH | RCVFLUSH); + twi->fifo_ctl = XMTFLUSH | RCVFLUSH; SSYNC(); - bfin_write_TWI_FIFO_CTL(0); + twi->fifo_ctl = 0; SSYNC(); /* prime the pump */ if (msg.alen) { len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; debugi("first byte=0x%02x", *msg.abuf); - bfin_write_TWI_XMT_DATA8(*(msg.abuf++)); + twi->xmt_data8 = *(msg.abuf++); --msg.alen; } else if (!(msg.flags & I2C_M_READ) && msg.len) { debugi("first byte=0x%02x", *msg.buf); - bfin_write_TWI_XMT_DATA8(*(msg.buf++)); + twi->xmt_data8 = *(msg.buf++); --msg.len; } /* clear int stat */ - bfin_write_TWI_MASTER_STAT(-1); - bfin_write_TWI_INT_STAT(-1); - bfin_write_TWI_INT_MASK(0); + twi->master_stat = -1; + twi->int_stat = -1; + twi->int_mask = 0; SSYNC(); /* Master enable */ - bfin_write_TWI_MASTER_CTL( - (bfin_read_TWI_MASTER_CTL() & FAST) | + twi->master_ctl = + (twi->master_ctl & FAST) | (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0) - ); + ((msg.flags & I2C_M_READ) ? MDIR : 0); SSYNC(); - debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL()); + debugi("CTL=0x%04x", twi->master_ctl); /* process the rest */ ret = wait_for_completion(&msg); debugi("ret=%d", ret); if (ret) { - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN); - bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA); + twi->master_ctl &= ~MEN; + twi->control &= ~TWI_ENA; SSYNC(); - bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); + twi->control |= TWI_ENA; SSYNC(); } @@ -238,10 +246,10 @@ int i2c_set_bus_speed(unsigned int speed) /* Set TWI interface clock */ if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) return -1; - bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff)); + twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff); /* Don't turn it on */ - bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + twi->master_ctl = (speed > 100000 ? FAST : 0); return 0; } @@ -253,7 +261,7 @@ int i2c_set_bus_speed(unsigned int speed) unsigned int i2c_get_bus_speed(void) { /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff); + return 5000000 / (twi->clkdiv & 0xff); } /** @@ -269,24 +277,23 @@ void i2c_init(int speed, int slaveaddr) uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; /* Set TWI internal clock as 10MHz */ - bfin_write_TWI_CONTROL(prescale); + twi->control = prescale; /* Set TWI interface clock as specified */ i2c_set_bus_speed(speed); /* Enable it */ - bfin_write_TWI_CONTROL(TWI_ENA | prescale); + twi->control = TWI_ENA | prescale; SSYNC(); - debugi("CONTROL:0x%04x CLKDIV:0x%04x", - bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV()); + debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv); #if CONFIG_SYS_I2C_SLAVE # error I2C slave support not tested/supported /* If they want us as a slave, do it */ if (slaveaddr) { - bfin_write_TWI_SLAVE_ADDR(slaveaddr); - bfin_write_TWI_SLAVE_CTL(SEN); + twi->slave_addr = slaveaddr; + twi->slave_ctl = SEN; } #endif } @@ -329,3 +336,43 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { return i2c_transfer(chip, addr, alen, buffer, len, 0); } + +/** + * i2c_set_bus_num - change active I2C bus + * @bus: bus index, zero based + * @returns: 0 on success, non-0 on failure + */ +int i2c_set_bus_num(unsigned int bus) +{ + switch (bus) { +#if CONFIG_SYS_MAX_I2C_BUS > 0 + case 0: twi = (void *)TWI0_CLKDIV; return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case 1: twi = (void *)TWI1_CLKDIV; return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case 2: twi = (void *)TWI2_CLKDIV; return 0; +#endif + default: return -1; + } +} + +/** + * i2c_get_bus_num - returns index of active I2C bus + */ +unsigned int i2c_get_bus_num(void) +{ + switch ((unsigned long)twi) { +#if CONFIG_SYS_MAX_I2C_BUS > 0 + case TWI0_CLKDIV: return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case TWI1_CLKDIV: return 1; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case TWI2_CLKDIV: return 2; +#endif + default: return -1; + } +} diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a9b07a9..a368fe6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -103,7 +103,7 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) /* * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. */ -static int +static void esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) { struct fsl_esdhc *regs = mmc->priv; @@ -125,7 +125,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) && --timeout); if (timeout <= 0) { printf("\nData Read Failed in PIO Mode."); - return timeout; + return; } while (size && (!(irqstat & IRQSTAT_TC))) { udelay(100); /* Wait before last byte transfer complete */ @@ -139,7 +139,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) } } else { blocks = data->blocks; - buffer = data->src; + buffer = (char *)data->src; while (blocks) { timeout = PIO_TIMEOUT; size = data->blocksize; @@ -148,7 +148,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) && --timeout); if (timeout <= 0) { printf("\nData Write Failed in PIO Mode."); - return timeout; + return; } while (size && (!(irqstat & IRQSTAT_TC))) { udelay(100); /* Wait before last byte transfer complete */ @@ -166,22 +166,12 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) { - uint wml_value; int timeout; struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO + uint wml_value; -#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO - if (!(data->flags & MMC_DATA_READ)) { - if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. " - "Can not write to a locked card.\n\n"); - return TIMEOUT; - } - esdhc_write32(®s->dsaddr, (u32)data->src); - } else - esdhc_write32(®s->dsaddr, (u32)data->dest); -#else wml_value = data->blocksize/4; if (data->flags & MMC_DATA_READ) { @@ -202,7 +192,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value << 16); esdhc_write32(®s->dsaddr, (u32)data->src); } -#endif +#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ + if (!(data->flags & MMC_DATA_READ)) { + if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { + printf("\nThe SD card is locked. " + "Can not write to a locked card.\n\n"); + return TIMEOUT; + } + esdhc_write32(®s->dsaddr, (u32)data->src); + } else + esdhc_write32(®s->dsaddr, (u32)data->dest); +#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 2f9a5e3..88b867a 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -696,8 +696,13 @@ static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk) list_add_tail(&wrk->list, &ubi->works); ubi_assert(ubi->works_count >= 0); ubi->works_count += 1; - if (ubi->thread_enabled) - wake_up_process(ubi->bgt_thread); + + /* + * U-Boot special: We have no bgt_thread in U-Boot! + * So just call do_work() here directly. + */ + do_work(ubi); + spin_unlock(&ubi->wl_lock); } diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ec0ba1..b75c02f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o @@ -39,6 +40,7 @@ COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o +COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c new file mode 100644 index 0000000..5c0c274 --- /dev/null +++ b/drivers/net/altera_tse.c @@ -0,0 +1,942 @@ +/* + * Altera 10/100/1000 triple speed ethernet mac driver + * + * Copyright (C) 2008 Altera Corporation. + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <command.h> +#include <asm/cache.h> +#include <asm/dma-mapping.h> +#include <miiphy.h> +#include "altera_tse.h" + +/* sgdma debug - print descriptor */ +static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc) +{ + debug("SGDMA DEBUG :\n"); + debug("desc->source : 0x%x \n", (unsigned int)desc->source); + debug("desc->destination : 0x%x \n", (unsigned int)desc->destination); + debug("desc->next : 0x%x \n", (unsigned int)desc->next); + debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad); + debug("desc->destination_pad : 0x%x \n", + (unsigned int)desc->destination_pad); + debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad); + debug("desc->bytes_to_transfer : 0x%x \n", + (unsigned int)desc->bytes_to_transfer); + debug("desc->actual_bytes_transferred : 0x%x \n", + (unsigned int)desc->actual_bytes_transferred); + debug("desc->descriptor_status : 0x%x \n", + (unsigned int)desc->descriptor_status); + debug("desc->descriptor_control : 0x%x \n", + (unsigned int)desc->descriptor_control); +} + +/* This is a generic routine that the SGDMA mode-specific routines + * call to populate a descriptor. + * arg1 :pointer to first SGDMA descriptor. + * arg2 :pointer to next SGDMA descriptor. + * arg3 :Address to where data to be written. + * arg4 :Address from where data to be read. + * arg5 :no of byte to transaction. + * arg6 :variable indicating to generate start of packet or not + * arg7 :read fixed + * arg8 :write fixed + * arg9 :read burst + * arg10 :write burst + * arg11 :atlantic_channel number + */ +static void alt_sgdma_construct_descriptor_burst( + volatile struct alt_sgdma_descriptor *desc, + volatile struct alt_sgdma_descriptor *next, + unsigned int *read_addr, + unsigned int *write_addr, + unsigned short length_or_eop, + int generate_eop, + int read_fixed, + int write_fixed_or_sop, + int read_burst, + int write_burst, + unsigned char atlantic_channel) +{ + /* + * Mark the "next" descriptor as "not" owned by hardware. This prevents + * The SGDMA controller from continuing to process the chain. This is + * done as a single IO write to bypass cache, without flushing + * the entire descriptor, since only the 8-bit descriptor status must + * be flushed. + */ + if (!next) + debug("Next descriptor not defined!!\n"); + + next->descriptor_control = (next->descriptor_control & + ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK); + + desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF); + desc->destination = + (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF); + desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF); + desc->source_pad = 0x0; + desc->destination_pad = 0x0; + desc->next_pad = 0x0; + desc->bytes_to_transfer = length_or_eop; + desc->actual_bytes_transferred = 0; + desc->descriptor_status = 0x0; + + /* SGDMA burst not currently supported */ + desc->read_burst = 0; + desc->write_burst = 0; + + /* + * Set the descriptor control block as follows: + * - Set "owned by hardware" bit + * - Optionally set "generate EOP" bit + * - Optionally set the "read from fixed address" bit + * - Optionally set the "write to fixed address bit (which serves + * serves as a "generate SOP" control bit in memory-to-stream mode). + * - Set the 4-bit atlantic channel, if specified + * + * Note this step is performed after all other descriptor information + * has been filled out so that, if the controller already happens to be + * pointing at this descriptor, it will not run (via the "owned by + * hardware" bit) until all other descriptor has been set up. + */ + + desc->descriptor_control = + ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) | + (generate_eop ? + ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) | + (read_fixed ? + ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) | + (write_fixed_or_sop ? + ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) | + (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0) + ); +} + +static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev, + volatile struct alt_sgdma_descriptor *desc) +{ + unsigned int status; + int counter = 0; + + /* Wait for any pending transfers to complete */ + alt_sgdma_print_desc(desc); + status = dev->status; + + counter = 0; + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + debug("Timeout waiting sgdma in do sync!\n"); + + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + dev->status = 0xFF; + + /* Point the controller at the descriptor */ + dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; + debug("next desc in sgdma 0x%x\n", + (unsigned int)dev->next_descriptor_pointer); + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | + ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); + + /* Wait for the descriptor (chain) to complete */ + status = dev->status; + debug("wait for sgdma...."); + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) + ; + debug("done\n"); + + /* Clear Run */ + dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK)); + + /* Get & clear status register contents */ + status = dev->status; + dev->status = 0xFF; + + /* we really should check if the transfer completes properly */ + debug("tx sgdma status = 0x%x", status); + return 0; +} + +static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, + volatile struct alt_sgdma_descriptor *desc) +{ + unsigned int status; + int counter = 0; + + /* Wait for any pending transfers to complete */ + alt_sgdma_print_desc(desc); + status = dev->status; + + counter = 0; + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + debug("Timeout waiting sgdma in do async!\n"); + + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + dev->status = 0xFF; + + /* Point the controller at the descriptor */ + dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | + ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); + + /* we really should check if the transfer completes properly */ + return 0; +} + +/* u-boot interface */ +static int tse_adjust_link(struct altera_tse_priv *priv) +{ + unsigned int refvar; + + refvar = priv->mac_dev->command_config.image; + + if (!(priv->duplexity)) + refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; + else + refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; + + switch (priv->speed) { + case 1000: + refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 100: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 10: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar |= ALTERA_TSE_CMD_ENA_10_MSK; + break; + } + priv->mac_dev->command_config.image = refvar; + + return 0; +} + +static int tse_eth_send(struct eth_device *dev, + volatile void *packet, int length) +{ + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + volatile struct alt_sgdma_descriptor *tx_desc = + (volatile struct alt_sgdma_descriptor *)priv->tx_desc; + + volatile struct alt_sgdma_descriptor *tx_desc_cur = + (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; + + flush_dcache((unsigned long)packet, length); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&tx_desc[0], + (volatile struct alt_sgdma_descriptor *)&tx_desc[1], + (unsigned int *)packet, /* read addr */ + (unsigned int *)0, + length, /* length or EOP ,will change for each tx */ + 0x1, /* gen eop */ + 0x0, /* read fixed */ + 0x1, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length); + + /* send the packet */ + debug("sending packet\n"); + alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur); + debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred); + return tx_desc_cur->actual_bytes_transferred; +} + +static int tse_eth_rx(struct eth_device *dev) +{ + int packet_length = 0; + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_sgdma_descriptor *rx_desc = + (volatile struct alt_sgdma_descriptor *)priv->rx_desc; + volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0]; + + if (rx_desc_cur->descriptor_status & + ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { + debug("got packet\n"); + packet_length = rx_desc->actual_bytes_transferred; + NetReceive(NetRxPackets[0], packet_length); + + /* start descriptor again */ + flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&rx_desc[0], + (volatile struct alt_sgdma_descriptor *)&rx_desc[1], + (unsigned int)0x0, /* read addr */ + (unsigned int *)NetRxPackets[0], + 0x0, /* length or EOP */ + 0x0, /* gen eop */ + 0x0, /* read fixed */ + 0x0, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + + /* setup the sgdma */ + alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); + } + + return -1; +} + +static void tse_eth_halt(struct eth_device *dev) +{ + /* don't do anything! */ + /* this gets called after each uboot */ + /* network command. don't need to reset the thing all of the time */ +} + +static void tse_eth_reset(struct eth_device *dev) +{ + /* stop sgdmas, disable tse receive */ + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_tse_mac *mac_dev = priv->mac_dev; + volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; + volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + int counter; + volatile struct alt_sgdma_descriptor *rx_desc = + (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0]; + + /* clear rx desc & wait for sgdma to complete */ + rx_desc->descriptor_control = 0; + rx_sgdma->control = 0; + counter = 0; + while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { + debug("Timeout waiting for rx sgdma!\n"); + rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + } + + counter = 0; + tx_sgdma->control = 0; + while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { + debug("Timeout waiting for tx sgdma!\n"); + tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + } + /* reset the mac */ + mac_dev->command_config.bits.transmit_enable = 1; + mac_dev->command_config.bits.receive_enable = 1; + mac_dev->command_config.bits.software_reset = 1; + + counter = 0; + while (mac_dev->command_config.bits.software_reset) { + if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR) + debug("TSEMAC SW reset bit never cleared!\n"); +} + +static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum) +{ + volatile struct alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + unsigned int data; + u16 value; + + mac_dev = priv->mac_dev; + + /* set mdio address */ + mac_dev->mdio_phy1_addr = priv->phyaddr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + /* get the data */ + data = mdio_regs[regnum]; + + value = data & 0xffff; + + return value; +} + +static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, + unsigned int value) +{ + volatile struct alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + unsigned int data; + + mac_dev = priv->mac_dev; + + /* set mdio address */ + mac_dev->mdio_phy1_addr = priv->phyaddr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + /* get the data */ + data = (unsigned int)value; + + mdio_regs[regnum] = data; + + return 0; +} + +/* MDIO access to phy */ +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) +static int altera_tse_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev; + struct altera_tse_priv *priv; + dev = eth_get_dev_by_name(devname); + priv = dev->priv; + + tse_mdio_write(priv, (uint) reg, (uint) value); + + return 0; +} + +static int altera_tse_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev; + struct altera_tse_priv *priv; + volatile struct alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + + dev = eth_get_dev_by_name(devname); + priv = dev->priv; + + mac_dev = priv->mac_dev; + mac_dev->mdio_phy1_addr = (int)addr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + *value = 0xffff & mdio_regs[reg]; + + return 0; + +} +#endif + +/* + * Also copied from tsec.c + */ +/* Parse the status register for link, and then do + * auto-negotiation + */ +static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) +{ + /* + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) + */ + mii_reg = tse_mdio_read(priv, MIIM_STATUS); + + if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) + && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + int i = 0; + + puts("Waiting for PHY auto negotiation to complete"); + while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + priv->link = 0; + return 0; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); /* 1 ms */ + mii_reg = tse_mdio_read(priv, MIIM_STATUS); + } + puts(" done\n"); + priv->link = 1; + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_STATUS_LINK) { + debug("Link is up\n"); + priv->link = 1; + } else { + debug("Link is down\n"); + priv->link = 0; + } + } + + return 0; +} + +/* Parse the 88E1011's status register for speed and duplex + * information + */ +static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint speed; + + mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); + + if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ == 1000) == 0) { + i = 0; + puts("."); + } + udelay(1000); /* 1 ms */ + mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) + priv->link = 1; + else + priv->link = 0; + } + + if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); + + switch (speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + debug("PHY Speed is 1000Mbit\n"); + break; + case MIIM_88E1011_PHYSTAT_100: + debug("PHY Speed is 100Mbit\n"); + priv->speed = 100; + break; + default: + debug("PHY Speed is 10Mbit\n"); + priv->speed = 10; + } + + return 0; +} + +static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint mii_data = tse_mdio_read(priv, mii_reg); + mii_data &= 0xfff0; + mii_data |= 0xb; + return mii_data; +} + +static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint mii_data = tse_mdio_read(priv, mii_reg); + mii_data &= ~0x82; + mii_data |= 0x82; + return mii_data; +} + +/* + * Returns which value to write to the control register. + * For 10/100, the value is slightly different + */ +static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv) +{ + return MIIM_CONTROL_INIT; +} + +/* + * PHY & MDIO code + * Need to add SGMII stuff + * + */ + +static struct phy_info phy_info_M88E1111S = { + 0x01410cc, + "Marvell 88E1111S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_88E1111_PHY_EXT_SR, 0x848f, + &mii_m88e1111s_setmode_sr}, + /* Delay RGMII TX and RX */ + {MIIM_88E1111_PHY_EXT_CR, 0x0cd2, + &mii_m88e1111s_setmode_cr}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, +}; + +/* a generic flavor. */ +static struct phy_info phy_info_generic = { + 0, + "Unknown/Generic PHY", + 32, + (struct phy_cmd[]){ /* config */ + {PHY_BMCR, PHY_BMCR_RESET, NULL}, + {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + {PHY_BMSR, miim_read, NULL}, + {PHY_BMSR, miim_read, &mii_parse_sr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + } +}; + +static struct phy_info *phy_info[] = { + &phy_info_M88E1111S, + NULL +}; + + /* Grab the identifier of the device's PHY, and search through + * all of the known PHYs to see if one matches. If so, return + * it, if not, return NULL + */ +static struct phy_info *get_phy_info(struct eth_device *dev) +{ + struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; + uint phy_reg, phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = tse_mdio_read(priv, MIIM_PHYIR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = tse_mdio_read(priv, MIIM_PHYIR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for (i = 0; phy_info[i]; i++) { + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { + theInfo = phy_info[i]; + break; + } + } + + if (theInfo == NULL) { + theInfo = &phy_info_generic; + debug("%s: No support for PHY id %x; assuming generic\n", + dev->name, phy_ID); + } else + debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); + + return theInfo; +} + +/* Execute the given series of commands on the given device's + * PHY, running functions as necessary + */ +static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd) +{ + int i; + uint result; + + for (i = 0; cmd->mii_reg != miim_end; i++) { + if (cmd->mii_data == miim_read) { + result = tse_mdio_read(priv, cmd->mii_reg); + + if (cmd->funct != NULL) + (*(cmd->funct)) (result, priv); + + } else { + if (cmd->funct != NULL) + result = (*(cmd->funct)) (cmd->mii_reg, priv); + else + result = cmd->mii_data; + + tse_mdio_write(priv, cmd->mii_reg, result); + + } + cmd++; + } +} + +/* Phy init code */ +static int init_phy(struct eth_device *dev) +{ + struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; + struct phy_info *curphy; + + /* Get the cmd structure corresponding to the attached + * PHY */ + curphy = get_phy_info(dev); + + if (curphy == NULL) { + priv->phyinfo = NULL; + debug("%s: No PHY found\n", dev->name); + + return 0; + } else + debug("%s found\n", curphy->name); + priv->phyinfo = curphy; + + phy_run_commands(priv, priv->phyinfo->config); + + return 1; +} + +static int tse_set_mac_address(struct eth_device *dev) +{ + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_tse_mac *mac_dev = priv->mac_dev; + + debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n", + dev->enetaddr[5], dev->enetaddr[4], + dev->enetaddr[3], dev->enetaddr[2], + dev->enetaddr[1], dev->enetaddr[0]); + mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | + (dev->enetaddr[2]) << 16 | + (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); + + mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | + (dev->enetaddr[4])) & 0xFFFF); + + /* Set the MAC address */ + mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; + return 0; +} + +static int tse_eth_init(struct eth_device *dev, bd_t * bd) +{ + int dat; + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_tse_mac *mac_dev = priv->mac_dev; + volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; + volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; + volatile struct alt_sgdma_descriptor *rx_desc_cur = + (volatile struct alt_sgdma_descriptor *)&rx_desc[0]; + + /* stop controller */ + debug("Reseting TSE & SGDMAs\n"); + tse_eth_reset(dev); + + /* start the phy */ + debug("Configuring PHY\n"); + phy_run_commands(priv, priv->phyinfo->startup); + + /* need to create sgdma */ + debug("Configuring tx desc\n"); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&tx_desc[0], + (volatile struct alt_sgdma_descriptor *)&tx_desc[1], + (unsigned int *)NULL, /* read addr */ + (unsigned int *)0, + 0, /* length or EOP ,will change for each tx */ + 0x1, /* gen eop */ + 0x0, /* read fixed */ + 0x1, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + debug("Configuring rx desc\n"); + flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&rx_desc[0], + (volatile struct alt_sgdma_descriptor *)&rx_desc[1], + (unsigned int)0x0, /* read addr */ + (unsigned int *)NetRxPackets[0], + 0x0, /* length or EOP */ + 0x0, /* gen eop */ + 0x0, /* read fixed */ + 0x0, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + /* start rx async transfer */ + debug("Starting rx sgdma\n"); + alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur); + + /* start TSE */ + debug("Configuring TSE Mac\n"); + /* Initialize MAC registers */ + mac_dev->max_frame_length = PKTSIZE_ALIGN; + mac_dev->rx_almost_empty_threshold = 8; + mac_dev->rx_almost_full_threshold = 8; + mac_dev->tx_almost_empty_threshold = 8; + mac_dev->tx_almost_full_threshold = 3; + mac_dev->tx_sel_empty_threshold = + CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; + mac_dev->tx_sel_full_threshold = 0; + mac_dev->rx_sel_empty_threshold = + CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; + mac_dev->rx_sel_full_threshold = 0; + + /* NO Shift */ + mac_dev->rx_cmd_stat.bits.rx_shift16 = 0; + mac_dev->tx_cmd_stat.bits.tx_shift16 = 0; + + /* enable MAC */ + dat = 0; + dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; + + mac_dev->command_config.image = dat; + + /* configure the TSE core */ + /* -- output clocks, */ + /* -- and later config stuff for SGMII */ + if (priv->link) { + debug("Adjusting TSE to link speed\n"); + tse_adjust_link(priv); + } + + return priv->link ? 0 : -1; +} + +/* TSE init code */ +int altera_tse_initialize(u8 dev_num, int mac_base, + int sgdma_rx_base, int sgdma_tx_base) +{ + struct altera_tse_priv *priv; + struct eth_device *dev; + struct alt_sgdma_descriptor *rx_desc; + struct alt_sgdma_descriptor *tx_desc; + unsigned long dma_handle; + + dev = (struct eth_device *)malloc(sizeof *dev); + + if (NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + priv = malloc(sizeof(*priv)); + + if (!priv) { + free(dev); + return 0; + } + tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), + &dma_handle); + rx_desc = tx_desc + 2; + debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); + debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc); + + if (!tx_desc) { + free(priv); + free(dev); + return 0; + } + memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); + memset(tx_desc, 0, (sizeof *tx_desc) * 2); + + /* initialize tse priv */ + priv->mac_dev = (volatile struct alt_tse_mac *)mac_base; + priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base; + priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base; + priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR; + priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS; + priv->rx_desc = rx_desc; + priv->tx_desc = tx_desc; + + /* init eth structure */ + dev->priv = priv; + dev->init = tse_eth_init; + dev->halt = tse_eth_halt; + dev->send = tse_eth_send; + dev->recv = tse_eth_rx; + dev->write_hwaddr = tse_set_mac_address; + sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) + miiphy_register(dev->name, altera_tse_miiphy_read, + altera_tse_miiphy_write); +#endif + + init_phy(dev); + + return 1; +} diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h new file mode 100644 index 0000000..c1cb79e --- /dev/null +++ b/drivers/net/altera_tse.h @@ -0,0 +1,494 @@ +/* + * Altera 10/100/1000 triple speed ethernet mac + * + * Copyright (C) 2008 Altera Corporation. + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ALTERA_TSE_H_ +#define _ALTERA_TSE_H_ + +#define __packed_1_ __attribute__ ((packed, aligned(1))) + +/* PHY Stuff */ +#define miim_end -2 +#define miim_read -1 + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ + +#ifndef CONFIG_SYS_TBIPA_VALUE +#define CONFIG_SYS_TBIPA_VALUE 0x1f +#endif +#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET 0x80000000 + +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +#define MIIM_CONTROL 0x00 +#define MIIM_CONTROL_RESET 0x00009140 +#define MIIM_CONTROL_INIT 0x00001140 +#define MIIM_CONTROL_RESTART 0x00001340 +#define MIIM_ANEN 0x00001000 + +#define MIIM_CR 0x00 +#define MIIM_CR_RST 0x00008000 +#define MIIM_CR_INIT 0x00001000 + +#define MIIM_STATUS 0x1 +#define MIIM_STATUS_AN_DONE 0x00000020 +#define MIIM_STATUS_LINK 0x0004 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_AUTN_COMP 0x0020 + +#define MIIM_PHYIR1 0x2 +#define MIIM_PHYIR2 0x3 + +#define MIIM_ANAR 0x4 +#define MIIM_ANAR_INIT 0x1e1 + +#define MIIM_TBI_ANLPBPA 0x5 +#define MIIM_TBI_ANLPBPA_HALF 0x00000040 +#define MIIM_TBI_ANLPBPA_FULL 0x00000020 + +#define MIIM_TBI_ANEX 0x6 +#define MIIM_TBI_ANEX_NP 0x00000004 +#define MIIM_TBI_ANEX_PRX 0x00000002 + +#define MIIM_GBIT_CONTROL 0x9 +#define MIIM_GBIT_CONTROL_INIT 0xe00 + +#define MIIM_EXT_PAGE_ACCESS 0x1f + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1011_PHY_STATUS 0x11 +#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1011_PHYSTAT_100 0x4000 +#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1011_PHYSTAT_LINK 0x0400 + +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +#define MIIM_88E1111_PHY_EXT_CR 0x14 +#define MIIM_88E1111_PHY_EXT_SR 0x1b + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +#define MIIM_READ_COMMAND 0x00000001 + +/* struct phy_info: a structure which defines attributes for a PHY + * id will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be shifted right by "shift" bits to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + * The struct phy_cmd entries represent pointers to an arrays of + * commands which tell the driver what to do to the PHY. + */ +struct phy_info { + uint id; + char *name; + uint shift; + /* Called to configure the PHY, and modify the controller + * based on the results */ + struct phy_cmd *config; + + /* Called when starting up the controller */ + struct phy_cmd *startup; + + /* Called when bringing down the controller */ + struct phy_cmd *shutdown; +}; + +/* SGDMA Stuff */ +#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) +#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) +#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) +#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) +#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) + +#define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001) +#define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002) +#define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004) +#define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008) +#define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010) +#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) +#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) +#define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080) +#define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00) +#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) +#define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000) +#define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000) + +#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ + | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ + | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) + +/* + * Descriptor control bit masks & offsets + * + * Note: The control byte physically occupies bits [31:24] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the control register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) + +/* + * Descriptor status bit masks & offsets + * + * Note: The status byte physically occupies bits [23:16] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the status register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) +#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) +#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) + +/* + * The SGDMA controller buffer descriptor allocates + * 64 bits for each address. To support ANSI C, the + * struct implementing a descriptor places 32-bits + * of padding directly above each address; each pad must + * be cleared when initializing a descriptor. + */ + +/* + * Buffer Descriptor data structure + * + */ +struct alt_sgdma_descriptor { + unsigned int *source; /* the address of data to be read. */ + unsigned int source_pad; + + unsigned int *destination; /* the address to write data */ + unsigned int destination_pad; + + unsigned int *next; /* the next descriptor in the list. */ + unsigned int next_pad; + + unsigned short bytes_to_transfer; /* the number of bytes to transfer */ + unsigned char read_burst; + unsigned char write_burst; + + unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ + unsigned char descriptor_status; + unsigned char descriptor_control; + +} __packed_1_; + +/* SG-DMA Control/Status Slave registers map */ + +struct alt_sgdma_registers { + unsigned int status; + unsigned int status_pad[3]; + unsigned int control; + unsigned int control_pad[3]; + unsigned int next_descriptor_pointer; + unsigned int descriptor_pad[3]; +}; + +/* TSE Stuff */ +#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) +#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) +#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) +#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) +#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) +#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) +#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) +#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) +#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) +#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) +#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) +#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) +#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) +#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) +#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) +#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) +/* Bits (18:16) = address select */ +#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) +#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) +#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) +#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) +#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) +#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) +#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) +#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) +#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) +/* Bits (30..27) reserved */ +#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) + +#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) +#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) + +#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) + +#define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000 +#define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000 + +/* Command_Config Register Bit Definitions */ + +typedef volatile union __alt_tse_command_config { + unsigned int image; + struct { + unsigned int + transmit_enable:1, /* bit 0 */ + receive_enable:1, /* bit 1 */ + pause_frame_xon_gen:1, /* bit 2 */ + ethernet_speed:1, /* bit 3 */ + promiscuous_enable:1, /* bit 4 */ + pad_enable:1, /* bit 5 */ + crc_forward:1, /* bit 6 */ + pause_frame_forward:1, /* bit 7 */ + pause_frame_ignore:1, /* bit 8 */ + set_mac_address_on_tx:1, /* bit 9 */ + halfduplex_enable:1, /* bit 10 */ + excessive_collision:1, /* bit 11 */ + late_collision:1, /* bit 12 */ + software_reset:1, /* bit 13 */ + multicast_hash_mode_sel:1, /* bit 14 */ + loopback_enable:1, /* bit 15 */ + src_mac_addr_sel_on_tx:3, /* bit 18:16 */ + magic_packet_detect:1, /* bit 19 */ + sleep_mode_enable:1, /* bit 20 */ + wake_up_request:1, /* bit 21 */ + pause_frame_xoff_gen:1, /* bit 22 */ + control_frame_enable:1, /* bit 23 */ + payload_len_chk_disable:1, /* bit 24 */ + enable_10mbps_intf:1, /* bit 25 */ + rx_error_discard_enable:1, /* bit 26 */ + reserved_bits:4, /* bit 30:27 */ + self_clear_counter_reset:1; /* bit 31 */ + } __packed_1_ bits; +} __packed_1_ alt_tse_command_config; + +/* Tx_Cmd_Stat Register Bit Definitions */ + +typedef volatile union __alt_tse_tx_cmd_stat { + unsigned int image; + struct { + unsigned int reserved_lsbs:17, /* bit 16:0 */ + omit_crc:1, /* bit 17 */ + tx_shift16:1, /* bit 18 */ + reserved_msbs:13; /* bit 31:19 */ + + } __packed_1_ bits; +} alt_tse_tx_cmd_stat; + +/* Rx_Cmd_Stat Register Bit Definitions */ + +typedef volatile union __alt_tse_rx_cmd_stat { + unsigned int image; + struct { + unsigned int reserved_lsbs:25, /* bit 24:0 */ + rx_shift16:1, /* bit 25 */ + reserved_msbs:6; /* bit 31:26 */ + + } __packed_1_ bits; +} alt_tse_rx_cmd_stat; + +struct alt_tse_mdio { + unsigned int control; /*PHY device operation control register */ + unsigned int status; /*PHY device operation status register */ + unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */ + unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */ + unsigned int auto_negotiation_advertisement; + unsigned int remote_partner_base_page_ability; + + unsigned int reg6; + unsigned int reg7; + unsigned int reg8; + unsigned int reg9; + unsigned int rega; + unsigned int regb; + unsigned int regc; + unsigned int regd; + unsigned int rege; + unsigned int regf; + unsigned int reg10; + unsigned int reg11; + unsigned int reg12; + unsigned int reg13; + unsigned int reg14; + unsigned int reg15; + unsigned int reg16; + unsigned int reg17; + unsigned int reg18; + unsigned int reg19; + unsigned int reg1a; + unsigned int reg1b; + unsigned int reg1c; + unsigned int reg1d; + unsigned int reg1e; + unsigned int reg1f; +}; + +/* MAC register Space */ + +struct alt_tse_mac { + unsigned int megacore_revision; + unsigned int scratch_pad; + alt_tse_command_config command_config; + unsigned int mac_addr_0; + unsigned int mac_addr_1; + unsigned int max_frame_length; + unsigned int pause_quanta; + unsigned int rx_sel_empty_threshold; + unsigned int rx_sel_full_threshold; + unsigned int tx_sel_empty_threshold; + unsigned int tx_sel_full_threshold; + unsigned int rx_almost_empty_threshold; + unsigned int rx_almost_full_threshold; + unsigned int tx_almost_empty_threshold; + unsigned int tx_almost_full_threshold; + unsigned int mdio_phy0_addr; + unsigned int mdio_phy1_addr; + + /* only if 100/1000 BaseX PCS, reserved otherwise */ + unsigned int reservedx44[5]; + + unsigned int reg_read_access_status; + unsigned int min_tx_ipg_length; + + /* IEEE 802.3 oEntity Managed Object Support */ + unsigned int aMACID_1; /*The MAC addresses */ + unsigned int aMACID_2; + unsigned int aFramesTransmittedOK; + unsigned int aFramesReceivedOK; + unsigned int aFramesCheckSequenceErrors; + unsigned int aAlignmentErrors; + unsigned int aOctetsTransmittedOK; + unsigned int aOctetsReceivedOK; + + /* IEEE 802.3 oPausedEntity Managed Object Support */ + unsigned int aTxPAUSEMACCtrlFrames; + unsigned int aRxPAUSEMACCtrlFrames; + + /* IETF MIB (MIB-II) Object Support */ + unsigned int ifInErrors; + unsigned int ifOutErrors; + unsigned int ifInUcastPkts; + unsigned int ifInMulticastPkts; + unsigned int ifInBroadcastPkts; + unsigned int ifOutDiscards; + unsigned int ifOutUcastPkts; + unsigned int ifOutMulticastPkts; + unsigned int ifOutBroadcastPkts; + + /* IETF RMON MIB Object Support */ + unsigned int etherStatsDropEvent; + unsigned int etherStatsOctets; + unsigned int etherStatsPkts; + unsigned int etherStatsUndersizePkts; + unsigned int etherStatsOversizePkts; + unsigned int etherStatsPkts64Octets; + unsigned int etherStatsPkts65to127Octets; + unsigned int etherStatsPkts128to255Octets; + unsigned int etherStatsPkts256to511Octets; + unsigned int etherStatsPkts512to1023Octets; + unsigned int etherStatsPkts1024to1518Octets; + + unsigned int etherStatsPkts1519toXOctets; + unsigned int etherStatsJabbers; + unsigned int etherStatsFragments; + + unsigned int reservedxE4; + + /*FIFO control register. */ + alt_tse_tx_cmd_stat tx_cmd_stat; + alt_tse_rx_cmd_stat rx_cmd_stat; + + unsigned int ipaccTxConf; + unsigned int ipaccRxConf; + unsigned int ipaccRxStat; + unsigned int ipaccRxStatSum; + + /*Multicast address resolution table */ + unsigned int hash_table[64]; + + /*Registers 0 to 31 within PHY device 0/1 */ + struct alt_tse_mdio mdio_phy0; + struct alt_tse_mdio mdio_phy1; + + /*4 Supplemental MAC Addresses */ + unsigned int supp_mac_addr_0_0; + unsigned int supp_mac_addr_0_1; + unsigned int supp_mac_addr_1_0; + unsigned int supp_mac_addr_1_1; + unsigned int supp_mac_addr_2_0; + unsigned int supp_mac_addr_2_1; + unsigned int supp_mac_addr_3_0; + unsigned int supp_mac_addr_3_1; + + unsigned int reservedx320[56]; +}; + +/* flags: TSE MII modes */ +/* GMII/MII = 0 */ +/* RGMII = 1 */ +/* RGMII_ID = 2 */ +/* RGMII_TXID = 3 */ +/* RGMII_RXID = 4 */ +/* SGMII = 5 */ +struct altera_tse_priv { + char devname[16]; + volatile struct alt_tse_mac *mac_dev; + volatile struct alt_sgdma_registers *sgdma_rx; + volatile struct alt_sgdma_registers *sgdma_tx; + unsigned int rx_sgdma_irq; + unsigned int tx_sgdma_irq; + unsigned int has_descriptor_mem; + unsigned int descriptor_mem_base; + unsigned int descriptor_mem_size; + volatile struct alt_sgdma_descriptor *rx_desc; + volatile struct alt_sgdma_descriptor *tx_desc; + volatile unsigned char *rx_buf; + struct phy_info *phyinfo; + unsigned int phyaddr; + unsigned int flags; + unsigned int link; + unsigned int duplexity; + unsigned int speed; +}; + +/* Phy stuff continued */ +/* + * struct phy_cmd: A command for reading or writing a PHY register + * + * mii_reg: The register to read or write + * + * mii_data: For writes, the value to put in the register. + * A value of -1 indicates this is a read. + * + * funct: A function pointer which is invoked for each command. + * For reads, this function will be passed the value read + * from the PHY, and process it. + * For writes, the result of this function will be written + * to the PHY register + */ +struct phy_cmd { + uint mii_reg; + uint mii_data; + uint(*funct) (uint mii_reg, struct altera_tse_priv *priv); +}; +#endif /* _ALTERA_TSE_H_ */ diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index ec45b63..720e126 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -106,6 +106,7 @@ int bfin_EMAC_initialize(bd_t *bis) dev->halt = bfin_EMAC_halt; dev->send = bfin_EMAC_send; dev->recv = bfin_EMAC_recv; + dev->write_hwaddr = bfin_EMAC_setup_addr; eth_register(dev); @@ -303,6 +304,19 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) return 0; } +static int bfin_EMAC_setup_addr(struct eth_device *dev) +{ + *pEMAC_ADDRLO = + dev->enetaddr[0] | + dev->enetaddr[1] << 8 | + dev->enetaddr[2] << 16 | + dev->enetaddr[3] << 24; + *pEMAC_ADDRHI = + dev->enetaddr[4] | + dev->enetaddr[5] << 8; + return 0; +} + static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) { u32 opmode; @@ -318,7 +332,7 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) return -1; /* Initialize EMAC address */ - bfin_EMAC_setup_addr(dev->enetaddr); + bfin_EMAC_setup_addr(dev); /* Initialize TX and RX buffer */ for (i = 0; i < PKTBUFSRX; i++) { @@ -376,18 +390,6 @@ static void bfin_EMAC_halt(struct eth_device *dev) } -void bfin_EMAC_setup_addr(uchar *enetaddr) -{ - *pEMAC_ADDRLO = - enetaddr[0] | - enetaddr[1] << 8 | - enetaddr[2] << 16 | - enetaddr[3] << 24; - *pEMAC_ADDRHI = - enetaddr[4] | - enetaddr[5] << 8; -} - ADI_ETHER_BUFFER *SetupRxBuffer(int no) { ADI_ETHER_FRAME_BUFFER *frmbuf; diff --git a/drivers/net/bfin_mac.h b/drivers/net/bfin_mac.h index 8f467a3..c731c17 100644 --- a/drivers/net/bfin_mac.h +++ b/drivers/net/bfin_mac.h @@ -60,7 +60,6 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd); static void bfin_EMAC_halt(struct eth_device *dev); static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length); static int bfin_EMAC_recv(struct eth_device *dev); - -void bfin_EMAC_setup_addr(uchar *enetaddr); +static int bfin_EMAC_setup_addr(struct eth_device *dev); #endif diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index a7fef56..137e41f 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -117,12 +117,12 @@ static void DM9000_iow(int reg, u8 value); /* DM9000 network board routine ---------------------------- */ -#define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) -#define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) -#define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) -#define DM9000_inb(r) (*(volatile u8 *)r) -#define DM9000_inw(r) (*(volatile u16 *)r) -#define DM9000_inl(r) (*(volatile u32 *)r) +#define DM9000_outb(d,r) writeb(d, r) +#define DM9000_outw(d,r) writew(d, r) +#define DM9000_outl(d,r) writel(d, r) +#define DM9000_inb(r) readb(r) +#define DM9000_inw(r) readw(r) +#define DM9000_inl(r) readl(r) #ifdef CONFIG_DM9000_DEBUG static void diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c new file mode 100644 index 0000000..34cc47f --- /dev/null +++ b/drivers/net/ethoc.c @@ -0,0 +1,511 @@ +/* + * Opencore 10/100 ethernet mac driver + * + * Copyright (C) 2007-2008 Avionic Design Development GmbH + * Copyright (C) 2008-2009 Avionic Design GmbH + * Thierry Reding <thierry.reding@avionic-design.de> + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <net.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/cache.h> + +/* register offsets */ +#define MODER 0x00 +#define INT_SOURCE 0x04 +#define INT_MASK 0x08 +#define IPGT 0x0c +#define IPGR1 0x10 +#define IPGR2 0x14 +#define PACKETLEN 0x18 +#define COLLCONF 0x1c +#define TX_BD_NUM 0x20 +#define CTRLMODER 0x24 +#define MIIMODER 0x28 +#define MIICOMMAND 0x2c +#define MIIADDRESS 0x30 +#define MIITX_DATA 0x34 +#define MIIRX_DATA 0x38 +#define MIISTATUS 0x3c +#define MAC_ADDR0 0x40 +#define MAC_ADDR1 0x44 +#define ETH_HASH0 0x48 +#define ETH_HASH1 0x4c +#define ETH_TXCTRL 0x50 + +/* mode register */ +#define MODER_RXEN (1 << 0) /* receive enable */ +#define MODER_TXEN (1 << 1) /* transmit enable */ +#define MODER_NOPRE (1 << 2) /* no preamble */ +#define MODER_BRO (1 << 3) /* broadcast address */ +#define MODER_IAM (1 << 4) /* individual address mode */ +#define MODER_PRO (1 << 5) /* promiscuous mode */ +#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ +#define MODER_LOOP (1 << 7) /* loopback */ +#define MODER_NBO (1 << 8) /* no back-off */ +#define MODER_EDE (1 << 9) /* excess defer enable */ +#define MODER_FULLD (1 << 10) /* full duplex */ +#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ +#define MODER_DCRC (1 << 12) /* delayed CRC enable */ +#define MODER_CRC (1 << 13) /* CRC enable */ +#define MODER_HUGE (1 << 14) /* huge packets enable */ +#define MODER_PAD (1 << 15) /* padding enabled */ +#define MODER_RSM (1 << 16) /* receive small packets */ + +/* interrupt source and mask registers */ +#define INT_MASK_TXF (1 << 0) /* transmit frame */ +#define INT_MASK_TXE (1 << 1) /* transmit error */ +#define INT_MASK_RXF (1 << 2) /* receive frame */ +#define INT_MASK_RXE (1 << 3) /* receive error */ +#define INT_MASK_BUSY (1 << 4) +#define INT_MASK_TXC (1 << 5) /* transmit control frame */ +#define INT_MASK_RXC (1 << 6) /* receive control frame */ + +#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) +#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) + +#define INT_MASK_ALL ( \ + INT_MASK_TXF | INT_MASK_TXE | \ + INT_MASK_RXF | INT_MASK_RXE | \ + INT_MASK_TXC | INT_MASK_RXC | \ + INT_MASK_BUSY \ + ) + +/* packet length register */ +#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) +#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) +#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ + PACKETLEN_MAX(max)) + +/* transmit buffer number register */ +#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) + +/* control module mode register */ +#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ +#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ +#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ + +/* MII mode register */ +#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ +#define MIIMODER_NOPRE (1 << 8) /* no preamble */ + +/* MII command register */ +#define MIICOMMAND_SCAN (1 << 0) /* scan status */ +#define MIICOMMAND_READ (1 << 1) /* read status */ +#define MIICOMMAND_WRITE (1 << 2) /* write control data */ + +/* MII address register */ +#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) +#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) +#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ + MIIADDRESS_RGAD(reg)) + +/* MII transmit data register */ +#define MIITX_DATA_VAL(x) ((x) & 0xffff) + +/* MII receive data register */ +#define MIIRX_DATA_VAL(x) ((x) & 0xffff) + +/* MII status register */ +#define MIISTATUS_LINKFAIL (1 << 0) +#define MIISTATUS_BUSY (1 << 1) +#define MIISTATUS_INVALID (1 << 2) + +/* TX buffer descriptor */ +#define TX_BD_CS (1 << 0) /* carrier sense lost */ +#define TX_BD_DF (1 << 1) /* defer indication */ +#define TX_BD_LC (1 << 2) /* late collision */ +#define TX_BD_RL (1 << 3) /* retransmission limit */ +#define TX_BD_RETRY_MASK (0x00f0) +#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) +#define TX_BD_UR (1 << 8) /* transmitter underrun */ +#define TX_BD_CRC (1 << 11) /* TX CRC enable */ +#define TX_BD_PAD (1 << 12) /* pad enable */ +#define TX_BD_WRAP (1 << 13) +#define TX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define TX_BD_READY (1 << 15) /* TX buffer ready */ +#define TX_BD_LEN(x) (((x) & 0xffff) << 16) +#define TX_BD_LEN_MASK (0xffff << 16) + +#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ + TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) + +/* RX buffer descriptor */ +#define RX_BD_LC (1 << 0) /* late collision */ +#define RX_BD_CRC (1 << 1) /* RX CRC error */ +#define RX_BD_SF (1 << 2) /* short frame */ +#define RX_BD_TL (1 << 3) /* too long */ +#define RX_BD_DN (1 << 4) /* dribble nibble */ +#define RX_BD_IS (1 << 5) /* invalid symbol */ +#define RX_BD_OR (1 << 6) /* receiver overrun */ +#define RX_BD_MISS (1 << 7) +#define RX_BD_CF (1 << 8) /* control frame */ +#define RX_BD_WRAP (1 << 13) +#define RX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define RX_BD_EMPTY (1 << 15) +#define RX_BD_LEN(x) (((x) & 0xffff) << 16) + +#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ + RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) + +#define ETHOC_BUFSIZ 1536 +#define ETHOC_ZLEN 64 +#define ETHOC_BD_BASE 0x400 +#define ETHOC_TIMEOUT (HZ / 2) +#define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) + +/** + * struct ethoc - driver-private device structure + * @num_tx: number of send buffers + * @cur_tx: last send buffer written + * @dty_tx: last buffer actually sent + * @num_rx: number of receive buffers + * @cur_rx: current receive buffer + */ +struct ethoc { + u32 num_tx; + u32 cur_tx; + u32 dty_tx; + u32 num_rx; + u32 cur_rx; +}; + +/** + * struct ethoc_bd - buffer descriptor + * @stat: buffer statistics + * @addr: physical memory address + */ +struct ethoc_bd { + u32 stat; + u32 addr; +}; + +static inline u32 ethoc_read(struct eth_device *dev, loff_t offset) +{ + return readl(dev->iobase + offset); +} + +static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data) +{ + writel(data, dev->iobase + offset); +} + +static inline void ethoc_read_bd(struct eth_device *dev, int index, + struct ethoc_bd *bd) +{ + loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + bd->stat = ethoc_read(dev, offset + 0); + bd->addr = ethoc_read(dev, offset + 4); +} + +static inline void ethoc_write_bd(struct eth_device *dev, int index, + const struct ethoc_bd *bd) +{ + loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + ethoc_write(dev, offset + 0, bd->stat); + ethoc_write(dev, offset + 4, bd->addr); +} + +static int ethoc_set_mac_address(struct eth_device *dev) +{ + u8 *mac = dev->enetaddr; + + ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | + (mac[4] << 8) | (mac[5] << 0)); + ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); + return 0; +} + +static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask) +{ + ethoc_write(dev, INT_SOURCE, mask); +} + +static inline void ethoc_enable_rx_and_tx(struct eth_device *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode |= MODER_RXEN | MODER_TXEN; + ethoc_write(dev, MODER, mode); +} + +static inline void ethoc_disable_rx_and_tx(struct eth_device *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode &= ~(MODER_RXEN | MODER_TXEN); + ethoc_write(dev, MODER, mode); +} + +static int ethoc_init_ring(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + struct ethoc_bd bd; + int i; + + priv->cur_tx = 0; + priv->dty_tx = 0; + priv->cur_rx = 0; + + /* setup transmission buffers */ + bd.stat = TX_BD_IRQ | TX_BD_CRC; + + for (i = 0; i < priv->num_tx; i++) { + if (i == priv->num_tx - 1) + bd.stat |= TX_BD_WRAP; + + ethoc_write_bd(dev, i, &bd); + } + + bd.stat = RX_BD_EMPTY | RX_BD_IRQ; + + for (i = 0; i < priv->num_rx; i++) { + bd.addr = (u32)NetRxPackets[i]; + if (i == priv->num_rx - 1) + bd.stat |= RX_BD_WRAP; + + flush_dcache(bd.addr, PKTSIZE_ALIGN); + ethoc_write_bd(dev, priv->num_tx + i, &bd); + } + + return 0; +} + +static int ethoc_reset(struct eth_device *dev) +{ + u32 mode; + + /* TODO: reset controller? */ + + ethoc_disable_rx_and_tx(dev); + + /* TODO: setup registers */ + + /* enable FCS generation and automatic padding */ + mode = ethoc_read(dev, MODER); + mode |= MODER_CRC | MODER_PAD; + ethoc_write(dev, MODER, mode); + + /* set full-duplex mode */ + mode = ethoc_read(dev, MODER); + mode |= MODER_FULLD; + ethoc_write(dev, MODER, mode); + ethoc_write(dev, IPGT, 0x15); + + ethoc_ack_irq(dev, INT_MASK_ALL); + ethoc_enable_rx_and_tx(dev); + return 0; +} + +static int ethoc_init(struct eth_device *dev, bd_t * bd) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + printf("ethoc\n"); + + priv->num_tx = 1; + priv->num_rx = PKTBUFSRX; + ethoc_write(dev, TX_BD_NUM, priv->num_tx); + ethoc_init_ring(dev); + ethoc_reset(dev); + + return 0; +} + +static int ethoc_update_rx_stats(struct ethoc_bd *bd) +{ + int ret = 0; + + if (bd->stat & RX_BD_TL) { + debug("ETHOC: " "RX: frame too long\n"); + ret++; + } + + if (bd->stat & RX_BD_SF) { + debug("ETHOC: " "RX: frame too short\n"); + ret++; + } + + if (bd->stat & RX_BD_DN) + debug("ETHOC: " "RX: dribble nibble\n"); + + if (bd->stat & RX_BD_CRC) { + debug("ETHOC: " "RX: wrong CRC\n"); + ret++; + } + + if (bd->stat & RX_BD_OR) { + debug("ETHOC: " "RX: overrun\n"); + ret++; + } + + if (bd->stat & RX_BD_LC) { + debug("ETHOC: " "RX: late collision\n"); + ret++; + } + + return ret; +} + +static int ethoc_rx(struct eth_device *dev, int limit) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + int count; + + for (count = 0; count < limit; ++count) { + u32 entry; + struct ethoc_bd bd; + + entry = priv->num_tx + (priv->cur_rx % priv->num_rx); + ethoc_read_bd(dev, entry, &bd); + if (bd.stat & RX_BD_EMPTY) + break; + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->cur_rx, bd.stat); + if (ethoc_update_rx_stats(&bd) == 0) { + int size = bd.stat >> 16; + size -= 4; /* strip the CRC */ + NetReceive((void *)bd.addr, size); + } + + /* clear the buffer descriptor so it can be reused */ + flush_dcache(bd.addr, PKTSIZE_ALIGN); + bd.stat &= ~RX_BD_STATS; + bd.stat |= RX_BD_EMPTY; + ethoc_write_bd(dev, entry, &bd); + priv->cur_rx++; + } + + return count; +} + +static int ethoc_update_tx_stats(struct ethoc_bd *bd) +{ + if (bd->stat & TX_BD_LC) + debug("ETHOC: " "TX: late collision\n"); + + if (bd->stat & TX_BD_RL) + debug("ETHOC: " "TX: retransmit limit\n"); + + if (bd->stat & TX_BD_UR) + debug("ETHOC: " "TX: underrun\n"); + + if (bd->stat & TX_BD_CS) + debug("ETHOC: " "TX: carrier sense lost\n"); + + return 0; +} + +static void ethoc_tx(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + u32 entry = priv->dty_tx % priv->num_tx; + struct ethoc_bd bd; + + ethoc_read_bd(dev, entry, &bd); + if ((bd.stat & TX_BD_READY) == 0) + (void)ethoc_update_tx_stats(&bd); +} + +static int ethoc_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + struct ethoc_bd bd; + u32 entry; + u32 pending; + int tmo; + + entry = priv->cur_tx % priv->num_tx; + ethoc_read_bd(dev, entry, &bd); + if (unlikely(length < ETHOC_ZLEN)) + bd.stat |= TX_BD_PAD; + else + bd.stat &= ~TX_BD_PAD; + bd.addr = (u32)packet; + + flush_dcache(bd.addr, length); + bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); + bd.stat |= TX_BD_LEN(length); + ethoc_write_bd(dev, entry, &bd); + + /* start transmit */ + bd.stat |= TX_BD_READY; + ethoc_write_bd(dev, entry, &bd); + + /* wait for transfer to succeed */ + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while (1) { + pending = ethoc_read(dev, INT_SOURCE); + ethoc_ack_irq(dev, pending & ~INT_MASK_RX); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + + if (pending & INT_MASK_TX) { + ethoc_tx(dev); + break; + } + if (get_timer(0) >= tmo) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + return 0; +} + +static void ethoc_halt(struct eth_device *dev) +{ + ethoc_disable_rx_and_tx(dev); +} + +static int ethoc_recv(struct eth_device *dev) +{ + u32 pending; + + pending = ethoc_read(dev, INT_SOURCE); + ethoc_ack_irq(dev, pending); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + if (pending & INT_MASK_RX) { + debug("%s(): rx irq\n", __func__); + ethoc_rx(dev, PKTBUFSRX); + } + + return 0; +} + +int ethoc_initialize(u8 dev_num, int base_addr) +{ + struct ethoc *priv; + struct eth_device *dev; + + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; + } + + memset(dev, 0, sizeof(*dev)); + dev->priv = priv; + dev->iobase = base_addr; + dev->init = ethoc_init; + dev->halt = ethoc_halt; + dev->send = ethoc_send; + dev->recv = ethoc_recv; + dev->write_hwaddr = ethoc_set_mac_address; + sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); + + eth_register(dev); + return 1; +} diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 8c4ade5..57f89a3 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -314,9 +314,9 @@ static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) { /* * The MX27 can store the mac address in internal eeprom - * This mechanism is not supported now by MX51 + * This mechanism is not supported now by MX51 or MX25 */ -#ifdef CONFIG_MX51 +#if defined(CONFIG_MX51) || defined(CONFIG_MX25) return -1; #else struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; @@ -325,7 +325,7 @@ static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) for (i = 0; i < 6; i++) mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]); - return is_valid_ether_addr(mac); + return !is_valid_ether_addr(mac); #endif } @@ -505,7 +505,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) miiphy_restart_aneg(dev); fec_open(dev); - fec_set_hwaddr(dev); return 0; } @@ -713,6 +712,7 @@ static int fec_probe(bd_t *bd) edev->send = fec_send; edev->recv = fec_recv; edev->halt = fec_halt; + edev->write_hwaddr = fec_set_hwaddr; fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; fec->bd = bd; diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 2ad7fea..932792e 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -424,8 +424,6 @@ static int kwgbe_init(struct eth_device *dev) KWGBEREG_WR(regs->pxc, PRT_CFG_VAL); KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); - /* Disable port initially */ - KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); /* Assign port SDMA configuration */ KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); @@ -438,6 +436,9 @@ static int kwgbe_init(struct eth_device *dev) KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE | (KWGBEREG_RD(regs->psc0) & MRU_MASK)); + /* Enable port initially */ + KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); + /* * Set ethernet MTU for leaky bucket mechanism to 0 - this will * disable the leaky bucket mechanism . @@ -445,7 +446,7 @@ static int kwgbe_init(struct eth_device *dev) KWGBEREG_WR(regs->pmtu, 0); /* Assignment of Rx CRDB of given RXUQ */ - KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr); + KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr); /* Enable port Rx. */ KWGBEREG_WR(regs->rqc, (1 << RXUQ)); @@ -480,7 +481,7 @@ static int kwgbe_halt(struct eth_device *dev) stop_queue(®s->tqc); stop_queue(®s->rqc); - /* Enable port */ + /* Disable port */ KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN); /* Set port is not reset */ KWGBEREG_BITS_RESET(regs->psc1, 1 << 4); @@ -497,6 +498,16 @@ static int kwgbe_halt(struct eth_device *dev) return 0; } +static int kwgbe_write_hwaddr(struct eth_device *dev) +{ + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + + /* Programs net device MAC address after initialization */ + port_uc_addr_set(regs, dkwgbe->dev.enetaddr); + return 0; +} + static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, int datasize) { @@ -525,7 +536,7 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, p_txdesc->buf_ptr = (u8 *) p; p_txdesc->byte_cnt = datasize; - /* Apply send command using zeroth RXUQ */ + /* Apply send command using zeroth TXUQ */ KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); KWGBEREG_WR(regs->tqc, (1 << TXUQ)); @@ -606,7 +617,7 @@ static int kwgbe_recv(struct eth_device *dev) p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; p_rxdesc_curr->byte_cnt = 0; - writel((unsigned)p_rxdesc_curr->nxtdesc_p, &dkwgbe->p_rxdesc_curr); + writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr); return 0; } @@ -693,6 +704,7 @@ int kirkwood_egiga_initialize(bd_t * bis) dev->halt = (void *)kwgbe_halt; dev->send = (void *)kwgbe_send; dev->recv = (void *)kwgbe_recv; + dev->write_hwaddr = (void *)kwgbe_write_hwaddr; eth_register(dev); diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h index 16d5214..30c773c 100644 --- a/drivers/net/kirkwood_egiga.h +++ b/drivers/net/kirkwood_egiga.h @@ -418,7 +418,7 @@ struct kwgbe_registers { u32 pmtbs; u8 pad14[0x60c - 0x4ec - 4]; struct kwgbe_rxcdp rxcdp[7]; - u32 rxcdp7; + struct kwgbe_rxdesc *rxcdp7; u32 rqc; struct kwgbe_txdesc *tcsdp; u8 pad15[0x6c0 - 0x684 - 4]; diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 90e4002..810079f 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -795,7 +795,6 @@ int lan91c96_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return 0; } memset(dev, 0, sizeof(*dev)); diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 4acc29e..060bdd7 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -175,38 +175,39 @@ int mii_discover_phy(struct eth_device *dev) #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type\n", phytype, pass); #endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + if (phytype == 0xffff) + continue; + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); #ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d\n", phyno, pass); + printf("PHY @ 0x%x pass %d\n", phyno, pass); #endif - for (i = 0; i < (sizeof(phyinfo) / sizeof(phy_info_t)); i++) { - if (phyinfo[i].phyid == phytype) { + for (i = 0; (i < (sizeof(phyinfo) / sizeof(phy_info_t))) + && (phyinfo[i].phyid != 0); i++) { + if (phyinfo[i].phyid == phytype) { #ifdef ET_DEBUG - printf("phyid %x - %s\n", - phyinfo[i].phyid, - phyinfo[i].strid); + printf("phyid %x - %s\n", + phyinfo[i].phyid, + phyinfo[i].strid); #endif - strcpy(info->phy_name, phyinfo[i].strid); - info->phyname_init = 1; - found = 1; - break; - } + strcpy(info->phy_name, phyinfo[i].strid); + info->phyname_init = 1; + found = 1; + break; } + } - if (!found) { + if (!found) { #ifdef ET_DEBUG - printf("0x%08x\n", phytype); + printf("0x%08x\n", phytype); #endif - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; } } } diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index fb2c19a..c580c82 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2009 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Derived from the MPC8xx FEC driver. @@ -25,10 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; #error "CONFIG_MII has to be defined!" #endif -#if (DEBUG & 0x40) -static u32 local_crc32(char *string, unsigned int crc_value, int len); -#endif - int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); @@ -164,7 +160,7 @@ static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) } /********************************************************************/ -static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac) +static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac) { u8 currByte; /* byte for which to compute the CRC */ int byte; /* loop - counter */ @@ -230,6 +226,12 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) printf ("mpc512x_fec_init... Begin\n"); #endif + mpc512x_fec_set_hwaddr (fec, dev->enetaddr); + out_be32(&fec->eth->gaddr1, 0x00000000); + out_be32(&fec->eth->gaddr2, 0x00000000); + + mpc512x_fec_init_phy (dev, bis); + /* Set interrupt mask register */ out_be32(&fec->eth->imask, 0x00000000); @@ -615,8 +617,6 @@ int mpc512x_fec_initialize (bd_t * bis) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; mpc512x_fec_priv *fec; struct eth_device *dev; - int i; - char *tmp, *end, env_enetaddr[6]; void * bd; fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); @@ -667,25 +667,6 @@ int mpc512x_fec_initialize (bd_t * bis) */ out_be32(&fec->eth->ievent, 0xffffffff); - /* - * Try to set the mac address now. The fec mac address is - * a garbage after reset. When not using fec for booting - * the Linux fec driver will try to work with this garbage. - */ - tmp = getenv ("ethaddr"); - if (tmp) { - for (i=0; i<6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - mpc512x_fec_set_hwaddr (fec, env_enetaddr); - out_be32(&fec->eth->gaddr1, 0x00000000); - out_be32(&fec->eth->gaddr2, 0x00000000); - } - - mpc512x_fec_init_phy (dev, bis); - return 1; } @@ -775,39 +756,4 @@ int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) return 0; } -#if (DEBUG & 0x40) -static u32 local_crc32 (char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - /**/ return crc; -} -#endif /* DEBUG */ - #endif /* CONFIG_MPC512x_FEC */ diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index c2b1bbd..1681e26 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.c, @@ -28,10 +28,6 @@ static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); #endif /* DEBUG */ -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len); -#endif - typedef struct { uint8 data[1500]; /* actual data */ int length; /* actual length */ @@ -1019,38 +1015,3 @@ int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 dat return 0; } - -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - /**/ return crc; -} -#endif /* DEBUG */ diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index cac08d0..3da4c35 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -220,7 +220,7 @@ static int smc911x_rx(struct eth_device *dev) smc911x_reg_write(dev, RX_CFG, 0); - tmplen = (pktlen + 2+ 3) / 4; + tmplen = (pktlen + 3) / 4; while (tmplen--) *data++ = pkt_data_pull(dev, RX_DATA_FIFO); @@ -242,7 +242,6 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return -1; } memset(dev, 0, sizeof(*dev)); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index fd49eff..3e4c3bd 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1082,7 +1082,8 @@ static void tsec_halt(struct eth_device *dev) regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); - while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; + while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)) + != (IEVENT_GRSC | IEVENT_GTSC)) ; regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 27dc500..ccbf27d 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -595,8 +595,7 @@ static void phy_change(struct eth_device *dev) adjust_link(dev); } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ - && !defined(BITBANGMII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* * Find a device index from the devlist by name @@ -1388,8 +1387,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info) return err; } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ - && !defined(BITBANGMII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); #endif diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index fa48fea..3baffe4 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -93,6 +93,27 @@ static const struct fixed_phy_port fixed_phy_port[] = { CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ }; +/*--------------------------------------------------------------------+ + * BitBang MII support for ethernet ports + * + * Based from MPC8560ADS implementation + *--------------------------------------------------------------------*/ +/* + * Example board header file to define bitbang ethernet ports: + * + * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name, + * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("FSL UEC0") +*/ +#ifndef CONFIG_SYS_BITBANG_PHY_PORTS +#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */ +#endif + +#if defined(CONFIG_BITBANGMII) +static const char *bitbang_phy_port[] = { + CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */ +}; +#endif /* CONFIG_BITBANGMII */ + static void config_genmii_advert (struct uec_mii_info *mii_info); static void genmii_setup_forced (struct uec_mii_info *mii_info); static void genmii_restart_aneg (struct uec_mii_info *mii_info); @@ -113,6 +134,19 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; + +#if defined(CONFIG_BITBANGMII) + u32 i = 0; + + for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { + if (strncmp(dev->name, bitbang_phy_port[i], + sizeof(dev->name)) == 0) { + (void)bb_miiphy_write(NULL, mii_id, regnum, value); + return; + } + } +#endif /* CONFIG_BITBANGMII */ + ug_regs = ugeth->uec_mii_regs; /* Stop the MII management read cycle */ @@ -140,6 +174,19 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) u32 tmp_reg; u16 value; + +#if defined(CONFIG_BITBANGMII) + u32 i = 0; + + for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { + if (strncmp(dev->name, bitbang_phy_port[i], + sizeof(dev->name)) == 0) { + (void)bb_miiphy_read(NULL, mii_id, regnum, &value); + return (value); + } + } +#endif /* CONFIG_BITBANGMII */ + ug_regs = ugeth->uec_mii_regs; /* Setting up the MII Mangement Address Register */ diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 23c0f76..7e833fd 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -7,6 +7,8 @@ #include <config.h> #include <ns16550.h> #include <watchdog.h> +#include <linux/types.h> +#include <asm/io.h> #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -14,28 +16,35 @@ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED +#define serial_out(x,y) outb(x,(ulong)y) +#define serial_in(y) inb((ulong)y) +#else +#define serial_out(x,y) writeb(x,y) +#define serial_in(y) readb(y) +#endif void NS16550_init (NS16550_t com_port, int baud_divisor) { - com_port->ier = 0x00; + serial_out(0x00, &com_port->ier); #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) - com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ + serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCRVAL; - com_port->mcr = UART_MCRVAL; - com_port->fcr = UART_FCRVAL; - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCRVAL; + serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr); + serial_out(0, &com_port->dll); + serial_out(0, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(UART_MCRVAL, &com_port->mcr); + serial_out(UART_FCRVAL, &com_port->fcr); + serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) #if defined(CONFIG_APTIX) - com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ + serial_out(3, &com_port->mdr1); /* /13 mode so Aptix 6MHz can hit 115200 */ #else - com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */ + serial_out(0, &com_port->mdr1); /* /16 is proper to hit 115200 with 48MHz */ #endif #endif /* CONFIG_OMAP */ } @@ -43,42 +52,42 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) #ifndef CONFIG_NS16550_MIN_FUNCTIONS void NS16550_reinit (NS16550_t com_port, int baud_divisor) { - com_port->ier = 0x00; - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCRVAL; - com_port->mcr = UART_MCRVAL; - com_port->fcr = UART_FCRVAL; - com_port->lcr = UART_LCR_BKSE; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCRVAL; + serial_out(0x00, &com_port->ier); + serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + serial_out(0, &com_port->dll); + serial_out(0, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(UART_MCRVAL, &com_port->mcr); + serial_out(UART_FCRVAL, &com_port->fcr); + serial_out(UART_LCR_BKSE, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ void NS16550_putc (NS16550_t com_port, char c) { - while ((com_port->lsr & UART_LSR_THRE) == 0); - com_port->thr = c; + while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0); + serial_out(c, &com_port->thr); } #ifndef CONFIG_NS16550_MIN_FUNCTIONS char NS16550_getc (NS16550_t com_port) { - while ((com_port->lsr & UART_LSR_DR) == 0) { + while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { #ifdef CONFIG_USB_TTY extern void usbtty_poll(void); usbtty_poll(); #endif WATCHDOG_RESET(); } - return (com_port->rbr); + return serial_in(&com_port->rbr); } int NS16550_tstc (NS16550_t com_port) { - return ((com_port->lsr & UART_LSR_DR) != 0); + return ((serial_in(&com_port->lsr) & UART_LSR_DR) != 0); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index f18f7f4..f383011 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -69,7 +69,7 @@ void serial_setbrg (void) #else void serial_setbrg (void) -{ +{ int n, k; const unsigned max_uns = 0xFFFFFFFF; unsigned best_n, best_m, baud; @@ -114,12 +114,14 @@ int serial_init (void) YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; writel(action, &uart->action); - - /* control register cleanup */ - /* no interrupts enabled */ - /* one stop bit */ - /* hardware flow control disabled */ - /* 8 bits */ + + /* + * control register cleanup + * no interrupts enabled + * one stop bit + * hardware flow control disabled + * 8 bits + */ control = (0x7 << YANU_CONTROL_BITS_POS); /* enven parity just to be clean */ control |= YANU_CONTROL_PAREVEN; @@ -146,7 +148,7 @@ void serial_putc (char c) if (c == '\n') serial_putc ('\r'); - + while (1) { status = readl(&uart->status); tx_chars = (status>>YANU_TFIFO_CHARS_POS) @@ -174,13 +176,13 @@ int serial_tstc(void) status = readl(&uart->status); return (((status >> YANU_RFIFO_CHARS_POS) & ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); -} +} int serial_getc (void) { while (serial_tstc() == 0) WATCHDOG_RESET (); - + /* first we pull the char */ writel(YANU_ACTION_RFIFO_PULL, &uart->action); diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 200b907..f09e55f 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -23,7 +23,6 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_phy.a COBJS-$(CONFIG_TWL4030_USB) += twl4030.o -COBJS-y := twl4030.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a5e339a..7d84fc7 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -25,20 +25,19 @@ include $(TOPDIR)/config.mk LIB := $(obj)libvideo.a -COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o +COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_AMBA) += amba.o -COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o -COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o +COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o +COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o -COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o +COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o -COBJS-y += videomodes.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index 99a595e..7f04b49 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c @@ -56,22 +56,7 @@ void lcd_panel_disable(void) #define msleep(a) udelay(a * 1000) -#ifndef CONFIG_DISPLAY_VBEST_VGG322403 -#define XRES 240 -#define YRES 320 -#define PANEL_TYPE IPU_PANEL_TFT -#define PIXEL_CLK 185925 -#define PIXEL_FMT IPU_PIX_FMT_RGB666 -#define H_START_WIDTH 9 /* left_margin */ -#define H_SYNC_WIDTH 1 /* hsync_len */ -#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ -#define V_START_WIDTH 7 /* upper_margin */ -#define V_SYNC_WIDTH 1 /* vsync_len */ -#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ -#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) -#define IF_CONF 0 -#define IF_CLK_DIV 0x175 -#else /* Display Vbest VGG322403 */ +#if defined(CONFIG_DISPLAY_VBEST_VGG322403) #define XRES 320 #define YRES 240 #define PANEL_TYPE IPU_PANEL_TFT @@ -86,6 +71,36 @@ void lcd_panel_disable(void) #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) #define IF_CONF 0 #define IF_CLK_DIV 0x175 +#elif defined(CONFIG_DISPLAY_COM57H5M10XRC) +#define XRES 640 +#define YRES 480 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 40000 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 120 /* left_margin */ +#define H_SYNC_WIDTH 30 /* hsync_len */ +#define H_END_WIDTH (10 + 30) /* right_margin + hsync_len */ +#define V_START_WIDTH 35 /* upper_margin */ +#define V_SYNC_WIDTH 3 /* vsync_len */ +#define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 +#else +#define XRES 240 +#define YRES 320 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 185925 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 9 /* left_margin */ +#define H_SYNC_WIDTH 1 /* hsync_len */ +#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ +#define V_START_WIDTH 7 /* upper_margin */ +#define V_SYNC_WIDTH 1 /* vsync_len */ +#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 #endif #define LCD_COLOR_IPU LCD_COLOR16 diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 391dea4..39e3efe 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -1178,6 +1178,7 @@ int ubifs_mount(char *vol_name) ubifs_umount(ubifs_sb->s_fs_info); INIT_LIST_HEAD(&ubifs_infos); + INIT_LIST_HEAD(&ubifs_fs_type.fs_supers); /* * Mount in read-only mode diff --git a/include/.gitignore b/include/.gitignore index 4481412..77594e5 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -1,7 +1,5 @@ /autoconf.mk* /asm -/asm-*/arch -/asm-*/proc /bmp_logo.h /config.h /config.mk diff --git a/include/asm-generic/ioctl.h b/include/asm-generic/ioctl.h new file mode 100644 index 0000000..15828b2 --- /dev/null +++ b/include/asm-generic/ioctl.h @@ -0,0 +1,105 @@ +#ifndef _ASM_GENERIC_IOCTL_H +#define _ASM_GENERIC_IOCTL_H + +/* ioctl command encoding: 32 bits total, command in lower 16 bits, + * size of the parameter structure in the lower 14 bits of the + * upper 16 bits. + * Encoding the size of the parameter structure in the ioctl request + * is useful for catching programs compiled with old versions + * and to avoid overwriting user space outside the user buffer area. + * The highest 2 bits are reserved for indicating the ``access mode''. + * NOTE: This limits the max parameter size to 16kB -1 ! + */ + +/* + * The following is for compatibility across the various Linux + * platforms. The generic ioctl numbering scheme doesn't really enforce + * a type field. De facto, however, the top 8 bits of the lower 16 + * bits are indeed used as a type field, so we might just as well make + * this explicit here. Please be sure to use the decoding macros + * below from now on. + */ +#define _IOC_NRBITS 8 +#define _IOC_TYPEBITS 8 + +/* + * Let any architecture override either of the following before + * including this file. + */ + +#ifndef _IOC_SIZEBITS +# define _IOC_SIZEBITS 14 +#endif + +#ifndef _IOC_DIRBITS +# define _IOC_DIRBITS 2 +#endif + +#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) +#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) +#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) +#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) + +#define _IOC_NRSHIFT 0 +#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) +#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) +#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) + +/* + * Direction bits, which any architecture can choose to override + * before including this file. + */ + +#ifndef _IOC_NONE +# define _IOC_NONE 0U +#endif + +#ifndef _IOC_WRITE +# define _IOC_WRITE 1U +#endif + +#ifndef _IOC_READ +# define _IOC_READ 2U +#endif + +#define _IOC(dir,type,nr,size) \ + (((dir) << _IOC_DIRSHIFT) | \ + ((type) << _IOC_TYPESHIFT) | \ + ((nr) << _IOC_NRSHIFT) | \ + ((size) << _IOC_SIZESHIFT)) + +#ifdef __KERNEL__ +/* provoke compile error for invalid uses of size argument */ +extern unsigned int __invalid_size_argument_for_IOC; +#define _IOC_TYPECHECK(t) \ + ((sizeof(t) == sizeof(t[1]) && \ + sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ + sizeof(t) : __invalid_size_argument_for_IOC) +#else +#define _IOC_TYPECHECK(t) (sizeof(t)) +#endif + +/* used to create numbers */ +#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) +#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) +#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) + +/* used to decode ioctl numbers.. */ +#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) +#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) +#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) +#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) + +/* ...and for the drivers/sound files... */ + +#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) +#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) +#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) +#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) +#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) + +#endif /* _ASM_GENERIC_IOCTL_H */ diff --git a/include/common.h b/include/common.h index df956bb..8bca04f 100644 --- a/include/common.h +++ b/include/common.h @@ -218,7 +218,7 @@ void hang (void) __attribute__ ((noreturn)); /* */ phys_size_t initdram (int); int display_options (void); -void print_size (phys_size_t, const char *); +void print_size(unsigned long long, const char *); int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen); /* common/main.c */ @@ -470,7 +470,6 @@ void ft_pci_setup(void *blob, bd_t *bd); /* $(CPU)/serial.c */ int serial_init (void); void serial_exit (void); -void serial_addr (unsigned int); void serial_setbrg (void); void serial_putc (const char); void serial_putc_raw(const char); diff --git a/include/compiler.h b/include/compiler.h index 332618e..8030bf6 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -55,6 +55,7 @@ typedef unsigned int uint; typedef uint8_t __u8; typedef uint16_t __u16; typedef uint32_t __u32; +typedef unsigned int uint; #define uswap_16(x) \ ((((x) & 0xff00) >> 8) | \ diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index ec982bd..ae0a873 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_COMMAND_EDIT 1 -#define CONFIG_COMMAND_HISTORY 1 #define CONFIG_COMPLETE_ADDRESSES 1 #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 41eaaab..20849bc 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -304,6 +304,7 @@ extern int flash_banks; * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index d516c3c..1c8c68b 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -59,7 +59,7 @@ #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ -#undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_MV64360_ECC /* enable ECC support */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ @@ -628,5 +628,7 @@ #define CONFIG_SYS_BOARD_ASM_INIT 1 #define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) +#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) +#define CONFIG_SYS_PLD_VER 0xf0e00000 #endif /* __CONFIG_H */ diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 26897c6..c28eb64 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -234,7 +234,11 @@ #define CONFIG_BOOTP_SEND_HOSTNAME /* USB */ +#define CONFIG_SYS_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* * Environment @@ -267,6 +271,8 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_I2C #define CONFIG_CMD_FPGA +#define CONFIG_CMD_USB +#define CONFIG_DOS_PARTITION #undef CONFIG_WATCHDOG diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 84af8df..9104f1a 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -126,6 +126,7 @@ #else #define CONFIG_SYS_NAND_BASE 0xE2800000 #endif +#define CONFIG_SYS_FPGA_BASE 0xFF000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -184,6 +185,16 @@ #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \ + | BR_PS_16 \ + | BR_MS_UPMA \ + | BR_V ) +#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \ + | OR_UPM_BCTLD) + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB) + /* * JFFS2 configuration */ @@ -407,7 +418,8 @@ | SICRH_ETSEC2_G \ | SICRH_TSOBI1 \ | SICRH_TSOBI2 ) -#define CONFIG_SYS_SICRL (SICRL_USBDR \ +#define CONFIG_SYS_SICRL ( SICRL_LBC \ + | SICRL_USBDR \ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 6a68bf4..361fe61 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -21,6 +21,7 @@ * MA 02111-1307 USA */ +#include <asm/ibmpc.h> /* * board/config.h - configuration options, board specific */ @@ -52,7 +53,27 @@ * bottom (processor) board MUST be removed! */ #undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG + + /*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SERIAL_MULTI +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 1843200 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_NS16550_COM2 UART1_BASE +#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) +#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) +#define CONFIG_SYS_NS16550_PORT_MAPPED /*----------------------------------------------------------------------- * Video Configuration @@ -65,8 +86,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_BAUDRATE 9600 - /*----------------------------------------------------------------------- * Command line configuration. */ @@ -86,9 +105,10 @@ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_CMD_PCI /* PCI support */ +#define CONFIG_CMD_PING /* ICMP echo support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ @@ -121,10 +141,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */ /*----------------------------------------------------------------------- * SDRAM Configuration @@ -143,7 +160,7 @@ * CPU Features */ #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */ +#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */ #define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */ #undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */ #undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */ @@ -182,7 +199,7 @@ CONFIG_SYS_FLASH_BASE_1, \ CONFIG_SYS_FLASH_BASE_2} #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_LEGACY_512Kx8 @@ -210,13 +227,11 @@ #define CONFIG_SYS_THIRD_PCI_IRQ 11 #define CONFIG_SYS_FORTH_PCI_IRQ 15 -/*----------------------------------------------------------------------- - * Hardware watchdog configuration + /* + * Network device (TRL8100B) support */ -#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000 -#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0 -#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 -#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0 +#define CONFIG_NET_MULTI +#define CONFIG_RTL8139 /*----------------------------------------------------------------------- * FPGA configuration diff --git a/include/configs/icon.h b/include/configs/icon.h new file mode 100644 index 0000000..3a57d69 --- /dev/null +++ b/include/configs/icon.h @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * icon.h - configuration for Mosaixtech ICON (440SPe) + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ICON 1 /* Board is icon */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME icon +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ +#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 +#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 +#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 + +/* base address of inbound PCIe window */ +#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ +#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 +#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 + +#define CONFIG_SYS_FLASH_SIZE (64 << 20) +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ + (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +/* + * Initial RAM & stack pointer (placed in internal SRAM) + */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE +#undef CONFIG_SYS_EXT_SERIAL_CLOCK + +/* + * DDR2 SDRAM + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ +#define CONFIG_DDR_ECC /* with ECC support */ +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 8 + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 +#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + +#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ + +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * Xilinx System ACE support + */ +#define CONFIG_SYSTEMACE /* Enable SystemACE support */ +#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ +#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE +#define CONFIG_DOS_PARTITION + +/* + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash) initialization */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (Xilinx System ACE controller) initialization */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* + * Initialize EBC CONFIG - + * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + */ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_16PERCLK | \ + EBC_CFG_ATC_PREVIOUS | \ + EBC_CFG_DTC_PREVIOUS | \ + EBC_CFG_CTC_PREVIOUS | \ + EBC_CFG_OEO_PREVIOUS | \ + EBC_CFG_EMC_DEFAULT | \ + EBC_CFG_PME_DISABLE | \ + EBC_CFG_PR_16) + +/* + * GPIO Setup + */ +#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 +#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 +#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 +#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 + +#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ + GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) +#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_ODR 0 + +#endif /* __CONFIG_H */ diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 729d1c0..3a9f790 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_COMMAND_HISTORY 1 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_HUSH_INIT_VAR 1 diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h index c04830b..0224608 100644 --- a/include/configs/manroland/common.h +++ b/include/configs/manroland/common.h @@ -126,7 +126,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_COMMAND_HISTORY 1 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Enable an alternate, more extensive memory test */ diff --git a/include/configs/qong.h b/include/configs/qong.h index 1a2f19f..100fa3f 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -84,7 +84,7 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP -#define CONFIG_DISPLAY_VBEST_VGG322403 +#define CONFIG_DISPLAY_COM57H5M10XRC /* * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the @@ -143,9 +143,9 @@ " console=ttymxc0,${baudrate}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addmisc=setenv bootargs ${bootargs}\0" \ - "uboot_addr=a0000000\0" \ - "kernel_addr=a0080000\0" \ - "ramdisk_addr=a0300000\0" \ + "uboot_addr=A0000000\0" \ + "kernel_addr=A00A0000\0" \ + "ramdisk_addr=A0300000\0" \ "u-boot=qong/u-boot.bin\0" \ "kernel_addr_r=80800000\0" \ "hostname=qong\0" \ @@ -188,6 +188,10 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif #define CONFIG_MISC_INIT_R 1 /*----------------------------------------------------------------------- @@ -274,7 +278,7 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=physmap-flash.0" #define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:256k(U-Boot),128k(env1)," \ - "128k(env2),2560k(kernel),13m(ramdisk),-(user)" + "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ + "128k(env2),2432k(kernel),13m(ramdisk),-(user)" #endif /* __CONFIG_H */ diff --git a/include/linux/apm_bios.h b/include/linux/apm_bios.h new file mode 100644 index 0000000..01a6244 --- /dev/null +++ b/include/linux/apm_bios.h @@ -0,0 +1,220 @@ +#ifndef _LINUX_APM_H +#define _LINUX_APM_H + +/* + * Include file for the interface to an APM BIOS + * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2, or (at your option) any + * later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/types.h> + +typedef unsigned short apm_event_t; +typedef unsigned short apm_eventinfo_t; + +struct apm_bios_info { + __u16 version; + __u16 cseg; + __u32 offset; + __u16 cseg_16; + __u16 dseg; + __u16 flags; + __u16 cseg_len; + __u16 cseg_16_len; + __u16 dseg_len; +}; + +#ifdef __KERNEL__ + +#define APM_CS (GDT_ENTRY_APMBIOS_BASE * 8) +#define APM_CS_16 (APM_CS + 8) +#define APM_DS (APM_CS_16 + 8) + +/* Results of APM Installation Check */ +#define APM_16_BIT_SUPPORT 0x0001 +#define APM_32_BIT_SUPPORT 0x0002 +#define APM_IDLE_SLOWS_CLOCK 0x0004 +#define APM_BIOS_DISABLED 0x0008 +#define APM_BIOS_DISENGAGED 0x0010 + +/* + * Data for APM that is persistent across module unload/load + */ +struct apm_info { + struct apm_bios_info bios; + unsigned short connection_version; + int get_power_status_broken; + int get_power_status_swabinminutes; + int allow_ints; + int forbid_idle; + int realmode_power_off; + int disabled; +}; + +/* + * The APM function codes + */ +#define APM_FUNC_INST_CHECK 0x5300 +#define APM_FUNC_REAL_CONN 0x5301 +#define APM_FUNC_16BIT_CONN 0x5302 +#define APM_FUNC_32BIT_CONN 0x5303 +#define APM_FUNC_DISCONN 0x5304 +#define APM_FUNC_IDLE 0x5305 +#define APM_FUNC_BUSY 0x5306 +#define APM_FUNC_SET_STATE 0x5307 +#define APM_FUNC_ENABLE_PM 0x5308 +#define APM_FUNC_RESTORE_BIOS 0x5309 +#define APM_FUNC_GET_STATUS 0x530a +#define APM_FUNC_GET_EVENT 0x530b +#define APM_FUNC_GET_STATE 0x530c +#define APM_FUNC_ENABLE_DEV_PM 0x530d +#define APM_FUNC_VERSION 0x530e +#define APM_FUNC_ENGAGE_PM 0x530f +#define APM_FUNC_GET_CAP 0x5310 +#define APM_FUNC_RESUME_TIMER 0x5311 +#define APM_FUNC_RESUME_ON_RING 0x5312 +#define APM_FUNC_TIMER 0x5313 + +/* + * Function code for APM_FUNC_RESUME_TIMER + */ +#define APM_FUNC_DISABLE_TIMER 0 +#define APM_FUNC_GET_TIMER 1 +#define APM_FUNC_SET_TIMER 2 + +/* + * Function code for APM_FUNC_RESUME_ON_RING + */ +#define APM_FUNC_DISABLE_RING 0 +#define APM_FUNC_ENABLE_RING 1 +#define APM_FUNC_GET_RING 2 + +/* + * Function code for APM_FUNC_TIMER_STATUS + */ +#define APM_FUNC_TIMER_DISABLE 0 +#define APM_FUNC_TIMER_ENABLE 1 +#define APM_FUNC_TIMER_GET 2 + +/* + * in arch/i386/kernel/setup.c + */ +extern struct apm_info apm_info; + +#endif /* __KERNEL__ */ + +/* + * Power states + */ +#define APM_STATE_READY 0x0000 +#define APM_STATE_STANDBY 0x0001 +#define APM_STATE_SUSPEND 0x0002 +#define APM_STATE_OFF 0x0003 +#define APM_STATE_BUSY 0x0004 +#define APM_STATE_REJECT 0x0005 +#define APM_STATE_OEM_SYS 0x0020 +#define APM_STATE_OEM_DEV 0x0040 + +#define APM_STATE_DISABLE 0x0000 +#define APM_STATE_ENABLE 0x0001 + +#define APM_STATE_DISENGAGE 0x0000 +#define APM_STATE_ENGAGE 0x0001 + +/* + * Events (results of Get PM Event) + */ +#define APM_SYS_STANDBY 0x0001 +#define APM_SYS_SUSPEND 0x0002 +#define APM_NORMAL_RESUME 0x0003 +#define APM_CRITICAL_RESUME 0x0004 +#define APM_LOW_BATTERY 0x0005 +#define APM_POWER_STATUS_CHANGE 0x0006 +#define APM_UPDATE_TIME 0x0007 +#define APM_CRITICAL_SUSPEND 0x0008 +#define APM_USER_STANDBY 0x0009 +#define APM_USER_SUSPEND 0x000a +#define APM_STANDBY_RESUME 0x000b +#define APM_CAPABILITY_CHANGE 0x000c + +/* + * Error codes + */ +#define APM_SUCCESS 0x00 +#define APM_DISABLED 0x01 +#define APM_CONNECTED 0x02 +#define APM_NOT_CONNECTED 0x03 +#define APM_16_CONNECTED 0x05 +#define APM_16_UNSUPPORTED 0x06 +#define APM_32_CONNECTED 0x07 +#define APM_32_UNSUPPORTED 0x08 +#define APM_BAD_DEVICE 0x09 +#define APM_BAD_PARAM 0x0a +#define APM_NOT_ENGAGED 0x0b +#define APM_BAD_FUNCTION 0x0c +#define APM_RESUME_DISABLED 0x0d +#define APM_NO_ERROR 0x53 +#define APM_BAD_STATE 0x60 +#define APM_NO_EVENTS 0x80 +#define APM_NOT_PRESENT 0x86 + +/* + * APM Device IDs + */ +#define APM_DEVICE_BIOS 0x0000 +#define APM_DEVICE_ALL 0x0001 +#define APM_DEVICE_DISPLAY 0x0100 +#define APM_DEVICE_STORAGE 0x0200 +#define APM_DEVICE_PARALLEL 0x0300 +#define APM_DEVICE_SERIAL 0x0400 +#define APM_DEVICE_NETWORK 0x0500 +#define APM_DEVICE_PCMCIA 0x0600 +#define APM_DEVICE_BATTERY 0x8000 +#define APM_DEVICE_OEM 0xe000 +#define APM_DEVICE_OLD_ALL 0xffff +#define APM_DEVICE_CLASS 0x00ff +#define APM_DEVICE_MASK 0xff00 + +#ifdef __KERNEL__ +/* + * This is the "All Devices" ID communicated to the BIOS + */ +#define APM_DEVICE_BALL ((apm_info.connection_version > 0x0100) ? \ + APM_DEVICE_ALL : APM_DEVICE_OLD_ALL) +#endif + +/* + * Battery status + */ +#define APM_MAX_BATTERIES 2 + +/* + * APM defined capability bit flags + */ +#define APM_CAP_GLOBAL_STANDBY 0x0001 +#define APM_CAP_GLOBAL_SUSPEND 0x0002 +#define APM_CAP_RESUME_STANDBY_TIMER 0x0004 /* Timer resume from standby */ +#define APM_CAP_RESUME_SUSPEND_TIMER 0x0008 /* Timer resume from suspend */ +#define APM_CAP_RESUME_STANDBY_RING 0x0010 /* Resume on Ring fr standby */ +#define APM_CAP_RESUME_SUSPEND_RING 0x0020 /* Resume on Ring fr suspend */ +#define APM_CAP_RESUME_STANDBY_PCMCIA 0x0040 /* Resume on PCMCIA Ring */ +#define APM_CAP_RESUME_SUSPEND_PCMCIA 0x0080 /* Resume on PCMCIA Ring */ + +/* + * ioctl operations + */ +#include <linux/ioctl.h> + +#define APM_IOC_STANDBY _IO('A', 1) +#define APM_IOC_SUSPEND _IO('A', 2) + +#endif /* LINUX_APM_H */ diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h new file mode 100644 index 0000000..73dcf80 --- /dev/null +++ b/include/linux/compiler-gcc.h @@ -0,0 +1,87 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead." +#endif + +/* + * Common definitions for all gcc versions go here. + */ + + +/* Optimization barrier */ +/* The "volatile" is due to gcc bugs */ +#define barrier() __asm__ __volatile__("": : :"memory") + +/* + * This macro obfuscates arithmetic on a variable address so that gcc + * shouldn't recognize the original var, and make assumptions about it. + * + * This is needed because the C standard makes it undefined to do + * pointer arithmetic on "objects" outside their boundaries and the + * gcc optimizers assume this is the case. In particular they + * assume such arithmetic does not wrap. + * + * A miscompilation has been observed because of this on PPC. + * To work around it we hide the relationship of the pointer and the object + * using this macro. + * + * Versions of the ppc64 compiler before 4.1 had a bug where use of + * RELOC_HIDE could trash r30. The bug can be worked around by changing + * the inline assembly constraint from =g to =r, in this particular + * case either is valid. + */ +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ + (typeof(ptr)) (__ptr + (off)); }) + +/* &a[0] degrades to a pointer: a different type from an array */ +#define __must_be_array(a) \ + BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0]))) + +/* + * Force always-inline if the user requests it so via the .config, + * or if gcc is too old: + */ +#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ + !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) +# define inline inline __attribute__((always_inline)) +# define __inline__ __inline__ __attribute__((always_inline)) +# define __inline __inline __attribute__((always_inline)) +#endif + +#define __deprecated __attribute__((deprecated)) +#define __packed __attribute__((packed)) +#define __weak __attribute__((weak)) + +/* + * it doesn't make sense on ARM (currently the only user of __naked) to trace + * naked functions because then mcount is called without stack and frame pointer + * being set up and there is no chance to restore the lr register to the value + * before mcount was called. + */ +#define __naked __attribute__((naked)) notrace + +#define __noreturn __attribute__((noreturn)) + +/* + * From the GCC manual: + * + * Many functions have no effects except the return value and their + * return value depends only on the parameters and/or global + * variables. Such a function can be subject to common subexpression + * elimination and loop optimization just as an arithmetic operator + * would be. + * [...] + */ +#define __pure __attribute__((pure)) +#define __aligned(x) __attribute__((aligned(x))) +#define __printf(a,b) __attribute__((format(printf,a,b))) +#define noinline __attribute__((noinline)) +#define __attribute_const__ __attribute__((__const__)) +#define __maybe_unused __attribute__((unused)) +#define __always_unused __attribute__((unused)) + +#define __gcc_header(x) #x +#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h) +#define gcc_header(x) _gcc_header(x) +#include gcc_header(__GNUC__) diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h new file mode 100644 index 0000000..94dea3f --- /dev/null +++ b/include/linux/compiler-gcc4.h @@ -0,0 +1,61 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead." +#endif + +/* GCC 4.1.[01] miscompiles __weak */ +#ifdef __KERNEL__ +# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1 +# error Your version of gcc miscompiles the __weak directive +# endif +#endif + +#define __used __attribute__((__used__)) +#define __must_check __attribute__((warn_unused_result)) +#define __compiler_offsetof(a,b) __builtin_offsetof(a,b) +#define __always_inline inline __attribute__((always_inline)) + +/* + * A trick to suppress uninitialized variable warning without generating any + * code + */ +#define uninitialized_var(x) x = x + +#if __GNUC_MINOR__ >= 3 +/* Mark functions as cold. gcc will assume any path leading to a call + to them will be unlikely. This means a lot of manual unlikely()s + are unnecessary now for any paths leading to the usual suspects + like BUG(), printk(), panic() etc. [but let's keep them for now for + older compilers] + + Early snapshots of gcc 4.3 don't support this and we can't detect this + in the preprocessor, but we can live with this because they're unreleased. + Maketime probing would be overkill here. + + gcc also has a __attribute__((__hot__)) to move hot functions into + a special section, but I don't see any sense in this right now in + the kernel context */ +#define __cold __attribute__((__cold__)) + + +#if __GNUC_MINOR__ >= 5 +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + * + * Early snapshots of gcc 4.5 don't support this and we can't detect + * this in the preprocessor, but we can live with this because they're + * unreleased. Really, we need to have autoconf for the kernel. + */ +#define unreachable() __builtin_unreachable() +#endif + +#endif + +#if __GNUC_MINOR__ > 0 +#define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +#endif +#if __GNUC_MINOR__ >= 4 +#define __compiletime_warning(message) __attribute__((warning(message))) +#define __compiletime_error(message) __attribute__((error(message))) +#endif diff --git a/include/linux/compiler.h b/include/linux/compiler.h new file mode 100644 index 0000000..5be3dab --- /dev/null +++ b/include/linux/compiler.h @@ -0,0 +1,303 @@ +#ifndef __LINUX_COMPILER_H +#define __LINUX_COMPILER_H + +#ifndef __ASSEMBLY__ + +#ifdef __CHECKER__ +# define __user __attribute__((noderef, address_space(1))) +# define __kernel /* default address space */ +# define __safe __attribute__((safe)) +# define __force __attribute__((force)) +# define __nocast __attribute__((nocast)) +# define __iomem __attribute__((noderef, address_space(2))) +# define __acquires(x) __attribute__((context(x,0,1))) +# define __releases(x) __attribute__((context(x,1,0))) +# define __acquire(x) __context__(x,1) +# define __release(x) __context__(x,-1) +# define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) +extern void __chk_user_ptr(const volatile void __user *); +extern void __chk_io_ptr(const volatile void __iomem *); +#else +# define __user +# define __kernel +# define __safe +# define __force +# define __nocast +# define __iomem +# define __chk_user_ptr(x) (void)0 +# define __chk_io_ptr(x) (void)0 +# define __builtin_warning(x, y...) (1) +# define __acquires(x) +# define __releases(x) +# define __acquire(x) (void)0 +# define __release(x) (void)0 +# define __cond_lock(x,c) (c) +#endif + +#ifdef __KERNEL__ + +#ifdef __GNUC__ +#include <linux/compiler-gcc.h> +#endif + +#define notrace __attribute__((no_instrument_function)) + +/* Intel compiler defines __GNUC__. So we will overwrite implementations + * coming from above header files here + */ +#ifdef __INTEL_COMPILER +# include <linux/compiler-intel.h> +#endif + +/* + * Generic compiler-dependent macros required for kernel + * build go below this comment. Actual compiler/compiler version + * specific implementations come from the above header files + */ + +struct ftrace_branch_data { + const char *func; + const char *file; + unsigned line; + union { + struct { + unsigned long correct; + unsigned long incorrect; + }; + struct { + unsigned long miss; + unsigned long hit; + }; + unsigned long miss_hit[2]; + }; +}; + +/* + * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code + * to disable branch tracing on a per file basis. + */ +#if defined(CONFIG_TRACE_BRANCH_PROFILING) \ + && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__) +void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); + +#define likely_notrace(x) __builtin_expect(!!(x), 1) +#define unlikely_notrace(x) __builtin_expect(!!(x), 0) + +#define __branch_check__(x, expect) ({ \ + int ______r; \ + static struct ftrace_branch_data \ + __attribute__((__aligned__(4))) \ + __attribute__((section("_ftrace_annotated_branch"))) \ + ______f = { \ + .func = __func__, \ + .file = __FILE__, \ + .line = __LINE__, \ + }; \ + ______r = likely_notrace(x); \ + ftrace_likely_update(&______f, ______r, expect); \ + ______r; \ + }) + +/* + * Using __builtin_constant_p(x) to ignore cases where the return + * value is always the same. This idea is taken from a similar patch + * written by Daniel Walker. + */ +# ifndef likely +# define likely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1)) +# endif +# ifndef unlikely +# define unlikely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0)) +# endif + +#ifdef CONFIG_PROFILE_ALL_BRANCHES +/* + * "Define 'is'", Bill Clinton + * "Define 'if'", Steven Rostedt + */ +#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) ) +#define __trace_if(cond) \ + if (__builtin_constant_p((cond)) ? !!(cond) : \ + ({ \ + int ______r; \ + static struct ftrace_branch_data \ + __attribute__((__aligned__(4))) \ + __attribute__((section("_ftrace_branch"))) \ + ______f = { \ + .func = __func__, \ + .file = __FILE__, \ + .line = __LINE__, \ + }; \ + ______r = !!(cond); \ + ______f.miss_hit[______r]++; \ + ______r; \ + })) +#endif /* CONFIG_PROFILE_ALL_BRANCHES */ + +#else +# define likely(x) __builtin_expect(!!(x), 1) +# define unlikely(x) __builtin_expect(!!(x), 0) +#endif + +/* Optimization barrier */ +#ifndef barrier +# define barrier() __memory_barrier() +#endif + +/* Unreachable code */ +#ifndef unreachable +# define unreachable() do { } while (1) +#endif + +#ifndef RELOC_HIDE +# define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ASSEMBLY__ */ + +#ifdef __KERNEL__ +/* + * Allow us to mark functions as 'deprecated' and have gcc emit a nice + * warning for each use, in hopes of speeding the functions removal. + * Usage is: + * int __deprecated foo(void) + */ +#ifndef __deprecated +# define __deprecated /* unimplemented */ +#endif + +#ifdef MODULE +#define __deprecated_for_modules __deprecated +#else +#define __deprecated_for_modules +#endif + +#ifndef __must_check +#define __must_check +#endif + +#ifndef CONFIG_ENABLE_MUST_CHECK +#undef __must_check +#define __must_check +#endif +#ifndef CONFIG_ENABLE_WARN_DEPRECATED +#undef __deprecated +#undef __deprecated_for_modules +#define __deprecated +#define __deprecated_for_modules +#endif + +/* + * Allow us to avoid 'defined but not used' warnings on functions and data, + * as well as force them to be emitted to the assembly file. + * + * As of gcc 3.4, static functions that are not marked with attribute((used)) + * may be elided from the assembly file. As of gcc 3.4, static data not so + * marked will not be elided, but this may change in a future gcc version. + * + * NOTE: Because distributions shipped with a backported unit-at-a-time + * compiler in gcc 3.3, we must define __used to be __attribute__((used)) + * for gcc >=3.3 instead of 3.4. + * + * In prior versions of gcc, such functions and data would be emitted, but + * would be warned about except with attribute((unused)). + * + * Mark functions that are referenced only in inline assembly as __used so + * the code is emitted even though it appears to be unreferenced. + */ +#ifndef __used +# define __used /* unimplemented */ +#endif + +#ifndef __maybe_unused +# define __maybe_unused /* unimplemented */ +#endif + +#ifndef __always_unused +# define __always_unused /* unimplemented */ +#endif + +#ifndef noinline +#define noinline +#endif + +/* + * Rather then using noinline to prevent stack consumption, use + * noinline_for_stack instead. For documentaiton reasons. + */ +#define noinline_for_stack noinline + +#ifndef __always_inline +#define __always_inline inline +#endif + +#endif /* __KERNEL__ */ + +/* + * From the GCC manual: + * + * Many functions do not examine any values except their arguments, + * and have no effects except the return value. Basically this is + * just slightly more strict class than the `pure' attribute above, + * since function is not allowed to read global memory. + * + * Note that a function that has pointer arguments and examines the + * data pointed to must _not_ be declared `const'. Likewise, a + * function that calls a non-`const' function usually must not be + * `const'. It does not make sense for a `const' function to return + * `void'. + */ +#ifndef __attribute_const__ +# define __attribute_const__ /* unimplemented */ +#endif + +/* + * Tell gcc if a function is cold. The compiler will assume any path + * directly leading to the call is unlikely. + */ + +#ifndef __cold +#define __cold +#endif + +/* Simple shorthand for a section definition */ +#ifndef __section +# define __section(S) __attribute__ ((__section__(#S))) +#endif + +/* Are two types/vars the same type (ignoring qualifiers)? */ +#ifndef __same_type +# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) +#endif + +/* Compile time object size, -1 for unknown */ +#ifndef __compiletime_object_size +# define __compiletime_object_size(obj) -1 +#endif +#ifndef __compiletime_warning +# define __compiletime_warning(message) +#endif +#ifndef __compiletime_error +# define __compiletime_error(message) +#endif + +/* + * Prevent the compiler from merging or refetching accesses. The compiler + * is also forbidden from reordering successive instances of ACCESS_ONCE(), + * but only when the compiler is aware of some particular ordering. One way + * to make the compiler aware of ordering is to put the two invocations of + * ACCESS_ONCE() in different C statements. + * + * This macro does absolutely -nothing- to prevent the CPU from reordering, + * merging, or refetching absolutely anything at any time. Its main intended + * use is to mediate communication between process-level code and irq/NMI + * handlers, all running on the same CPU. + */ +#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) + +#endif /* __LINUX_COMPILER_H */ diff --git a/include/linux/edd.h b/include/linux/edd.h new file mode 100644 index 0000000..4cbd0fe --- /dev/null +++ b/include/linux/edd.h @@ -0,0 +1,194 @@ +/* + * linux/include/linux/edd.h + * Copyright (C) 2002, 2003, 2004 Dell Inc. + * by Matt Domsch <Matt_Domsch@dell.com> + * + * structures and definitions for the int 13h, ax={41,48}h + * BIOS Enhanced Disk Drive Services + * This is based on the T13 group document D1572 Revision 0 (August 14 2002) + * available at http://www.t13.org/docs2002/d1572r0.pdf. It is + * very similar to D1484 Revision 3 http://www.t13.org/docs2002/d1484r3.pdf + * + * In a nutshell, arch/{i386,x86_64}/boot/setup.S populates a scratch + * table in the boot_params that contains a list of BIOS-enumerated + * boot devices. + * In arch/{i386,x86_64}/kernel/setup.c, this information is + * transferred into the edd structure, and in drivers/firmware/edd.c, that + * information is used to identify BIOS boot disk. The code in setup.S + * is very sensitive to the size of these structures. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2.0 as published by + * the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef _LINUX_EDD_H +#define _LINUX_EDD_H + +#include <linux/types.h> + +#define EDDNR 0x1e9 /* addr of number of edd_info structs at EDDBUF + in boot_params - treat this as 1 byte */ +#define EDDBUF 0xd00 /* addr of edd_info structs in boot_params */ +#define EDDMAXNR 6 /* number of edd_info structs starting at EDDBUF */ +#define EDDEXTSIZE 8 /* change these if you muck with the structures */ +#define EDDPARMSIZE 74 +#define CHECKEXTENSIONSPRESENT 0x41 +#define GETDEVICEPARAMETERS 0x48 +#define LEGACYGETDEVICEPARAMETERS 0x08 +#define EDDMAGIC1 0x55AA +#define EDDMAGIC2 0xAA55 + + +#define READ_SECTORS 0x02 /* int13 AH=0x02 is READ_SECTORS command */ +#define EDD_MBR_SIG_OFFSET 0x1B8 /* offset of signature in the MBR */ +#define EDD_MBR_SIG_BUF 0x290 /* addr in boot params */ +#define EDD_MBR_SIG_MAX 16 /* max number of signatures to store */ +#define EDD_MBR_SIG_NR_BUF 0x1ea /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF + in boot_params - treat this as 1 byte */ + +#ifndef __ASSEMBLY__ + +#define EDD_EXT_FIXED_DISK_ACCESS (1 << 0) +#define EDD_EXT_DEVICE_LOCKING_AND_EJECTING (1 << 1) +#define EDD_EXT_ENHANCED_DISK_DRIVE_SUPPORT (1 << 2) +#define EDD_EXT_64BIT_EXTENSIONS (1 << 3) + +#define EDD_INFO_DMA_BOUNDARY_ERROR_TRANSPARENT (1 << 0) +#define EDD_INFO_GEOMETRY_VALID (1 << 1) +#define EDD_INFO_REMOVABLE (1 << 2) +#define EDD_INFO_WRITE_VERIFY (1 << 3) +#define EDD_INFO_MEDIA_CHANGE_NOTIFICATION (1 << 4) +#define EDD_INFO_LOCKABLE (1 << 5) +#define EDD_INFO_NO_MEDIA_PRESENT (1 << 6) +#define EDD_INFO_USE_INT13_FN50 (1 << 7) + +struct edd_device_params { + __u16 length; + __u16 info_flags; + __u32 num_default_cylinders; + __u32 num_default_heads; + __u32 sectors_per_track; + __u64 number_of_sectors; + __u16 bytes_per_sector; + __u32 dpte_ptr; /* 0xFFFFFFFF for our purposes */ + __u16 key; /* = 0xBEDD */ + __u8 device_path_info_length; /* = 44 */ + __u8 reserved2; + __u16 reserved3; + __u8 host_bus_type[4]; + __u8 interface_type[8]; + union { + struct { + __u16 base_address; + __u16 reserved1; + __u32 reserved2; + } __attribute__ ((packed)) isa; + struct { + __u8 bus; + __u8 slot; + __u8 function; + __u8 channel; + __u32 reserved; + } __attribute__ ((packed)) pci; + /* pcix is same as pci */ + struct { + __u64 reserved; + } __attribute__ ((packed)) ibnd; + struct { + __u64 reserved; + } __attribute__ ((packed)) xprs; + struct { + __u64 reserved; + } __attribute__ ((packed)) htpt; + struct { + __u64 reserved; + } __attribute__ ((packed)) unknown; + } interface_path; + union { + struct { + __u8 device; + __u8 reserved1; + __u16 reserved2; + __u32 reserved3; + __u64 reserved4; + } __attribute__ ((packed)) ata; + struct { + __u8 device; + __u8 lun; + __u8 reserved1; + __u8 reserved2; + __u32 reserved3; + __u64 reserved4; + } __attribute__ ((packed)) atapi; + struct { + __u16 id; + __u64 lun; + __u16 reserved1; + __u32 reserved2; + } __attribute__ ((packed)) scsi; + struct { + __u64 serial_number; + __u64 reserved; + } __attribute__ ((packed)) usb; + struct { + __u64 eui; + __u64 reserved; + } __attribute__ ((packed)) i1394; + struct { + __u64 wwid; + __u64 lun; + } __attribute__ ((packed)) fibre; + struct { + __u64 identity_tag; + __u64 reserved; + } __attribute__ ((packed)) i2o; + struct { + __u32 array_number; + __u32 reserved1; + __u64 reserved2; + } __attribute__ ((packed)) raid; + struct { + __u8 device; + __u8 reserved1; + __u16 reserved2; + __u32 reserved3; + __u64 reserved4; + } __attribute__ ((packed)) sata; + struct { + __u64 reserved1; + __u64 reserved2; + } __attribute__ ((packed)) unknown; + } device_path; + __u8 reserved4; + __u8 checksum; +} __attribute__ ((packed)); + +struct edd_info { + __u8 device; + __u8 version; + __u16 interface_support; + __u16 legacy_max_cylinder; + __u8 legacy_max_head; + __u8 legacy_sectors_per_track; + struct edd_device_params params; +} __attribute__ ((packed)); + +struct edd { + unsigned int mbr_signature[EDD_MBR_SIG_MAX]; + struct edd_info edd_info[EDDMAXNR]; + unsigned char mbr_signature_nr; + unsigned char edd_info_nr; +}; + +#ifdef __KERNEL__ +extern struct edd edd; +#endif /* __KERNEL__ */ +#endif /*!__ASSEMBLY__ */ + +#endif /* _LINUX_EDD_H */ diff --git a/include/linux/ioctl.h b/include/linux/ioctl.h new file mode 100644 index 0000000..7e55c36 --- /dev/null +++ b/include/linux/ioctl.h @@ -0,0 +1,6 @@ +#ifndef _LINUX_IOCTL_H +#define _LINUX_IOCTL_H + +#include <asm/ioctl.h> + +#endif /* _LINUX_IOCTL_H */ diff --git a/include/linux/ioport.h b/include/linux/ioport.h new file mode 100644 index 0000000..7129504 --- /dev/null +++ b/include/linux/ioport.h @@ -0,0 +1,192 @@ +/* + * ioport.h Definitions of routines for detecting, reserving and + * allocating system resources. + * + * Authors: Linus Torvalds + */ + +#ifndef _LINUX_IOPORT_H +#define _LINUX_IOPORT_H + +#ifndef __ASSEMBLY__ +#include <linux/compiler.h> +#include <linux/types.h> +/* + * Resources are tree-like, allowing + * nesting etc.. + */ +struct resource { + resource_size_t start; + resource_size_t end; + const char *name; + unsigned long flags; + struct resource *parent, *sibling, *child; +}; + +struct resource_list { + struct resource_list *next; + struct resource *res; + struct pci_dev *dev; +}; + +/* + * IO resources have these defined flags. + */ +#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ + +#define IORESOURCE_TYPE_BITS 0x00000f00 /* Resource type */ +#define IORESOURCE_IO 0x00000100 +#define IORESOURCE_MEM 0x00000200 +#define IORESOURCE_IRQ 0x00000400 +#define IORESOURCE_DMA 0x00000800 + +#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ +#define IORESOURCE_READONLY 0x00002000 +#define IORESOURCE_CACHEABLE 0x00004000 +#define IORESOURCE_RANGELENGTH 0x00008000 +#define IORESOURCE_SHADOWABLE 0x00010000 + +#define IORESOURCE_SIZEALIGN 0x00020000 /* size indicates alignment */ +#define IORESOURCE_STARTALIGN 0x00040000 /* start field is alignment */ + +#define IORESOURCE_MEM_64 0x00100000 + +#define IORESOURCE_EXCLUSIVE 0x08000000 /* Userland may not map this resource */ +#define IORESOURCE_DISABLED 0x10000000 +#define IORESOURCE_UNSET 0x20000000 +#define IORESOURCE_AUTO 0x40000000 +#define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ + +/* PnP IRQ specific bits (IORESOURCE_BITS) */ +#define IORESOURCE_IRQ_HIGHEDGE (1<<0) +#define IORESOURCE_IRQ_LOWEDGE (1<<1) +#define IORESOURCE_IRQ_HIGHLEVEL (1<<2) +#define IORESOURCE_IRQ_LOWLEVEL (1<<3) +#define IORESOURCE_IRQ_SHAREABLE (1<<4) +#define IORESOURCE_IRQ_OPTIONAL (1<<5) + +/* PnP DMA specific bits (IORESOURCE_BITS) */ +#define IORESOURCE_DMA_TYPE_MASK (3<<0) +#define IORESOURCE_DMA_8BIT (0<<0) +#define IORESOURCE_DMA_8AND16BIT (1<<0) +#define IORESOURCE_DMA_16BIT (2<<0) + +#define IORESOURCE_DMA_MASTER (1<<2) +#define IORESOURCE_DMA_BYTE (1<<3) +#define IORESOURCE_DMA_WORD (1<<4) + +#define IORESOURCE_DMA_SPEED_MASK (3<<6) +#define IORESOURCE_DMA_COMPATIBLE (0<<6) +#define IORESOURCE_DMA_TYPEA (1<<6) +#define IORESOURCE_DMA_TYPEB (2<<6) +#define IORESOURCE_DMA_TYPEF (3<<6) + +/* PnP memory I/O specific bits (IORESOURCE_BITS) */ +#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ +#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ +#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ +#define IORESOURCE_MEM_TYPE_MASK (3<<3) +#define IORESOURCE_MEM_8BIT (0<<3) +#define IORESOURCE_MEM_16BIT (1<<3) +#define IORESOURCE_MEM_8AND16BIT (2<<3) +#define IORESOURCE_MEM_32BIT (3<<3) +#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ +#define IORESOURCE_MEM_EXPANSIONROM (1<<6) + +/* PnP I/O specific bits (IORESOURCE_BITS) */ +#define IORESOURCE_IO_16BIT_ADDR (1<<0) +#define IORESOURCE_IO_FIXED (1<<1) + +/* PCI ROM control bits (IORESOURCE_BITS) */ +#define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ +#define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ +#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ +#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ + +/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ +#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ + +/* PC/ISA/whatever - the normal PC address spaces: IO and memory */ +extern struct resource ioport_resource; +extern struct resource iomem_resource; + +extern int request_resource(struct resource *root, struct resource *new); +extern int release_resource(struct resource *new); +extern void reserve_region_with_split(struct resource *root, + resource_size_t start, resource_size_t end, + const char *name); +extern int insert_resource(struct resource *parent, struct resource *new); +extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new); +extern int allocate_resource(struct resource *root, struct resource *new, + resource_size_t size, resource_size_t min, + resource_size_t max, resource_size_t align, + void (*alignf)(void *, struct resource *, + resource_size_t, resource_size_t), + void *alignf_data); +int adjust_resource(struct resource *res, resource_size_t start, + resource_size_t size); +resource_size_t resource_alignment(struct resource *res); +static inline resource_size_t resource_size(const struct resource *res) +{ + return res->end - res->start + 1; +} +static inline unsigned long resource_type(const struct resource *res) +{ + return res->flags & IORESOURCE_TYPE_BITS; +} + +/* Convenience shorthand with allocation */ +#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0) +#define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl) +#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0) +#define request_mem_region_exclusive(start,n,name) \ + __request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE) +#define rename_region(region, newname) do { (region)->name = (newname); } while (0) + +extern struct resource * __request_region(struct resource *, + resource_size_t start, + resource_size_t n, + const char *name, int flags); + +/* Compatibility cruft */ +#define release_region(start,n) __release_region(&ioport_resource, (start), (n)) +#define check_mem_region(start,n) __check_region(&iomem_resource, (start), (n)) +#define release_mem_region(start,n) __release_region(&iomem_resource, (start), (n)) + +extern int __check_region(struct resource *, resource_size_t, resource_size_t); +extern void __release_region(struct resource *, resource_size_t, + resource_size_t); + +static inline int __deprecated check_region(resource_size_t s, + resource_size_t n) +{ + return __check_region(&ioport_resource, s, n); +} + +/* Wrappers for managed devices */ +struct device; +#define devm_request_region(dev,start,n,name) \ + __devm_request_region(dev, &ioport_resource, (start), (n), (name)) +#define devm_request_mem_region(dev,start,n,name) \ + __devm_request_region(dev, &iomem_resource, (start), (n), (name)) + +extern struct resource * __devm_request_region(struct device *dev, + struct resource *parent, resource_size_t start, + resource_size_t n, const char *name); + +#define devm_release_region(dev, start, n) \ + __devm_release_region(dev, &ioport_resource, (start), (n)) +#define devm_release_mem_region(dev, start, n) \ + __devm_release_region(dev, &iomem_resource, (start), (n)) + +extern void __devm_release_region(struct device *dev, struct resource *parent, + resource_size_t start, resource_size_t n); +extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size); +extern int iomem_is_exclusive(u64 addr); + +extern int +walk_system_ram_range(unsigned long start_pfn, unsigned long nr_pages, + void *arg, int (*func)(unsigned long, unsigned long, void *)); + +#endif /* __ASSEMBLY__ */ +#endif /* _LINUX_IOPORT_H */ diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h new file mode 100644 index 0000000..899fbb4 --- /dev/null +++ b/include/linux/screen_info.h @@ -0,0 +1,84 @@ +#ifndef _SCREEN_INFO_H +#define _SCREEN_INFO_H + +#include <linux/types.h> + +/* + * These are set up by the setup-routine at boot-time: + */ + +struct screen_info { + __u8 orig_x; /* 0x00 */ + __u8 orig_y; /* 0x01 */ + __u16 ext_mem_k; /* 0x02 */ + __u16 orig_video_page; /* 0x04 */ + __u8 orig_video_mode; /* 0x06 */ + __u8 orig_video_cols; /* 0x07 */ + __u8 flags; /* 0x08 */ + __u8 unused2; /* 0x09 */ + __u16 orig_video_ega_bx;/* 0x0a */ + __u16 unused3; /* 0x0c */ + __u8 orig_video_lines; /* 0x0e */ + __u8 orig_video_isVGA; /* 0x0f */ + __u16 orig_video_points;/* 0x10 */ + + /* VESA graphic mode -- linear frame buffer */ + __u16 lfb_width; /* 0x12 */ + __u16 lfb_height; /* 0x14 */ + __u16 lfb_depth; /* 0x16 */ + __u32 lfb_base; /* 0x18 */ + __u32 lfb_size; /* 0x1c */ + __u16 cl_magic, cl_offset; /* 0x20 */ + __u16 lfb_linelength; /* 0x24 */ + __u8 red_size; /* 0x26 */ + __u8 red_pos; /* 0x27 */ + __u8 green_size; /* 0x28 */ + __u8 green_pos; /* 0x29 */ + __u8 blue_size; /* 0x2a */ + __u8 blue_pos; /* 0x2b */ + __u8 rsvd_size; /* 0x2c */ + __u8 rsvd_pos; /* 0x2d */ + __u16 vesapm_seg; /* 0x2e */ + __u16 vesapm_off; /* 0x30 */ + __u16 pages; /* 0x32 */ + __u16 vesa_attributes; /* 0x34 */ + __u32 capabilities; /* 0x36 */ + __u8 _reserved[6]; /* 0x3a */ +} __attribute__((packed)); + +#define VIDEO_TYPE_MDA 0x10 /* Monochrome Text Display */ +#define VIDEO_TYPE_CGA 0x11 /* CGA Display */ +#define VIDEO_TYPE_EGAM 0x20 /* EGA/VGA in Monochrome Mode */ +#define VIDEO_TYPE_EGAC 0x21 /* EGA in Color Mode */ +#define VIDEO_TYPE_VGAC 0x22 /* VGA+ in Color Mode */ +#define VIDEO_TYPE_VLFB 0x23 /* VESA VGA in graphic mode */ + +#define VIDEO_TYPE_PICA_S3 0x30 /* ACER PICA-61 local S3 video */ +#define VIDEO_TYPE_MIPS_G364 0x31 /* MIPS Magnum 4000 G364 video */ +#define VIDEO_TYPE_SGI 0x33 /* Various SGI graphics hardware */ + +#define VIDEO_TYPE_TGAC 0x40 /* DEC TGA */ + +#define VIDEO_TYPE_SUN 0x50 /* Sun frame buffer. */ +#define VIDEO_TYPE_SUNPCI 0x51 /* Sun PCI based frame buffer. */ + +#define VIDEO_TYPE_PMAC 0x60 /* PowerMacintosh frame buffer. */ + +#define VIDEO_TYPE_EFI 0x70 /* EFI graphic mode */ + +#define VIDEO_FLAGS_NOCURSOR (1 << 0) /* The video mode has no cursor set */ + +#ifdef __KERNEL__ +extern struct screen_info screen_info; + +#define ORIG_X (screen_info.orig_x) +#define ORIG_Y (screen_info.orig_y) +#define ORIG_VIDEO_MODE (screen_info.orig_video_mode) +#define ORIG_VIDEO_COLS (screen_info.orig_video_cols) +#define ORIG_VIDEO_EGA_BX (screen_info.orig_video_ega_bx) +#define ORIG_VIDEO_LINES (screen_info.orig_video_lines) +#define ORIG_VIDEO_ISVGA (screen_info.orig_video_isVGA) +#define ORIG_VIDEO_POINTS (screen_info.orig_video_points) +#endif /* __KERNEL__ */ + +#endif /* _SCREEN_INFO_H */ diff --git a/include/net.h b/include/net.h index 3f6a5d1..a180881 100644 --- a/include/net.h +++ b/include/net.h @@ -105,6 +105,7 @@ struct eth_device { #ifdef CONFIG_MCAST_TFTP int (*mcast) (struct eth_device*, u32 ip, u8 set); #endif + int (*write_hwaddr) (struct eth_device*); struct eth_device *next; void *priv; }; diff --git a/include/netdev.h b/include/netdev.h index 1dd80f0..882642a 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -41,6 +41,8 @@ int board_eth_init(bd_t *bis); int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ +int altera_tse_initialize(u8 dev_num, int mac_base, + int sgdma_rx_base, int sgdma_tx_base); int au1x00_enet_initialize(bd_t*); int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); @@ -51,6 +53,7 @@ int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); int ep93xx_eth_initialize(u8 dev_num, int base_addr); +int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); diff --git a/include/serial.h b/include/serial.h index 111edbe..6513d8e 100644 --- a/include/serial.h +++ b/include/serial.h @@ -26,7 +26,8 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ - defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ + defined(CONFIG_SYS_SC520) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 60f6a5f..d2c90a6 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -123,7 +123,7 @@ typedef int wait_queue_head_t; #define init_rwsem(...) do { } while (0) #define down_read(...) do { } while (0) #define down_write(...) do { } while (0) -#define down_write_trylock(...) 0 +#define down_write_trylock(...) 1 #define up_read(...) do { } while (0) #define up_write(...) do { } while (0) diff --git a/lib/display_options.c b/lib/display_options.c index 2dc2567..a711425 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -39,30 +39,37 @@ int display_options (void) } /* - * print sizes as "xxx kB", "xxx.y kB", "xxx MB", "xxx.y MB", - * xxx GB, or xxx.y GB as needed; allow for optional trailing string + * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB", + * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string * (like "\n") */ -void print_size (phys_size_t size, const char *s) +void print_size(unsigned long long size, const char *s) { - ulong m = 0, n; - phys_size_t d = 1 << 30; /* 1 GB */ - char c = 'G'; - - if (size < d) { /* try MB */ - c = 'M'; - d = 1 << 20; - if (size < d) { /* print in kB */ - c = 'k'; - d = 1 << 10; + unsigned long m = 0, n; + unsigned long long f; + static const char names[] = {'E', 'P', 'T', 'G', 'M', 'K'}; + unsigned long d = 10 * ARRAY_SIZE(names); + char c = 0; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(names); i++, d -= 10) { + if (size >> d) { + c = names[i]; + break; } } - n = size / d; + if (!c) { + printf("%llu Bytes%s", size, s); + return; + } + + n = size >> d; + f = size & ((1ULL << d) - 1); /* If there's a remainder, deal with it */ - if(size % d) { - m = (10 * (size - (n * d)) + (d / 2) ) / d; + if (f) { + m = (10ULL * f + (1ULL << (d - 1))) >> d; if (m >= 10) { m -= 10; @@ -70,11 +77,11 @@ void print_size (phys_size_t size, const char *s) } } - printf ("%2ld", n); + printf ("%lu", n); if (m) { printf (".%ld", m); } - printf (" %cB%s", c, s); + printf (" %ciB%s", c, s); } /* @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001-2004 + * (C) Copyright 2001-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -60,6 +60,14 @@ int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr) return eth_getenv_enetaddr(enetvar, enetaddr); } +static int eth_mac_skip(int index) +{ + char enetvar[15]; + char *skip_state; + sprintf(enetvar, index ? "eth%dmacskip" : "ethmacskip", index); + return ((skip_state = getenv(enetvar)) != NULL); +} + #ifdef CONFIG_NET_MULTI /* @@ -173,7 +181,8 @@ int eth_register(struct eth_device* dev) } #endif } else { - for (d=eth_devices; d->next!=eth_devices; d=d->next); + for (d=eth_devices; d->next!=eth_devices; d=d->next) + ; d->next = dev; } @@ -241,6 +250,11 @@ int eth_initialize(bd_t *bis) memcpy(dev->enetaddr, env_enetaddr, 6); } + if (dev->write_hwaddr && + !eth_mac_skip(eth_number) && + is_valid_ether_addr(dev->enetaddr)) { + dev->write_hwaddr(dev); + } eth_number++; dev = dev->next; @@ -1872,11 +1872,13 @@ void copy_filename (char *dst, char *src, int size) #if defined(CONFIG_CMD_NFS) || defined(CONFIG_CMD_SNTP) || defined(CONFIG_CMD_DNS) /* - * make port a little random, but use something trivial to compute + * make port a little random (1024-17407) + * This keeps the math somewhat trivial to compute, and seems to work with + * all supported protocols/clients/servers */ unsigned int random_port(void) { - return 1024 + (get_timer(0) % 0x8000);; + return 1024 + (get_timer(0) % 0x4000); } #endif diff --git a/post/cpu/mpc83xx/Makefile b/post/cpu/mpc83xx/Makefile new file mode 100644 index 0000000..86d8784 --- /dev/null +++ b/post/cpu/mpc83xx/Makefile @@ -0,0 +1,30 @@ +# +# (C) Copyright 2002-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(OBJTREE)/include/autoconf.mk + +LIB = libpostmpc83xx.a + +AOBJS-$(CONFIG_HAS_POST) += +COBJS-$(CONFIG_HAS_POST) += ecc.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c new file mode 100644 index 0000000..de87339 --- /dev/null +++ b/post/cpu/mpc83xx/ecc.c @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2010 + * Eastman Kodak Company, <www.kodak.com> + * Michael Zaidman, <michael.zaidman@kodak.com> + * + * The code is based on the cpu/mpc83xx/ecc.c written by + * Dave Liu <daveliu@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc83xx.h> +#include <watchdog.h> +#include <asm/io.h> +#include <post.h> + +#if CONFIG_POST & CONFIG_SYS_POST_ECC +/* + * We use the RAW I/O accessors where possible in order to + * achieve performance goal, since the test's execution time + * affects the board start up time. + */ +static inline void ecc_clear(ddr83xx_t *ddr) +{ + /* Clear capture registers */ + __raw_writel(0, &ddr->capture_address); + __raw_writel(0, &ddr->capture_data_hi); + __raw_writel(0, &ddr->capture_data_lo); + __raw_writel(0, &ddr->capture_ecc); + __raw_writel(0, &ddr->capture_attributes); + + /* Clear SBEC and set SBET to 1 */ + out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT); + + /* Clear Error Detect register */ + out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\ + ECC_ERROR_DETECT_MBE |\ + ECC_ERROR_DETECT_SBE |\ + ECC_ERROR_DETECT_MSE); + + isync(); +} + +int ecc_post_test(int flags) +{ + int ret = 0; + int int_state; + int errbit; + u32 pattern[2], writeback[2], retval[2]; + ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; + volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR; + + /* The pattern is written into memory to generate error */ + pattern[0] = 0xfedcba98UL; + pattern[1] = 0x76543210UL; + + /* After injecting error, re-initialize the memory with the value */ + writeback[0] = ~pattern[0]; + writeback[1] = ~pattern[1]; + + /* Check if ECC is enabled */ + if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { + debug("DDR's ECC is not enabled, skipping the ECC POST.\n"); + return 0; + } + + int_state = disable_interrupts(); + icache_enable(); + +#ifdef CONFIG_DDR_32BIT + /* It seems like no one really uses the CONFIG_DDR_32BIT mode */ +#error "Add ECC POST support for CONFIG_DDR_32BIT here!" +#else + for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0; + addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { + + WATCHDOG_RESET(); + + ecc_clear(ddr); + + /* Enable error injection */ + setbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN); + sync(); + isync(); + + /* Set bit to be injected */ + if (errbit < 32) { + __raw_writel(1 << errbit, &ddr->data_err_inject_lo); + __raw_writel(0, &ddr->data_err_inject_hi); + } else { + __raw_writel(0, &ddr->data_err_inject_lo); + __raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi); + } + sync(); + isync(); + + /* Write memory location injecting SBE */ + ppcDWstore((u32*)addr, pattern); + sync(); + + /* Disable error injection */ + clrbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN); + sync(); + isync(); + + /* Data read should generate SBE */ + ppcDWload((u32*)addr, retval); + sync(); + + if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) || + (__raw_readl(&ddr->data_err_inject_hi) != + (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) || + (__raw_readl(&ddr->data_err_inject_lo) != + (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) { + + post_log("ECC failed to detect SBE error at %08x, " + "SBE injection mask %08x-%08x, wrote " + "%08x-%08x, read %08x-%08x\n", addr, + ddr->data_err_inject_hi, + ddr->data_err_inject_lo, + pattern[0], pattern[1], + retval[0], retval[1]); + + printf("ERR_DETECT Reg: %08x\n", ddr->err_detect); + printf("ECC CAPTURE_DATA Reg: %08x-%08x\n", + ddr->capture_data_hi, ddr->capture_data_lo); + ret = 1; + break; + } + + /* Re-initialize the ECC memory */ + ppcDWstore((u32*)addr, writeback); + sync(); + isync(); + + errbit %= 63; + } +#endif /* !CONFIG_DDR_32BIT */ + + ecc_clear(ddr); + + icache_disable(); + + if (int_state) + enable_interrupts(); + + return ret; +} +#endif |