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| author | York Sun <yorksun@freescale.com> | 2012-10-26 16:40:14 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-11-27 18:28:06 -0600 |
| commit | 765ad3cf4d6f60f6104289d05bfa39d562c83859 (patch) | |
| tree | 5483a1fbc3b8e885b3a16cf60149c888609e6ce8 | |
| parent | 0118033b6700fc96a84a8c0593af3cbe2f10a6dc (diff) | |
| download | u-boot-imx-765ad3cf4d6f60f6104289d05bfa39d562c83859.zip u-boot-imx-765ad3cf4d6f60f6104289d05bfa39d562c83859.tar.gz u-boot-imx-765ad3cf4d6f60f6104289d05bfa39d562c83859.tar.bz2 | |
powerpc/corenet_ds: Update DDR timing for single-rank DIMMs
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | board/freescale/corenet_ds/ddr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 4a53b8d..da284cd 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = { {2, 1250, 4, 6, 0xff, 2, 0}, {2, 1350, 5, 7, 0xff, 2, 0}, {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, {1, 1666, 4, 8, 0xff, 2, 0}, {} }; |