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| author | Akshay Saraswat <akshay.s@samsung.com> | 2013-03-22 02:26:36 +0000 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2013-05-21 20:17:30 +0900 |
| commit | 234370cab4b2f096e095fe8f3284fd39740a4023 (patch) | |
| tree | 1ce12817aa13a62f65562f5b9191de5956e4a892 | |
| parent | c7c4fe072eeb95852f4a015df3c1a39b37caae51 (diff) | |
| download | u-boot-imx-234370cab4b2f096e095fe8f3284fd39740a4023.zip u-boot-imx-234370cab4b2f096e095fe8f3284fd39740a4023.tar.gz u-boot-imx-234370cab4b2f096e095fe8f3284fd39740a4023.tar.bz2 | |
Exynos5: clock: Update the equation to calculate PLL output frequency
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 223660a..1203ada 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -116,10 +116,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 1024) * (freq / (p * (1 << s))); } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); } return fout; |