ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455

Signed-off-by: Alison Wang <b18965@freescale.com>

7 files changed, 267 insertions, 243 deletions

diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index 323a54e..adfc708 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -31,14 +31,15 @@
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 	udelay(1000);
-	rcm->rcr |= RCM_RCR_SOFTRST;
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
 	return 0;
@@ -46,14 +47,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 	u16 msk;
 	u16 id = 0;
 	u8 ver;
 
 	puts("CPU:   ");
-	msk = (ccm->cir >> 6);
-	ver = (ccm->cir & 0x003f);
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
 	switch (msk) {
 	case 0x48:
 		id = 54455;
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index fdcd185..3f9209f 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,6 +30,7 @@
 #include <asm/immap.h>
 #include <asm/processor.h>
 #include <asm/rtc.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -46,64 +47,64 @@
  */
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
-	scm1->pacrg = 0;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
 
 	/* FlexBus */
-	gpio->par_be =
-	    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
-	    GPIO_PAR_BE_BE0_BE0;
-	gpio->par_fbctl =
-	    GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
-	    GPIO_PAR_FBCTL_TS_TS;
+	out_8(&gpio->par_be,
+		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+	out_8(&gpio->par_fbctl,
+		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
 
 #if !defined(CONFIG_CF_SBF)
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
 	/* Latch chipselect */
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 	/*
@@ -115,7 +116,8 @@ void cpu_init_f(void)
 		setvbr(CONFIG_SYS_CS0_BASE);
 
 #ifdef CONFIG_FSL_I2C
-	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+	out_be16(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
 #endif
 
 	icache_enable();
@@ -127,11 +129,11 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
-	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+	rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 
-	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
-	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 #endif
 
 	return (0);
@@ -139,40 +141,40 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &=
-		    ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 		break;
 	case 1:
 #ifdef CONFIG_SYS_UART1_PRI_GPIO
-		gpio->par_uart &=
-		    ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
-		gpio->par_ssi &=
-		    (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
-		gpio->par_ssi |=
-		    (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+		clrbits_be16(&gpio->par_ssi,
+			~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
+		setbits_be16(&gpio->par_ssi,
+			GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
 #endif
 		break;
 	case 2:
 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
-		gpio->par_timer &=
-		    (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-		gpio->par_timer &=
-		    (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
 #endif
 		break;
 	}
@@ -181,43 +183,43 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
 	if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_feci2c |=
-			    (GPIO_PAR_FECI2C_MDC0_MDC0 |
-			     GPIO_PAR_FECI2C_MDIO0_MDIO0);
+			setbits_be16(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC0_MDC0 |
+				GPIO_PAR_FECI2C_MDIO0_MDIO0);
 		else
-			gpio->par_feci2c |=
-			    (GPIO_PAR_FECI2C_MDC1_MDC1 |
-			     GPIO_PAR_FECI2C_MDIO1_MDIO1);
+			setbits_be16(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC1_MDC1 |
+				GPIO_PAR_FECI2C_MDIO1_MDIO1);
 #else
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+		setbits_be16(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 #endif
 
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
 		else
-			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
 	} else {
-		gpio->par_feci2c &=
-		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+		clrbits_be16(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 #ifdef CONFIG_SYS_FEC_FULL_MII
-			gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
 #else
-			gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
+			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
 #endif
 		} else {
 #ifdef CONFIG_SYS_FEC_FULL_MII
-			gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
 #else
-			gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
+			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
 #endif
 		}
 	}
@@ -228,43 +230,45 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #ifdef CONFIG_CF_DSPI
 void cfspi_port_conf(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
+	out_8(&gpio->par_dspi,
+		GPIO_PAR_DSPI_SIN_SIN |
+		GPIO_PAR_DSPI_SOUT_SOUT |
+		GPIO_PAR_DSPI_SCK_SCK);
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
 		return -1;
 
 	/* Clear FIFO and resume transfer */
-	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 		break;
 	case 1:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 		break;
 	case 2:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 		break;
 	case 3:
-		gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
-		gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3;
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
 		break;
 	case 5:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 		break;
 	}
 
@@ -273,26 +277,27 @@ int cfspi_claim_bus(uint bus, uint cs)
 
 void cfspi_release_bus(uint bus, uint cs)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+	/* Clear FIFO */
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 		break;
 	case 1:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 		break;
 	case 2:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 		break;
 	case 3:
-		gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
 		break;
 	case 5:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 		break;
 	}
 }
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index 85828a6..a2cf519 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,14 +28,15 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrh0 |= 0xFFFFFFFF;
-	intp->imrl0 |= 0xFFFFFFFF;
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
 
 	enable_interrupts();
 	return 0;
@@ -44,9 +45,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif
diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c
index 7f9784c..c32fcee 100644
--- a/arch/m68k/cpu/mcf5445x/pci.c
+++ b/arch/m68k/cpu/mcf5445x/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -60,78 +60,82 @@ PCI_OP(write, dword, u32, out_le32, 0)
 
 void pci_mcf5445x_init(struct pci_controller *hose)
 {
-	volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
-	volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	pci_t *pci = (pci_t *)MMAP_PCI;
+	pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	u32 barEn = 0;
 
-	pciarb->acr = 0x001F001F;
+	out_be32(&pciarb->acr, 0x001f001f);
 
 	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
 	   PCIREQ2, PCIGNT2 */
-	gpio->par_pci =
-	    GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
-	    GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
-	    GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
+	out_be16(&gpio->par_pci,
+		GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
+		GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
+		GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
+		GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
 
 	/* Assert reset bit */
-	pci->gscr |= PCI_GSCR_PR;
+	setbits_be32(&pci->gscr, PCI_GSCR_PR);
 
-	pci->tcr1 |= PCI_TCR1_P;
+	setbits_be32(&pci->tcr1, PCI_TCR1_P);
 
 	/* Initiator windows */
-	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
-	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
-	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
+	out_be32(&pci->iw0btar,
+		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+	out_be32(&pci->iw1btar,
+		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+	out_be32(&pci->iw2btar,
+		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
 
-	pci->iwcr =
-	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
-	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+	out_be32(&pci->iwcr,
+		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
 
-	pci->icr = 0;
+	out_be32(&pci->icr, 0);
 
 	/* Enable bus master and mem access */
-	pci->scr = PCI_SCR_B | PCI_SCR_M;
+	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
 
 	/* Cache line size and master latency */
-	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
-	pci->cr2 = 0;
+	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
+	out_be32(&pci->cr2, 0);
 
 #ifdef CONFIG_SYS_PCI_BAR0
-	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
-	pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
+	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+	out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B0E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR1
-	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
-	pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
+	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+	out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B1E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR2
-	pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
-	pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
+	out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
+	out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B2E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR3
-	pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
-	pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
+	out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
+	out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B3E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR4
-	pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
-	pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
+	out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
+	out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B4E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR5
-	pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
-	pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
+	out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
+	out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B5E;
 #endif
 
-	pci->tcr2 = barEn;
+	out_be32(&pci->tcr2, barEn);
 
 	/* Deassert reset bit */
-	pci->gscr &= ~PCI_GSCR_PR;
+	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
 	udelay(1000);
 
 	/* Enable PCI bus master support */
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 9c0c077..073b7ef 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void clock_enter_limp(int lpdiv)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
 	int i, j;
 
 	/* Check bounds of divider */
@@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv)
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
 	/* Apply the divider to the system clock */
-	ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
 
 	/* Enable Limp Mode */
-	ccm->misccr |= CCM_MISCCR_LIMP;
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 }
 
 /*
@@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv)
  */
 void clock_exit_limp(void)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 
 	/* Exit Limp mode */
-	ccm->misccr &= ~CCM_MISCCR_LIMP;
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
 	/* Wait for the PLL to lock */
-	while (!(pll->psr & PLL_PSR_LOCK)) ;
+	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+		;
 }
 
 /*
@@ -85,8 +87,8 @@ void clock_exit_limp(void)
 int get_clocks(void)
 {
 
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
 	int pllmult_pci[] = { 12, 6, 16, 8 };
 	int vco = 0, bPci, temp, fbtemp, pcrvalue;
@@ -94,13 +96,13 @@ int get_clocks(void)
 	u16 fbpll_mask;
 
 #ifdef CONFIG_M54455EVB
-	volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
+	u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
 #endif
 	u8 bootmode;
 
 	/* To determine PCI is present or not */
-	if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
-	    ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
+	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
+	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
 		pPllmult = &pllmult_pci[0];
 		fbpll_mask = 3;		/* 11b */
 		bPci = 1;
@@ -114,7 +116,7 @@ int get_clocks(void)
 	}
 
 #ifdef CONFIG_M54455EVB
-	bootmode = (*cpld & 0x03);
+	bootmode = (in_8(cpld) & 0x03);
 
 	if (bootmode != 3) {
 		/* Temporary read from CCR- fixed fb issue, must be the same clock
@@ -122,11 +124,11 @@ int get_clocks(void)
 		fbtemp = pPllmult[ccm->ccr & fbpll_mask];
 
 		/* Break down into small pieces, code still in flex bus */
-		pcrvalue = pll->pcr & 0xFFFFF0FF;
+		pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
 		temp = fbtemp - 1;
 		pcrvalue |= PLL_PCR_OUTDIV3(temp);
 
-		pll->pcr = pcrvalue;
+		out_be32(&pll->pcr, pcrvalue);
 	}
 #endif
 #ifdef CONFIG_M54451EVB
@@ -137,9 +139,10 @@ int get_clocks(void)
 	bootmode = 2;
 
 	/* default value is 16 mul, set to 20 mul */
-	pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
-	pll->pcr = pcrvalue;
-	while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
+	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
+	out_be32(&pll->pcr, pcrvalue);
+	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
+		;
 #endif
 #endif
 
@@ -149,10 +152,10 @@ int get_clocks(void)
 
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* invaild range, re-set in PCR */
-			int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+			int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
 			int i, j, bus;
 
-			j = (pll->pcr & 0xFF000000) >> 24;
+			j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
 			for (i = j; i < 0xFF; i++) {
 				vco = i * CONFIG_SYS_INPUT_CLKSRC;
 				if (vco >= CLOCK_PLL_FVCO_MIN) {
@@ -163,47 +166,47 @@ int get_clocks(void)
 						break;
 				}
 			}
-			pcrvalue = pll->pcr & 0x00FF00FF;
+			pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
 			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
 			pcrvalue |= ((i << 24) | fbtemp);
 
-			pll->pcr = pcrvalue;
+			out_be32(&pll->pcr, pcrvalue);
 		}
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 2) {
 		/* Normal mode */
-		vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* Default value */
-			pcrvalue = (pll->pcr & 0x00FFFFFF);
-			pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
-			pll->pcr = pcrvalue;
-			vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
+			pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
+			out_be32(&pll->pcr, pcrvalue);
+			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		}
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 3) {
 		/* serial mode */
-		vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		gd->vco_clk = vco;	/* Vco clock */
 	}
 
-	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
 		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
 
-		temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
 
-		temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
 		gd->bus_clk = vco / temp;	/* bus clock */
 
-		temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
 		gd->flb_clk = vco / temp;	/* FlexBus clock */
 
 #ifdef CONFIG_PCI
 		if (bPci) {
-			temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
+			temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
 			gd->pci_clk = vco / temp;	/* PCI clock */
 		}
 #endif
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 088c8c4..32a9374 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <spi.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,14 +52,14 @@ phys_size_t initdram(int board_type)
 	 */
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 #else
-	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
-	if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
-	    (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+	if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+	    (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
 		return dramsize;
 
 	for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +68,33 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
 
-	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	udelay(200);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 	__asm__("nop");
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
 
 	/* Issue LEMR */
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
-	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
 
 	udelay(100);
 #endif
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 2a84514..0ca268e 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
 	 */
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
 #else
-	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
@@ -59,33 +60,34 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
 
-	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
-	sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
 
-	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 #endif
@@ -105,26 +107,29 @@ int testdram(void)
 
 int ide_preinit(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
-	gpio->par_feci2c |=
-	    (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
-					   GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
-	gpio->par_ata |=
-	    (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
-	     GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
-	     | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
-	     GPIO_PAR_ATA_IORDY_IORDY);
-	gpio->par_pci |=
-	    (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	u32 tmp;
+
+	tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+	setbits_8(&gpio->par_fec, tmp);
+	tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+		(GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+	setbits_be16(&gpio->par_feci2c, tmp);
+
+	setbits_be16(&gpio->par_ata,
+		GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+		GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+		GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+		GPIO_PAR_ATA_IORDY_IORDY);
+	setbits_be16(&gpio->par_pci,
+		GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
 
 	return (0);
 }
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) MMAP_ATA;
+	atac_t *ata = (atac_t *) MMAP_ATA;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = {
@@ -136,24 +141,27 @@ void ide_set_reset(int idereset)
 	};			/* PIO 4 */
 
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(10000);
 	} else {
 #define CALC_TIMING(t) (t + period - 1) / period
 		period = 1000000000 / gd->bus_clk;	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
-
-		ata->cr = 0x40;	/* IORDY enable */
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(200000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif