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| author | Markus Niebel <Markus.Niebel@tq-group.de> | 2014-02-17 17:33:16 +0100 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jaganna@xilinx.com> | 2014-02-18 22:29:26 +0530 |
| commit | d7cbcc762ea88ad20e9005a85bf7d55939b5e9d2 (patch) | |
| tree | 87e832cfc63d3b86740e689a17a6b22d81bca5c9 | |
| parent | 999c39a45f115a17f6b894e3a9cd894c598fb2e0 (diff) | |
| download | u-boot-imx-d7cbcc762ea88ad20e9005a85bf7d55939b5e9d2.zip u-boot-imx-d7cbcc762ea88ad20e9005a85bf7d55939b5e9d2.tar.gz u-boot-imx-d7cbcc762ea88ad20e9005a85bf7d55939b5e9d2.tar.bz2 | |
spi: spi-mxc: add defines for clk inactive state for ECSPI
Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 7 |
2 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 4955ccf..054c680 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -230,9 +230,10 @@ #define MXC_CSPICTRL_CHAN 18 /* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #define MXC_SPI_BASE_ADDRESSES \ CSPI1_BASE_ADDR, \ CSPI2_BASE_ADDR, \ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index f2ad6e9..3c58c01 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -405,9 +405,10 @@ struct cspi_regs { #define MXC_CSPICTRL_CHAN 18 /* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #ifdef CONFIG_MX6SL #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ |