diff options
| author | Simon Glass <sjg@chromium.org> | 2012-07-29 20:53:25 +0000 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2012-09-07 13:54:30 -0700 |
| commit | b572595ee95829ab62e354c55a8fbd0f4db23935 (patch) | |
| tree | 18ce59921123f5b98f47e4845bef96f191593cd4 | |
| parent | 057df193b40d31799d41d43bc832a972f658bfe4 (diff) | |
| download | u-boot-imx-b572595ee95829ab62e354c55a8fbd0f4db23935.zip u-boot-imx-b572595ee95829ab62e354c55a8fbd0f4db23935.tar.gz u-boot-imx-b572595ee95829ab62e354c55a8fbd0f4db23935.tar.bz2 | |
nand: Try to align the default buffers
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
| -rw-r--r-- | drivers/mtd/nand/nand_base.c | 3 | ||||
| -rw-r--r-- | include/linux/mtd/nand.h | 7 |
2 files changed, 6 insertions, 4 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index bfd668f..891af1f 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd) struct nand_chip *chip = mtd->priv; if (!(chip->options & NAND_OWN_BUFFERS)) - chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); + chip->buffers = memalign(ARCH_DMA_MINALIGN, + sizeof(*chip->buffers)); if (!chip->buffers) return -ENOMEM; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 82704de..dc839e7 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -391,9 +391,10 @@ struct nand_ecc_ctrl { * consecutive order. */ struct nand_buffers { - uint8_t ecccalc[NAND_MAX_OOBSIZE]; - uint8_t ecccode[NAND_MAX_OOBSIZE]; - uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; + uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, + ARCH_DMA_MINALIGN)]; }; /** |