diff options
author | Nitin Garg <nitin.garg@freescale.com> | 2014-05-27 21:09:21 -0500 |
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committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-13 10:17:01 -0500 |
commit | 230871db5538f69c101db7d5695c37f282bd641d (patch) | |
tree | 29029365cc22b3b6178a08801d59dc7f09c6130f | |
parent | 9887413a1bc0554469f20e3b4511878881563dfc (diff) | |
download | u-boot-imx-230871db5538f69c101db7d5695c37f282bd641d.zip u-boot-imx-230871db5538f69c101db7d5695c37f282bd641d.tar.gz u-boot-imx-230871db5538f69c101db7d5695c37f282bd641d.tar.bz2 |
ENGR00315499-16 I2C: add I2C support on Sabre- board
- add I2C support on Sabresd ,Sabreauto board.
- add pfuze init code based on I2C transfer in Sabre* board file.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
-rw-r--r-- | board/freescale/mx6qsabreauto/mx6qsabreauto.c | 81 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 126 |
2 files changed, 206 insertions, 1 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index eb289c4..5e277aa 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. * * Author: Fabio Estevam <fabio.estevam@freescale.com> * @@ -33,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define I2C_EXP_RST IMX_GPIO_NR(1, 15) +#define I2C3_STEER IMX_GPIO_NR(5, 4) #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -157,6 +159,72 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#ifdef CONFIG_SYS_I2C_MXC +static int setup_pmic_voltages(void) +{ + unsigned char value, rev_id = 0 ; + i2c_set_bus_num(1); + if (!i2c_probe(0x8)) { + if (i2c_read(0x8, 0, 1, &value, 1)) { + printf("Read device ID error!\n"); + return -1; + } + if (i2c_read(0x8, 3, 1, &rev_id, 1)) { + printf("Read Rev ID error!\n"); + return -1; + } + printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id); + /* set SW1AB staby volatage 0.975V*/ + if (i2c_read(0x8, 0x21, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0x3f; + value |= 0x1b; + if (i2c_write(0x8, 0x21, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + if (i2c_read(0x8, 0x24, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0xc0; + value |= 0x40; + if (i2c_write(0x8, 0x24, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + + /* set SW1C staby volatage 0.975V*/ + if (i2c_read(0x8, 0x2f, 1, &value, 1)) { + printf("Read SW1CSTBY error!\n"); + return -1; + } + value &= ~0x3f; + value |= 0x1b; + if (i2c_write(0x8, 0x2f, 1, &value, 1)) { + printf("Set SW1CSTBY error!\n"); + return -1; + } + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + if (i2c_read(0x8, 0x32, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0xc0; + value |= 0x40; + if (i2c_write(0x8, 0x32, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + } + + return 0; +} + #ifdef CONFIG_LDO_BYPASS_CHECK void ldo_mode_set(int ldo_bypass) { @@ -190,6 +258,7 @@ void ldo_mode_set(int ldo_bypass) } } #endif +#endif static void setup_iomux_uart(void) { @@ -402,9 +471,19 @@ static const struct boot_mode board_boot_modes[] = { int board_late_init(void) { + int ret; #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(1, CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, &i2c_pad_info1); + ret = setup_pmic_voltages(); + if (ret) + return -1; +#endif + #ifdef CONFIG_ENV_IS_IN_MMC board_late_mmc_env_init(); #endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5501db9..b368492 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -56,9 +56,31 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 Camera, MIPI, pfuze */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; +#endif + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -223,6 +245,100 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +#ifdef CONFIG_SYS_I2C_MXC +static int setup_pmic_voltages(void) +{ + unsigned char value, rev_id = 0 ; + + i2c_set_bus_num(1); + if (!i2c_probe(0x8)) { + if (i2c_read(0x8, 0, 1, &value, 1)) { + printf("Read device ID error!\n"); + return -1; + } + if (i2c_read(0x8, 3, 1, &rev_id, 1)) { + printf("Read Rev ID error!\n"); + return -1; + } + printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id); + /*For camera streaks issue,swap VGEN5 and VGEN3 to power camera. + *sperate VDDHIGH_IN and camera 2.8V power supply, after switch: + *VGEN5 for VDDHIGH_IN and increase to 3V to align with datasheet + *VGEN3 for camera 2.8V power supply + */ + /*increase VGEN3 from 2.5 to 2.8V*/ + if (i2c_read(0x8, 0x6e, 1, &value, 1)) { + printf("Read VGEN3 error!\n"); + return -1; + } + value &= ~0xf; + value |= 0xa; + if (i2c_write(0x8, 0x6e, 1, &value, 1)) { + printf("Set VGEN3 error!\n"); + return -1; + } + /*increase VGEN5 from 2.8 to 3V*/ + if (i2c_read(0x8, 0x70, 1, &value, 1)) { + printf("Read VGEN5 error!\n"); + return -1; + } + value &= ~0xf; + value |= 0xc; + if (i2c_write(0x8, 0x70, 1, &value, 1)) { + printf("Set VGEN5 error!\n"); + return -1; + } + /* set SW1AB staby volatage 0.975V*/ + if (i2c_read(0x8, 0x21, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0x3f; + value |= 0x1b; + if (i2c_write(0x8, 0x21, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + if (i2c_read(0x8, 0x24, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0xc0; + value |= 0x40; + if (i2c_write(0x8, 0x24, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + + /* set SW1C staby volatage 0.975V*/ + if (i2c_read(0x8, 0x2f, 1, &value, 1)) { + printf("Read SW1CSTBY error!\n"); + return -1; + } + value &= ~0x3f; + value |= 0x1b; + if (i2c_write(0x8, 0x2f, 1, &value, 1)) { + printf("Set SW1CSTBY error!\n"); + return -1; + } + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + if (i2c_read(0x8, 0x32, 1, &value, 1)) { + printf("Read SW1ABSTBY error!\n"); + return -1; + } + value &= ~0xc0; + value |= 0x40; + if (i2c_write(0x8, 0x32, 1, &value, 1)) { + printf("Set SW1ABSTBY error!\n"); + return -1; + } + } + + return 0; +} + #ifdef CONFIG_LDO_BYPASS_CHECK void ldo_mode_set(int ldo_bypass) { @@ -284,6 +400,7 @@ void ldo_mode_set(int ldo_bypass) } } #endif +#endif #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[3] = { @@ -665,10 +782,19 @@ static const struct boot_mode board_boot_modes[] = { int board_late_init(void) { + int ret = 0; #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(1, CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, &i2c_pad_info1); + ret = setup_pmic_voltages(); + if (ret) + return -1; +#endif + #ifdef CONFIG_ENV_IS_IN_MMC board_late_mmc_env_init(); #endif |