summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorYe.Li <B37916@freescale.com>2014-06-24 11:20:03 +0800
committerYe.Li <B37916@freescale.com>2014-06-25 18:57:14 +0800
commit115ec908f5f4425aabcd26071212fa48073890c3 (patch)
treea44a16f8424afa2e35867d10b7de50bbfb41d466
parent8b8630ada916304bbc5612acf76d81d981c0365b (diff)
downloadu-boot-imx-115ec908f5f4425aabcd26071212fa48073890c3.zip
u-boot-imx-115ec908f5f4425aabcd26071212fa48073890c3.tar.gz
u-boot-imx-115ec908f5f4425aabcd26071212fa48073890c3.tar.bz2
ENGR00319772 iMX6SX:ARM2: Add EIM-NOR support for 17x17 ARM2 board
The NOR flash PC28F00AG18 has 512 of 256KB erase blocks which are locked after power on reset. Change the 17x17 ARM2 configurations to match the flash parameters, and enable the CONFIG_SYS_FLASH_PROTECTION to allow write to the flash. The EIM-NOR on 17x17 ARM2 board uses MUXed mode. This has less effort on board rework. When boot from EIM-NOR, set SW8, SW7, SW5 to all off. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit da0e5e9e12c79a250002c1b442e25f93603f9695)
Diffstat
-rw-r--r--board/freescale/mx6sx_17x17_arm2/imximage.cfg2
-rw-r--r--board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c67
-rw-r--r--boards.cfg1
-rw-r--r--include/configs/mx6sx_17x17_arm2.h9
4 files changed, 79 insertions, 0 deletions
diff --git a/board/freescale/mx6sx_17x17_arm2/imximage.cfg b/board/freescale/mx6sx_17x17_arm2/imximage.cfg
index d8bbeb0..f98acb0 100644
--- a/board/freescale/mx6sx_17x17_arm2/imximage.cfg
+++ b/board/freescale/mx6sx_17x17_arm2/imximage.cfg
@@ -23,6 +23,8 @@ IMAGE_VERSION 2
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM nor
#else
BOOT_FROM sd
#endif
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
index 703db49..a793049 100644
--- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
+++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
@@ -59,6 +59,14 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm)
+
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -370,6 +378,61 @@ void setup_spinor(void)
}
#endif
+#ifdef CONFIG_SYS_USE_EIMNOR
+iomux_v3_cfg_t eimnor_pads[] = {
+ MX6SX_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+ MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+ MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6SX_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ MX6SX_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+};
+static void eimnor_cs_setup(void)
+{
+ writel(0x00000120, WEIM_BASE_ADDR + 0x090);
+ writel(0x00610089, WEIM_BASE_ADDR + 0x000);
+ writel(0x00000001, WEIM_BASE_ADDR + 0x004);
+ writel(0x1c022000, WEIM_BASE_ADDR + 0x008);
+ writel(0x00000000, WEIM_BASE_ADDR + 0x00c);
+ writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
+}
+
+static void setup_eimnor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(eimnor_pads,
+ ARRAY_SIZE(eimnor_pads));
+
+ eimnor_cs_setup();
+}
+#endif
+
#ifdef CONFIG_SYS_USE_NAND
iomux_v3_cfg_t gpmi_pads[] = {
MX6SX_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
@@ -665,6 +728,10 @@ int board_init(void)
setup_spinor();
#endif
+#ifdef CONFIG_SYS_USE_EIMNOR
+ setup_eimnor();
+#endif
+
#ifdef CONFIG_SYS_USE_NAND
setup_gpmi_nand();
#endif
diff --git a/boards.cfg b/boards.cfg
index aa8b7d6..25948b2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -353,6 +353,7 @@ Active arm armv7 mx6 freescale mx6sx_17x17_arm2
Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_17x17_arm2_spinor mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb",SYS_BOOT_SPINOR Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_17x17_arm2_nand mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb",SYS_BOOT_NAND Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_17x17_arm2_qspi2 mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb",SYS_BOOT_QSPI Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6sx_17x17_arm2 mx6sx_17x17_arm2_eimnor mx6sx_17x17_arm2:IMX_CONFIG=board/freescale/mx6sx_17x17_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-17x17-arm2.dtb",SYS_BOOT_EIMNOR Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sx_19x19_arm2 mx6sx_19x19_ddr3_arm2 mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb" Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sx_19x19_arm2 mx6sx_19x19_ddr3_arm2_qspi2 mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb",SYS_BOOT_QSPI
Active arm armv7 mx6 freescale mx6sx_19x19_arm2 mx6sx_19x19_ddr3_arm2_spinor mx6sx_19x19_arm2:IMX_CONFIG=board/freescale/mx6sx_19x19_arm2/imximage.cfg,MX6SX,DEFAULT_FDT_FILE="imx6sx-19x19-arm2.dtb",SYS_BOOT_SPINOR
diff --git a/include/configs/mx6sx_17x17_arm2.h b/include/configs/mx6sx_17x17_arm2.h
index e5bae55..9db44cf 100644
--- a/include/configs/mx6sx_17x17_arm2.h
+++ b/include/configs/mx6sx_17x17_arm2.h
@@ -20,4 +20,13 @@
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#endif
+
+#ifdef CONFIG_SYS_USE_EIMNOR
+#undef CONFIG_SYS_FLASH_SECT_SIZE
+#undef CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_PROTECTION
+#endif
+
#endif
generated by cgit v1.1 at 2024-11-24 02:09:43 +0000