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| author | Daniel Mack <daniel@caiaq.de> | 2009-06-23 17:30:05 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-07-12 17:43:32 +0200 |
| commit | c33c5990cec7ced9ef1ef148debbca34adafa12b (patch) | |
| tree | c2879e1aac68ea58e09c681f0c4d3fca24c5bb1a | |
| parent | bd876be46f28b5fc2896537f6d01353f332789f7 (diff) | |
| download | u-boot-imx-c33c5990cec7ced9ef1ef148debbca34adafa12b.zip u-boot-imx-c33c5990cec7ced9ef1ef148debbca34adafa12b.tar.gz u-boot-imx-c33c5990cec7ced9ef1ef148debbca34adafa12b.tar.bz2 | |
pxa: fix CKEN_B register bits
The current defition for CKEN_B register bits is nonsense. Adding 32 to
the shifted value is equal to '| (1 << 5)', and this bit is marked
'reserved' in the PXA docs.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 1f81e11..2a723dc 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1953,12 +1953,12 @@ typedef void (*ExcpHndlr) (void) ; #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ #define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ -#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ +#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ +#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ #else /* if defined CONFIG_CPU_MONAHANS */ |