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authorJay Monkman <jay.monkman@freescale.com>2014-04-15 12:19:32 -0500
committerJay Monkman <jay.monkman@freescale.com>2014-04-15 12:20:47 -0500
commit9d3bd9da11fd7f35d818fe8d8c15c2906175df19 (patch)
tree66bad75833c3e2cc33da310043a841ccb248392a
parent43d71693e88fc221219b5710eb89a15971f5627b (diff)
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ENGR00297869: Image authentication is slow in u-boot-2013.04
authenticate_image() is slower than necessary since caching is not enabled for OCRAM and Boot ROM. This patch turns them on. It also sets the pu_irom_mmu_enabled bit in OCRAM so that ROM code will properly flush caches. Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 9569038..d8942a6 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -436,8 +436,10 @@ void enable_caches(void)
{
/* Avoid random hang when download by usb */
invalidate_dcache_all();
+
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
+
}
#endif
@@ -895,6 +897,42 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+
+ /*
+ * If the MMU is enabled, we have to notify the ROM code, or
+ * it won't flush the caches when needed. This is done by
+ * setting the "pu_irom_mmu_enabled" word to 1. You can find
+ * its address by looking in the ROM map.
+ *
+ * This is critical for authenticate_image(). If MMU is enabled
+ * without setting this bit, authentication will fail and may
+ * crash.
+ *
+ * This is no longer needed in CPUs starting with i.MX6SX.
+ */
+ if (is_mx6dq()) {
+ /* Will not work for rev 1.0.0 of the CPU */
+ writel(1, 0x009024a8);
+ } else if (is_mx6solo() || is_mx6dlsolo()) {
+ writel(1, 0x00901dd0);
+ } else if (is_mx6sl()) {
+ writel(1, 0x00900a18);
+ }
+
+ /* Enable caching on OCRAM and ROM */
+ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+ ROMCP_ARB_END_ADDR,
+ option);
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+ IRAM_SIZE,
+ option);
+
+
hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
hab_rvt_entry = hab_rvt_entry_p;
hab_rvt_exit = hab_rvt_exit_p;