Merge remote branch 'u-boot-avr32/master'

33 files changed, 817 insertions, 564 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index cc88762..d608a6b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -699,6 +699,7 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
 	ATSTK1002		AT32AP7000
 	ATSTK1003		AT32AP7001
 	ATSTK1004		AT32AP7002
+	ATSTK1006		AT32AP7000
 	ATNGW100		AT32AP7000
 
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 4bf6d4d..aad681f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -698,6 +698,7 @@ LIST_avr32="		\
 	atstk1002	\
 	atstk1003	\
 	atstk1004	\
+	atstk1006	\
 	atngw100	\
 "
 
diff --git a/Makefile b/Makefile
index 04cebac..543c57b 100644
--- a/Makefile
+++ b/Makefile
@@ -2882,6 +2882,9 @@ atstk1003_config	:	unconfig
 atstk1004_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
 
+atstk1006_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
 atngw100_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x
 
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index 1ccbe2c..c649855 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -25,12 +25,12 @@
 #include <asm/sdram.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix2.h>
+#include <asm/arch/hmatrix.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_16BIT,
 	.row_bits	= 13,
 	.col_bits	= 9,
 	.bank_bits	= 2,
@@ -47,8 +47,8 @@ static const struct sdram_info sdram = {
 
 int board_early_init_f(void)
 {
-	/* Set the SDRAM_ENABLE bit in the HEBI SFR */
-	hmatrix2_writel(SFR4, 1 << 1);
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
 
 	gpio_enable_ebi();
 	gpio_enable_usart1();
@@ -66,7 +66,22 @@ int board_early_init_f(void)
 
 long int initdram(int board_type)
 {
-	return sdram_init(&sdram);
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %u of %u MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
 }
 
 void board_init_info(void)
diff --git a/board/atmel/atngw100/u-boot.lds b/board/atmel/atngw100/u-boot.lds
index 34e347a..e736adf 100644
--- a/board/atmel/atngw100/u-boot.lds
+++ b/board/atmel/atngw100/u-boot.lds
@@ -29,17 +29,10 @@ SECTIONS
 	. = 0;
 	_text = .;
 	.text : {
+		*(.exception.text)
 		*(.text)
 		*(.text.*)
 	}
-
-	. = ALIGN(32);
-	__flashprog_start = .;
-	.flashprog : {
-		*(.flashprog)
-	}
-	. = ALIGN(32);
-	__flashprog_end = .;
 	_etext = .;
 
 	.rodata : {
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
index 28f64c4..33bdba6 100644
--- a/board/atmel/atstk1000/atstk1000.c
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -25,13 +25,39 @@
 #include <asm/sdram.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix2.h>
+#include <asm/arch/hmatrix.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
+static const struct sdram_config sdram_config = {
+#if defined(CONFIG_ATSTK1006)
+	/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 2,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 4,
+	.txsr		= 7,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+#else
+	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
+#ifdef CONFIG_ATSTK1004
+	.data_bits	= SDRAM_DATA_16BIT,
+#else
+	.data_bits	= SDRAM_DATA_32BIT,
+#endif
+#ifdef CONFIG_ATSTK1000_16MB_SDRAM
+	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
+	.row_bits	= 12,
+#else
 	.row_bits	= 11,
+#endif
 	.col_bits	= 8,
 	.bank_bits	= 2,
 	.cas		= 3,
@@ -43,12 +69,13 @@ static const struct sdram_info sdram = {
 	.txsr		= 5,
 	/* 15.6 us */
 	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+#endif
 };
 
 int board_early_init_f(void)
 {
-	/* Set the SDRAM_ENABLE bit in the HEBI SFR */
-	hmatrix2_writel(SFR4, 1 << 1);
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
 
 	gpio_enable_ebi();
 	gpio_enable_usart1();
@@ -65,7 +92,22 @@ int board_early_init_f(void)
 
 long int initdram(int board_type)
 {
-	return sdram_init(&sdram);
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %u of %u MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
 }
 
 void board_init_info(void)
diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c
index 4047825..12537f3 100644
--- a/board/atmel/atstk1000/flash.c
+++ b/board/atmel/atstk1000/flash.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 flash_info_t flash_info[1];
 
-static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
+static void flash_identify(uint16_t *flash, flash_info_t *info)
 {
 	unsigned long flags;
 
@@ -76,7 +76,7 @@ void flash_print_info(flash_info_t *info)
 	       info->size >> 10, info->sector_count);
 }
 
-int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
 	unsigned long flags;
 	unsigned long start_time;
@@ -154,7 +154,7 @@ int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
 	return ERR_OK;
 }
 
-int __flashprog write_buff(flash_info_t *info, uchar *src,
+int write_buff(flash_info_t *info, uchar *src,
 			   ulong addr, ulong count)
 {
 	unsigned long flags;
diff --git a/board/atmel/atstk1000/u-boot.lds b/board/atmel/atstk1000/u-boot.lds
index 247812e..0d3b19c 100644
--- a/board/atmel/atstk1000/u-boot.lds
+++ b/board/atmel/atstk1000/u-boot.lds
@@ -29,17 +29,10 @@ SECTIONS
 	. = 0;
 	_text = .;
 	.text : {
+		*(.exception.text)
 		*(.text)
 		*(.text.*)
 	}
-
-	. = ALIGN(32);
-	__flashprog_start = .;
-	.flashprog : {
-		*(.flashprog)
-	}
-	. = ALIGN(32);
-	__flashprog_end = .;
 	_etext = .;
 
 	.rodata : {
diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index f69b1f3..d16c58b 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -27,13 +27,19 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(CPU).a
 
-START	:= start.o
-SOBJS	:= entry.o
-COBJS	:= cpu.o hsdramc.o exception.o cache.o
-COBJS	+= interrupts.o pio.o atmel_mci.o
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
+START-y			+= start.o
+
+COBJS-y			+= cpu.o
+COBJS-y			+= hsdramc.o
+COBJS-y			+= exception.o
+COBJS-y			+= cache.o
+COBJS-y			+= interrupts.o
+COBJS-y			+= pio.o
+COBJS-$(CONFIG_MMC)	+= atmel_mci.o
+
+SRCS	:= $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START	:= $(addprefix $(obj),$(START-y))
 
 all: $(obj).depend $(START) $(LIB)
 
diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile
index d276712..7404235 100644
--- a/cpu/at32ap/at32ap700x/Makefile
+++ b/cpu/at32ap/at32ap700x/Makefile
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(SOC).a
 
-COBJS	:= gpio.o
+COBJS	:= gpio.o clk.o
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c
new file mode 100644
index 0000000..b3aa034
--- /dev/null
+++ b/cpu/at32ap/at32ap700x/clk.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2005-2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/memory-map.h>
+
+#include "sm.h"
+
+void clk_init(void)
+{
+	uint32_t cksel;
+
+	/* in case of soft resets, disable watchdog */
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
+
+#ifdef CONFIG_PLL
+	/* Initialize the PLL */
+	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+			    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+			    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+			    | SM_BF(PLLOPT, CFG_PLL0_OPT)
+			    | SM_BF(PLLOSC, 0)
+			    | SM_BIT(PLLEN)));
+
+	/* Wait for lock */
+	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
+#endif
+
+	/* Set up clocks for the CPU and all peripheral buses */
+	cksel = 0;
+	if (CFG_CLKDIV_CPU)
+		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+	if (CFG_CLKDIV_HSB)
+		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+	if (CFG_CLKDIV_PBA)
+		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+	if (CFG_CLKDIV_PBB)
+		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+	sm_writel(PM_CKSEL, cksel);
+
+#ifdef CONFIG_PLL
+	/* Use PLL0 as main clock */
+	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}
diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/at32ap700x/sm.h
index 6492c8e..6492c8e 100644
--- a/cpu/at32ap/sm.h
+++ b/cpu/at32ap/at32ap700x/sm.h
diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c
index f59dfb5..3795add 100644
--- a/cpu/at32ap/atmel_mci.c
+++ b/cpu/at32ap/atmel_mci.c
@@ -21,8 +21,6 @@
  */
 #include <common.h>
 
-#ifdef CONFIG_MMC
-
 #include <part.h>
 #include <mmc.h>
 
@@ -139,7 +137,7 @@ mmc_cmd(unsigned long cmd, unsigned long arg,
 
 	pr_debug("mmc: status 0x%08lx\n", status);
 
-	if (status & ERROR_FLAGS) {
+	if (status & error_flags) {
 		printf("mmc: command %lu failed (status: 0x%08lx)\n",
 		       cmd, status);
 		return -EIO;
@@ -182,12 +180,13 @@ static int mmc_acmd(unsigned long cmd, unsigned long arg,
 
 static unsigned long
 mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
-	  unsigned long *buffer)
+	  void *buffer)
 {
 	int ret, i = 0;
 	unsigned long resp[4];
 	unsigned long card_status, data;
 	unsigned long wordcount;
+	u32 *p = buffer;
 	u32 status;
 
 	if (blkcnt == 0)
@@ -225,7 +224,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
 			if (status & MMCI_BIT(RXRDY)) {
 				data = mmci_readl(RDR);
 				/* pr_debug("%x\n", data); */
-				*buffer++ = data;
+				*p++ = data;
 				wordcount++;
 			}
 		} while(wordcount < (mmc_blkdev.blksz / 4));
@@ -443,6 +442,7 @@ static void mci_set_data_timeout(struct mmc_csd *csd)
 
 	dtocyc = timeout_clks;
 	dtomul = 0;
+	shift = 0;
 	while (dtocyc > 15 && dtomul < 8) {
 		dtomul++;
 		shift = dtomul_to_shift[dtomul];
@@ -546,5 +546,3 @@ int mmc2info(ulong addr)
 {
 	return 0;
 }
-
-#endif /* CONFIG_MMC */
diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index 311466b..0ba8361 100644
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -30,7 +30,6 @@
 #include <asm/arch/memory-map.h>
 
 #include "hsmc3.h"
-#include "sm.h"
 
 /* Sanity checks */
 #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)		\
@@ -44,47 +43,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void pm_init(void)
-{
-	uint32_t cksel;
-
-#ifdef CONFIG_PLL
-	/* Initialize the PLL */
-	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
-			    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
-			    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
-			    | SM_BF(PLLOPT, CFG_PLL0_OPT)
-			    | SM_BF(PLLOSC, 0)
-			    | SM_BIT(PLLEN)));
-
-	/* Wait for lock */
-	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
-	/* Set up clocks for the CPU and all peripheral buses */
-	cksel = 0;
-	if (CFG_CLKDIV_CPU)
-		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
-	if (CFG_CLKDIV_HSB)
-		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
-	if (CFG_CLKDIV_PBA)
-		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
-	if (CFG_CLKDIV_PBB)
-		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
-	sm_writel(PM_CKSEL, cksel);
-
-	gd->cpu_hz = get_cpu_clk_rate();
-
-#ifdef CONFIG_PLL
-	/* Use PLL0 as main clock */
-	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-#endif
-}
-
 int cpu_init(void)
 {
 	extern void _evba(void);
-	char *p;
 
 	gd->cpu_hz = CFG_OSC0_HZ;
 
@@ -95,16 +56,15 @@ int cpu_init(void)
 	hsmc3_writel(PULSE0, 0x0b0a0906);
 	hsmc3_writel(SETUP0, 0x00010002);
 
-	pm_init();
+	clk_init();
 
+	/* Update the CPU speed according to the PLL configuration */
+	gd->cpu_hz = get_cpu_clk_rate();
+
+	/* Set up the exception handler table and enable exceptions */
 	sysreg_write(EVBA, (unsigned long)&_evba);
 	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
 
-	/* Lock everything that mess with the flash in the icache */
-	for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
-	     p += CFG_ICACHE_LINESZ)
-		asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
-
 	return 0;
 }
 
diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S
deleted file mode 100644
index a6fc688..0000000
--- a/cpu/at32ap/entry.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <asm/sysreg.h>
-#include <asm/ptrace.h>
-
-	.section .text.exception,"ax"
-	.global	_evba
-	.type	_evba,@function
-	.align	10
-_evba:
-	.irp	x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
-	.align	2
-	rjmp	unknown_exception
-	.endr
-
-	.global	timer_interrupt_handler
-	.type	timer_interrupt_handler,@function
-	.align	2
-timer_interrupt_handler:
-	/*
-	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
-	 *
-	 * We're running at interrupt level 3, so we don't need to save
-	 * r8-r12 or lr to the stack.
-	 */
-	lda.w	r8, timer_overflow
-	ld.w	r9, r8[0]
-	mov	r10, -1
-	mtsr	SYSREG_COMPARE, r10
-	sub	r9, -1
-	st.w	r8[0], r9
-	rete
-
-	.type	unknown_exception, @function
-unknown_exception:
-	pushm	r0-r12
-	sub	r8, sp, REG_R12 - REG_R0 - 4
-	mov	r9, lr
-	mfsr	r10, SYSREG_RAR_EX
-	mfsr	r11, SYSREG_RSR_EX
-	pushm	r8-r11
-	mfsr	r12, SYSREG_ECR
-	mov	r11, sp
-	rcall	do_unknown_exception
-1:	rjmp	1b
diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c
index 0672685..dc9c300 100644
--- a/cpu/at32ap/exception.c
+++ b/cpu/at32ap/exception.c
@@ -111,7 +111,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
 	printf("CPU Mode: %s\n", cpu_modes[mode]);
 
 	/* Avoid exception loops */
-	if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end)
+	if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
+			|| regs->sp >= gd->stack_end)
 		printf("\nStack pointer seems bogus, won't do stack dump\n");
 	else
 		dump_mem("\nStack: ", regs->sp, gd->stack_end);
diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c
index 1fcfe75..992612b 100644
--- a/cpu/at32ap/hsdramc.c
+++ b/cpu/at32ap/hsdramc.c
@@ -30,39 +30,32 @@
 
 #include "hsdramc1.h"
 
-unsigned long sdram_init(const struct sdram_info *info)
+unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
 {
-	unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
 	unsigned long sdram_size;
-	unsigned long tmp;
-	unsigned long bus_hz;
+	uint32_t cfgreg;
 	unsigned int i;
 
-	if (!info->refresh_period)
-		panic("ERROR: SDRAM refresh period == 0. "
-				"Please update the board code\n");
-
-	tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
-	       | HSDRAMC1_BF(NR, info->row_bits - 11)
-	       | HSDRAMC1_BF(NB, info->bank_bits - 1)
-	       | HSDRAMC1_BF(CAS, info->cas)
-	       | HSDRAMC1_BF(TWR, info->twr)
-	       | HSDRAMC1_BF(TRC, info->trc)
-	       | HSDRAMC1_BF(TRP, info->trp)
-	       | HSDRAMC1_BF(TRCD, info->trcd)
-	       | HSDRAMC1_BF(TRAS, info->tras)
-	       | HSDRAMC1_BF(TXSR, info->txsr));
-
-#ifdef CFG_SDRAM_16BIT
-	tmp |= HSDRAMC1_BIT(DBW);
-	sdram_size = 1 << (info->row_bits + info->col_bits
-			   + info->bank_bits + 1);
-#else
-	sdram_size = 1 << (info->row_bits + info->col_bits
-			   + info->bank_bits + 2);
-#endif
-
-	hsdramc1_writel(CR, tmp);
+	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
+		       | HSDRAMC1_BF(NR, config->row_bits - 11)
+		       | HSDRAMC1_BF(NB, config->bank_bits - 1)
+		       | HSDRAMC1_BF(CAS, config->cas)
+		       | HSDRAMC1_BF(TWR, config->twr)
+		       | HSDRAMC1_BF(TRC, config->trc)
+		       | HSDRAMC1_BF(TRP, config->trp)
+		       | HSDRAMC1_BF(TRCD, config->trcd)
+		       | HSDRAMC1_BF(TRAS, config->tras)
+		       | HSDRAMC1_BF(TXSR, config->txsr));
+
+	if (config->data_bits == SDRAM_DATA_16BIT)
+		cfgreg |= HSDRAMC1_BIT(DBW);
+
+	hsdramc1_writel(CR, cfgreg);
+
+	/* Send a NOP to turn on the clock (necessary on some chips) */
+	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
+	hsdramc1_readl(MR);
+	writel(0, sdram_base);
 
 	/*
 	 * Initialization sequence for SDRAM, from the data sheet:
@@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info)
 	 */
 	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
 	hsdramc1_readl(MR);
-	writel(0, sdram);
+	writel(0, sdram_base);
 
 	/*
 	 * 3. Eight auto-refresh (CBR) cycles are provided
@@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info)
 	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
 	hsdramc1_readl(MR);
 	for (i = 0; i < 8; i++)
-		writel(0, sdram);
+		writel(0, sdram_base);
 
 	/*
 	 * 4. A mode register set (MRS) cycle is issued to program
 	 *    SDRAM parameters, in particular CAS latency and burst
 	 *    length.
 	 *
-	 * CAS from info struct, burst length 1, serial burst type
+	 * The address will be chosen by the SDRAMC automatically; we
+	 * just have to make sure BA[1:0] are set to 0.
 	 */
 	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
 	hsdramc1_readl(MR);
-	writel(0, sdram + (info->cas << 4));
+	writel(0, sdram_base);
 
 	/*
-	 * 5. A Normal Mode command is provided, 3 clocks after tMRD
-	 *    is met.
-	 *
-	 * From the timing diagram, it looks like tMRD is 3
-	 * cycles...try a dummy read from the peripheral bus.
+	 * 5. The application must go into Normal Mode, setting Mode
+	 *    to 0 in the Mode Register and performing a write access
+	 *    at any location in the SDRAM.
 	 */
-	hsdramc1_readl(MR);
 	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
 	hsdramc1_readl(MR);
-	writel(0, sdram);
+	writel(0, sdram_base);
 
 	/*
 	 * 6. Write refresh rate into SDRAMC refresh timer count
 	 *    register (refresh rate = timing between refresh cycles).
-	 *
-	 * 15.6 us is a typical value for a burst of length one
 	 */
-	bus_hz = get_sdram_clk_rate();
-	hsdramc1_writel(TR, info->refresh_period);
-
-	printf("SDRAM: %u MB at address 0x%08lx\n",
-	       sdram_size >> 20, info->phys_addr);
-
-	printf("Testing SDRAM...");
-	for (i = 0; i < sdram_size / 4; i++)
-		sdram[i] = i;
-
-	for (i = 0; i < sdram_size / 4; i++) {
-		tmp = sdram[i];
-		if (tmp != i) {
-			printf("FAILED at address 0x%08lx\n",
-			       info->phys_addr + i * 4);
-			printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
-			return 0;
-		}
-	}
-
-	puts("OK\n");
+	hsdramc1_writel(TR, config->refresh_period);
+
+	if (config->data_bits == SDRAM_DATA_16BIT)
+		sdram_size = 1 << (config->row_bits + config->col_bits
+				   + config->bank_bits + 1);
+	else
+		sdram_size = 1 << (config->row_bits + config->col_bits
+				   + config->bank_bits + 2);
 
 	return sdram_size;
 }
diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c
index bef1f30..160838e 100644
--- a/cpu/at32ap/interrupts.c
+++ b/cpu/at32ap/interrupts.c
@@ -98,18 +98,16 @@ void set_timer(unsigned long t)
  */
 void udelay(unsigned long usec)
 {
-	unsigned long now, end;
+	unsigned long cycles;
+	unsigned long base;
+	unsigned long now;
 
-	now = sysreg_read(COUNT);
+	base = sysreg_read(COUNT);
+	cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
 
-	end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
-	end += now;
-
-	while (now > end)
-		now = sysreg_read(COUNT);
-
-	while (now < end)
+	do {
 		now = sysreg_read(COUNT);
+	} while ((now - base) < cycles);
 }
 
 static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
diff --git a/cpu/at32ap/pm.c b/cpu/at32ap/pm.c
deleted file mode 100644
index c78d547..0000000
--- a/cpu/at32ap/pm.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#ifdef CFG_POWER_MANAGER
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#include <asm/arch/memory-map.h>
-
-#include "sm.h"
-
-
-#ifdef CONFIG_PLL
-#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
-#else
-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-#endif /* CFG_POWER_MANAGER */
diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S
index ab8c2b7..907e9b1 100644
--- a/cpu/at32ap/start.S
+++ b/cpu/at32ap/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2006 Atmel Corporation
+ * Copyright (C) 2005-2008 Atmel Corporation
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,12 +20,9 @@
  * MA 02111-1307 USA
  */
 #include <config.h>
+#include <asm/ptrace.h>
 #include <asm/sysreg.h>
 
-#ifndef PART_SPECIFIC_BOOTSTRAP
-# define PART_SPECIFIC_BOOTSTRAP
-#endif
-
 #define SYSREG_MMUCR_I_OFFSET	2
 #define SYSREG_MMUCR_S_OFFSET	4
 
@@ -34,11 +31,115 @@
 		    | SYSREG_BIT(FE) | SYSREG_BIT(RE)		\
 		    | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
 
-	.text
+	/*
+	 * To save some space, we use the same entry point for
+	 * exceptions and reset. This avoids lots of alignment padding
+	 * since the reset vector is always suitably aligned.
+	 */
+	.section .exception.text, "ax", @progbits
 	.global	_start
+	.global	_evba
+	.type	_start, @function
+	.type	_evba, @function
 _start:
-	PART_SPECIFIC_BOOTSTRAP
+	.size	_start, 0
+_evba:
+	.org	0x00
+	rjmp	unknown_exception	/* Unrecoverable exception */
+	.org	0x04
+	rjmp	unknown_exception	/* TLB multiple hit */
+	.org	0x08
+	rjmp	unknown_exception	/* Bus error data fetch */
+	.org	0x0c
+	rjmp	unknown_exception	/* Bus error instruction fetch */
+	.org	0x10
+	rjmp	unknown_exception	/* NMI */
+	.org	0x14
+	rjmp	unknown_exception	/* Instruction address */
+	.org	0x18
+	rjmp	unknown_exception	/* ITLB protection */
+	.org	0x1c
+	rjmp	unknown_exception	/* Breakpoint */
+	.org	0x20
+	rjmp	unknown_exception	/* Illegal opcode */
+	.org	0x24
+	rjmp	unknown_exception	/* Unimplemented instruction */
+	.org	0x28
+	rjmp	unknown_exception	/* Privilege violation */
+	.org	0x2c
+	rjmp	unknown_exception	/* Floating-point */
+	.org	0x30
+	rjmp	unknown_exception	/* Coprocessor absent */
+	.org	0x34
+	rjmp	unknown_exception	/* Data Address (read) */
+	.org	0x38
+	rjmp	unknown_exception	/* Data Address (write) */
+	.org	0x3c
+	rjmp	unknown_exception	/* DTLB Protection (read) */
+	.org	0x40
+	rjmp	unknown_exception	/* DTLB Protection (write) */
+	.org	0x44
+	rjmp	unknown_exception	/* DTLB Modified */
+
+	.org	0x50
+	rjmp	unknown_exception	/* ITLB Miss */
+	.org	0x60
+	rjmp	unknown_exception	/* DTLB Miss (read) */
+	.org	0x70
+	rjmp	unknown_exception	/* DTLB Miss (write) */
+
+	.size	_evba, . - _evba
+
+	.align	2
+	.type	unknown_exception, @function
+unknown_exception:
+	/* Figure out whether we're handling an exception (Exception
+	 * mode) or just booting (Supervisor mode). */
+	csrfcz	SYSREG_M1_OFFSET
+	brcc	at32ap_cpu_bootstrap
+
+	/* This is an exception. Complain. */
+	pushm	r0-r12
+	sub	r8, sp, REG_R12 - REG_R0 - 4
+	mov	r9, lr
+	mfsr	r10, SYSREG_RAR_EX
+	mfsr	r11, SYSREG_RSR_EX
+	pushm	r8-r11
+	mfsr	r12, SYSREG_ECR
+	mov	r11, sp
+	rcall	do_unknown_exception
+1:	rjmp	1b
+
+	/* The COUNT/COMPARE timer interrupt handler */
+	.global	timer_interrupt_handler
+	.type	timer_interrupt_handler,@function
+	.align	2
+timer_interrupt_handler:
+	/*
+	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
+	 *
+	 * We're running at interrupt level 3, so we don't need to save
+	 * r8-r12 or lr to the stack.
+	 */
+	lda.w	r8, timer_overflow
+	ld.w	r9, r8[0]
+	mov	r10, -1
+	mtsr	SYSREG_COMPARE, r10
+	sub	r9, -1
+	st.w	r8[0], r9
+	rete
 
+	/*
+	 * CPU bootstrap after reset is handled here. SoC code may
+	 * override this in case they need to initialize oscillators,
+	 * etc.
+	 */
+	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
+	.global	at32ap_cpu_bootstrap
+	.weak	at32ap_cpu_bootstrap
+	.type	at32ap_cpu_bootstrap, @function
+	.align	2
+at32ap_cpu_bootstrap:
 	/* Reset the Status Register */
 	mov	r0, lo(SR_INIT)
 	orh	r0, hi(SR_INIT)
@@ -66,9 +167,16 @@ _start:
 	lddpc	pc, 1f
 
 	.align	2
-1:	.long	2f
+1:	.long	at32ap_low_level_init
+	.size	_start, . - _start
 
-2:	lddpc	sp, sp_init
+	/* Common CPU bootstrap code after oscillator/cache/etc. init */
+	.section .text.avr32ap_low_level_init, "ax", @progbits
+	.global	at32ap_low_level_init
+	.type	at32ap_low_level_init, @function
+	.align	2
+at32ap_low_level_init:
+	lddpc	sp, sp_init
 
 	/* Initialize the GOT pointer */
 	lddpc	r6, got_init
@@ -90,6 +198,7 @@ got_init:
 	 * Relocate the u-boot image into RAM and continue from there.
 	 * Does not return.
 	 */
+	.section .text.relocate_code,"ax",@progbits
 	.global	relocate_code
 	.type	relocate_code,@function
 relocate_code:
@@ -162,3 +271,5 @@ in_ram:
 	.align	2
 got_init_reloc:
 	.long	3b - _GLOBAL_OFFSET_TABLE_
+
+	.size	relocate_code, . - relocate_code
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 385319a..4a1dd33 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -58,7 +58,7 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
 	return get_pba_clk_rate();
 }
 #endif
-#ifdef AT32AP700x_CHIP_HAS_USART
+#ifdef AT32AP700x_CHIP_HAS_MACB
 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
 {
 	return get_pbb_clk_rate();
@@ -75,6 +75,8 @@ static inline unsigned long get_mci_clk_rate(void)
 }
 #endif
 
+extern void clk_init(void);
+
 /* Board code may need the SDRAM base clock as a compile-time constant */
 #define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
 
diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix.h b/include/asm-avr32/arch-at32ap700x/hmatrix.h
new file mode 100644
index 0000000..d6b6263
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/hmatrix.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_HMATRIX_H__
+#define __ASM_AVR32_ARCH_HMATRIX_H__
+
+#include <asm/hmatrix-common.h>
+
+/* Bitfields in SFR4 (EBI) */
+#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET		1
+#define HMATRIX_EBI_SDRAM_ENABLE_SIZE		1
+#define HMATRIX_EBI_NAND_ENABLE_OFFSET		3
+#define HMATRIX_EBI_NAND_ENABLE_SIZE		1
+#define HMATRIX_EBI_CF0_ENABLE_OFFSET		4
+#define HMATRIX_EBI_CF0_ENABLE_SIZE		1
+#define HMATRIX_EBI_CF1_ENABLE_OFFSET		5
+#define HMATRIX_EBI_CF1_ENABLE_SIZE		1
+#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET	8
+#define HMATRIX_EBI_PULLUP_DISABLE_SIZE		1
+
+/* HSB masters */
+#define HMATRIX_MASTER_CPU_DCACHE		0
+#define HMATRIX_MASTER_CPU_ICACHE		1
+#define HMATRIX_MASTER_PDC			2
+#define HMATRIX_MASTER_ISI			3
+#define HMATRIX_MASTER_USBA			4
+#define HMATRIX_MASTER_LCDC			5
+#define HMATRIX_MASTER_MACB0			6
+#define HMATRIX_MASTER_MACB1			7
+#define HMATRIX_MASTER_DMACA_M0			8
+#define HMATRIX_MASTER_DMACA_M1			9
+
+/* HSB slaves */
+#define HMATRIX_SLAVE_SRAM0			0
+#define HMATRIX_SLAVE_SRAM1			1
+#define HMATRIX_SLAVE_PBA			2
+#define HMATRIX_SLAVE_PBB			3
+#define HMATRIX_SLAVE_EBI			4
+#define HMATRIX_SLAVE_USBA			5
+#define HMATRIX_SLAVE_LCDC			6
+#define HMATRIX_SLAVE_DMACA			7
+
+#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h
deleted file mode 100644
index b0e787a..0000000
--- a/include/asm-avr32/arch-at32ap700x/hmatrix2.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Register definition for the High-speed Bus Matrix
- */
-#ifndef __ASM_AVR32_HMATRIX2_H__
-#define __ASM_AVR32_HMATRIX2_H__
-
-/* HMATRIX2 register offsets */
-#define HMATRIX2_MCFG0				0x0000
-#define HMATRIX2_MCFG1				0x0004
-#define HMATRIX2_MCFG2				0x0008
-#define HMATRIX2_MCFG3				0x000c
-#define HMATRIX2_MCFG4				0x0010
-#define HMATRIX2_MCFG5				0x0014
-#define HMATRIX2_MCFG6				0x0018
-#define HMATRIX2_MCFG7				0x001c
-#define HMATRIX2_MCFG8				0x0020
-#define HMATRIX2_MCFG9				0x0024
-#define HMATRIX2_MCFG10				0x0028
-#define HMATRIX2_MCFG11				0x002c
-#define HMATRIX2_MCFG12				0x0030
-#define HMATRIX2_MCFG13				0x0034
-#define HMATRIX2_MCFG14				0x0038
-#define HMATRIX2_MCFG15				0x003c
-#define HMATRIX2_SCFG0				0x0040
-#define HMATRIX2_SCFG1				0x0044
-#define HMATRIX2_SCFG2				0x0048
-#define HMATRIX2_SCFG3				0x004c
-#define HMATRIX2_SCFG4				0x0050
-#define HMATRIX2_SCFG5				0x0054
-#define HMATRIX2_SCFG6				0x0058
-#define HMATRIX2_SCFG7				0x005c
-#define HMATRIX2_SCFG8				0x0060
-#define HMATRIX2_SCFG9				0x0064
-#define HMATRIX2_SCFG10				0x0068
-#define HMATRIX2_SCFG11				0x006c
-#define HMATRIX2_SCFG12				0x0070
-#define HMATRIX2_SCFG13				0x0074
-#define HMATRIX2_SCFG14				0x0078
-#define HMATRIX2_SCFG15				0x007c
-#define HMATRIX2_PRAS0				0x0080
-#define HMATRIX2_PRBS0				0x0084
-#define HMATRIX2_PRAS1				0x0088
-#define HMATRIX2_PRBS1				0x008c
-#define HMATRIX2_PRAS2				0x0090
-#define HMATRIX2_PRBS2				0x0094
-#define HMATRIX2_PRAS3				0x0098
-#define HMATRIX2_PRBS3				0x009c
-#define HMATRIX2_PRAS4				0x00a0
-#define HMATRIX2_PRBS4				0x00a4
-#define HMATRIX2_PRAS5				0x00a8
-#define HMATRIX2_PRBS5				0x00ac
-#define HMATRIX2_PRAS6				0x00b0
-#define HMATRIX2_PRBS6				0x00b4
-#define HMATRIX2_PRAS7				0x00b8
-#define HMATRIX2_PRBS7				0x00bc
-#define HMATRIX2_PRAS8				0x00c0
-#define HMATRIX2_PRBS8				0x00c4
-#define HMATRIX2_PRAS9				0x00c8
-#define HMATRIX2_PRBS9				0x00cc
-#define HMATRIX2_PRAS10				0x00d0
-#define HMATRIX2_PRBS10				0x00d4
-#define HMATRIX2_PRAS11				0x00d8
-#define HMATRIX2_PRBS11				0x00dc
-#define HMATRIX2_PRAS12				0x00e0
-#define HMATRIX2_PRBS12				0x00e4
-#define HMATRIX2_PRAS13				0x00e8
-#define HMATRIX2_PRBS13				0x00ec
-#define HMATRIX2_PRAS14				0x00f0
-#define HMATRIX2_PRBS14				0x00f4
-#define HMATRIX2_PRAS15				0x00f8
-#define HMATRIX2_PRBS15				0x00fc
-#define HMATRIX2_MRCR				0x0100
-#define HMATRIX2_SFR0				0x0110
-#define HMATRIX2_SFR1				0x0114
-#define HMATRIX2_SFR2				0x0118
-#define HMATRIX2_SFR3				0x011c
-#define HMATRIX2_SFR4				0x0120
-#define HMATRIX2_SFR5				0x0124
-#define HMATRIX2_SFR6				0x0128
-#define HMATRIX2_SFR7				0x012c
-#define HMATRIX2_SFR8				0x0130
-#define HMATRIX2_SFR9				0x0134
-#define HMATRIX2_SFR10				0x0138
-#define HMATRIX2_SFR11				0x013c
-#define HMATRIX2_SFR12				0x0140
-#define HMATRIX2_SFR13				0x0144
-#define HMATRIX2_SFR14				0x0148
-#define HMATRIX2_SFR15				0x014c
-#define HMATRIX2_VERSION			0x01fc
-
-/* Bitfields in MCFG0 */
-#define HMATRIX2_ULBT_OFFSET			0
-#define HMATRIX2_ULBT_SIZE			3
-
-/* Bitfields in SCFG0 */
-#define HMATRIX2_SLOT_CYCLE_OFFSET		0
-#define HMATRIX2_SLOT_CYCLE_SIZE		8
-#define HMATRIX2_DEFMSTR_TYPE_OFFSET		16
-#define HMATRIX2_DEFMSTR_TYPE_SIZE		2
-#define HMATRIX2_FIXED_DEFMSTR_OFFSET		18
-#define HMATRIX2_FIXED_DEFMSTR_SIZE		4
-#define HMATRIX2_ARBT_OFFSET			24
-#define HMATRIX2_ARBT_SIZE			2
-
-/* Bitfields in PRAS0 */
-#define HMATRIX2_M0PR_OFFSET			0
-#define HMATRIX2_M0PR_SIZE			4
-#define HMATRIX2_M1PR_OFFSET			4
-#define HMATRIX2_M1PR_SIZE			4
-#define HMATRIX2_M2PR_OFFSET			8
-#define HMATRIX2_M2PR_SIZE			4
-#define HMATRIX2_M3PR_OFFSET			12
-#define HMATRIX2_M3PR_SIZE			4
-#define HMATRIX2_M4PR_OFFSET			16
-#define HMATRIX2_M4PR_SIZE			4
-#define HMATRIX2_M5PR_OFFSET			20
-#define HMATRIX2_M5PR_SIZE			4
-#define HMATRIX2_M6PR_OFFSET			24
-#define HMATRIX2_M6PR_SIZE			4
-#define HMATRIX2_M7PR_OFFSET			28
-#define HMATRIX2_M7PR_SIZE			4
-
-/* Bitfields in PRBS0 */
-#define HMATRIX2_M8PR_OFFSET			0
-#define HMATRIX2_M8PR_SIZE			4
-#define HMATRIX2_M9PR_OFFSET			4
-#define HMATRIX2_M9PR_SIZE			4
-#define HMATRIX2_M10PR_OFFSET			8
-#define HMATRIX2_M10PR_SIZE			4
-#define HMATRIX2_M11PR_OFFSET			12
-#define HMATRIX2_M11PR_SIZE			4
-#define HMATRIX2_M12PR_OFFSET			16
-#define HMATRIX2_M12PR_SIZE			4
-#define HMATRIX2_M13PR_OFFSET			20
-#define HMATRIX2_M13PR_SIZE			4
-#define HMATRIX2_M14PR_OFFSET			24
-#define HMATRIX2_M14PR_SIZE			4
-#define HMATRIX2_M15PR_OFFSET			28
-#define HMATRIX2_M15PR_SIZE			4
-
-/* Bitfields in MRCR */
-#define HMATRIX2_RBC0_OFFSET			0
-#define HMATRIX2_RBC0_SIZE			1
-#define HMATRIX2_RBC1_OFFSET			1
-#define HMATRIX2_RBC1_SIZE			1
-#define HMATRIX2_RBC2_OFFSET			2
-#define HMATRIX2_RBC2_SIZE			1
-#define HMATRIX2_RBC3_OFFSET			3
-#define HMATRIX2_RBC3_SIZE			1
-#define HMATRIX2_RBC4_OFFSET			4
-#define HMATRIX2_RBC4_SIZE			1
-#define HMATRIX2_RBC5_OFFSET			5
-#define HMATRIX2_RBC5_SIZE			1
-#define HMATRIX2_RBC6_OFFSET			6
-#define HMATRIX2_RBC6_SIZE			1
-#define HMATRIX2_RBC7_OFFSET			7
-#define HMATRIX2_RBC7_SIZE			1
-#define HMATRIX2_RBC8_OFFSET			8
-#define HMATRIX2_RBC8_SIZE			1
-#define HMATRIX2_RBC9_OFFSET			9
-#define HMATRIX2_RBC9_SIZE			1
-#define HMATRIX2_RBC10_OFFSET			10
-#define HMATRIX2_RBC10_SIZE			1
-#define HMATRIX2_RBC11_OFFSET			11
-#define HMATRIX2_RBC11_SIZE			1
-#define HMATRIX2_RBC12_OFFSET			12
-#define HMATRIX2_RBC12_SIZE			1
-#define HMATRIX2_RBC13_OFFSET			13
-#define HMATRIX2_RBC13_SIZE			1
-#define HMATRIX2_RBC14_OFFSET			14
-#define HMATRIX2_RBC14_SIZE			1
-#define HMATRIX2_RBC15_OFFSET			15
-#define HMATRIX2_RBC15_SIZE			1
-
-/* Bitfields in SFR0 */
-#define HMATRIX2_SFR_OFFSET			0
-#define HMATRIX2_SFR_SIZE			32
-
-/* Bitfields in SFR4 */
-#define HMATRIX2_CS1A_OFFSET			1
-#define HMATRIX2_CS1A_SIZE			1
-#define HMATRIX2_CS3A_OFFSET			3
-#define HMATRIX2_CS3A_SIZE			1
-#define HMATRIX2_CS4A_OFFSET			4
-#define HMATRIX2_CS4A_SIZE			1
-#define HMATRIX2_CS5A_OFFSET			5
-#define HMATRIX2_CS5A_SIZE			1
-#define HMATRIX2_DBPUC_OFFSET			8
-#define HMATRIX2_DBPUC_SIZE			1
-
-/* Bitfields in VERSION */
-#define HMATRIX2_VERSION_OFFSET			0
-#define HMATRIX2_VERSION_SIZE			12
-#define HMATRIX2_MFN_OFFSET			16
-#define HMATRIX2_MFN_SIZE			3
-
-/* Constants for ULBT */
-#define HMATRIX2_ULBT_INFINITE			0
-#define HMATRIX2_ULBT_SINGLE			1
-#define HMATRIX2_ULBT_FOUR_BEAT			2
-#define HMATRIX2_ULBT_SIXTEEN_BEAT		4
-
-/* Constants for DEFMSTR_TYPE */
-#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT	0
-#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT	1
-#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT	2
-
-/* Constants for ARBT */
-#define HMATRIX2_ARBT_ROUND_ROBIN		0
-#define HMATRIX2_ARBT_FIXED_PRIORITY		1
-
-/* Bit manipulation macros */
-#define HMATRIX2_BIT(name)					\
-	(1 << HMATRIX2_##name##_OFFSET)
-#define HMATRIX2_BF(name,value)					\
-	(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1))	\
-	 << HMATRIX2_##name##_OFFSET)
-#define HMATRIX2_BFEXT(name,value)				\
-	(((value) >> HMATRIX2_##name##_OFFSET)			\
-	 & ((1 << HMATRIX2_##name##_SIZE) - 1))
-#define HMATRIX2_BFINS(name,value,old)				\
-	(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1)		\
-		    << HMATRIX2_##name##_OFFSET))		\
-	 | HMATRIX2_BF(name,value))
-
-/* Register access macros */
-#define hmatrix2_readl(reg)					\
-	readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
-#define hmatrix2_writel(reg,value)				\
-	writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
-
-#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h
index 5513e88..6592c03 100644
--- a/include/asm-avr32/arch-at32ap700x/memory-map.h
+++ b/include/asm-avr32/arch-at32ap700x/memory-map.h
@@ -22,6 +22,26 @@
 #ifndef __AT32AP7000_MEMORY_MAP_H__
 #define __AT32AP7000_MEMORY_MAP_H__
 
+/* Internal and external memories */
+#define EBI_SRAM_CS0_BASE			0x00000000
+#define EBI_SRAM_CS0_SIZE			0x04000000
+#define EBI_SRAM_CS4_BASE			0x04000000
+#define EBI_SRAM_CS4_SIZE			0x04000000
+#define EBI_SRAM_CS2_BASE			0x08000000
+#define EBI_SRAM_CS2_SIZE			0x04000000
+#define EBI_SRAM_CS3_BASE			0x0c000000
+#define EBI_SRAM_CS3_SIZE			0x04000000
+#define EBI_SRAM_CS1_BASE			0x10000000
+#define EBI_SRAM_CS1_SIZE			0x10000000
+#define EBI_SRAM_CS5_BASE			0x20000000
+#define EBI_SRAM_CS5_SIZE			0x04000000
+
+#define EBI_SDRAM_BASE				EBI_SRAM_CS1_BASE
+#define EBI_SDRAM_SIZE				EBI_SRAM_CS1_SIZE
+
+#define INTERNAL_SRAM_BASE			0x24000000
+#define INTERNAL_SRAM_SIZE			0x00008000
+
 /* Devices on the High Speed Bus (HSB) */
 #define LCDC_BASE				0xFF000000
 #define DMAC_BASE				0xFF200000
diff --git a/include/asm-avr32/hmatrix-common.h b/include/asm-avr32/hmatrix-common.h
new file mode 100644
index 0000000..4b7e610
--- /dev/null
+++ b/include/asm-avr32/hmatrix-common.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_HMATRIX_COMMON_H__
+#define __ASM_AVR32_HMATRIX_COMMON_H__
+
+/* HMATRIX register offsets */
+struct hmatrix_regs {
+	u32	MCFG[16];
+	u32	SCFG[16];
+	struct {
+		u32	A;
+		u32	B;
+	} PRS[16];
+	u32	MRCR;
+	u32	__reserved[3];
+	u32	SFR[16];
+};
+
+/* Bitfields in MCFG */
+#define HMATRIX_ULBT_OFFSET			0
+#define HMATRIX_ULBT_SIZE			3
+
+/* Bitfields in SCFG */
+#define HMATRIX_SLOT_CYCLE_OFFSET		0
+#define HMATRIX_SLOT_CYCLE_SIZE			8
+#define HMATRIX_DEFMSTR_TYPE_OFFSET		16
+#define HMATRIX_DEFMSTR_TYPE_SIZE		2
+#define HMATRIX_FIXED_DEFMSTR_OFFSET		18
+#define HMATRIX_FIXED_DEFMSTR_SIZE		4
+#define HMATRIX_ARBT_OFFSET			24
+#define HMATRIX_ARBT_SIZE			1
+
+/* Bitfields in PRS.A */
+#define HMATRIX_M0PR_OFFSET			0
+#define HMATRIX_M0PR_SIZE			4
+#define HMATRIX_M1PR_OFFSET			4
+#define HMATRIX_M1PR_SIZE			4
+#define HMATRIX_M2PR_OFFSET			8
+#define HMATRIX_M2PR_SIZE			4
+#define HMATRIX_M3PR_OFFSET			12
+#define HMATRIX_M3PR_SIZE			4
+#define HMATRIX_M4PR_OFFSET			16
+#define HMATRIX_M4PR_SIZE			4
+#define HMATRIX_M5PR_OFFSET			20
+#define HMATRIX_M5PR_SIZE			4
+#define HMATRIX_M6PR_OFFSET			24
+#define HMATRIX_M6PR_SIZE			4
+#define HMATRIX_M7PR_OFFSET			28
+#define HMATRIX_M7PR_SIZE			4
+
+/* Bitfields in PRS.B */
+#define HMATRIX_M8PR_OFFSET			0
+#define HMATRIX_M8PR_SIZE			4
+#define HMATRIX_M9PR_OFFSET			4
+#define HMATRIX_M9PR_SIZE			4
+#define HMATRIX_M10PR_OFFSET			8
+#define HMATRIX_M10PR_SIZE			4
+#define HMATRIX_M11PR_OFFSET			12
+#define HMATRIX_M11PR_SIZE			4
+#define HMATRIX_M12PR_OFFSET			16
+#define HMATRIX_M12PR_SIZE			4
+#define HMATRIX_M13PR_OFFSET			20
+#define HMATRIX_M13PR_SIZE			4
+#define HMATRIX_M14PR_OFFSET			24
+#define HMATRIX_M14PR_SIZE			4
+#define HMATRIX_M15PR_OFFSET			28
+#define HMATRIX_M15PR_SIZE			4
+
+/* Constants for ULBT */
+#define HMATRIX_ULBT_INFINITE			0
+#define HMATRIX_ULBT_SINGLE			1
+#define HMATRIX_ULBT_FOUR_BEAT			2
+#define HMATRIX_ULBT_EIGHT_BEAT			3
+#define HMATRIX_ULBT_SIXTEEN_BEAT		4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT		0
+#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT	1
+#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT	2
+
+/* Constants for ARBT */
+#define HMATRIX_ARBT_ROUND_ROBIN		0
+#define HMATRIX_ARBT_FIXED_PRIORITY		1
+
+/* Bit manipulation macros */
+#define HMATRIX_BIT(name)					\
+	(1 << HMATRIX_##name##_OFFSET)
+#define HMATRIX_BF(name,value)					\
+	(((value) & ((1 << HMATRIX_##name##_SIZE) - 1))		\
+	 << HMATRIX_##name##_OFFSET)
+#define HMATRIX_BFEXT(name,value)				\
+	(((value) >> HMATRIX_##name##_OFFSET)			\
+	 & ((1 << HMATRIX_##name##_SIZE) - 1))
+#define HMATRIX_BFINS(name,value,old)				\
+	(((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1)		\
+		    << HMATRIX_##name##_OFFSET))		\
+	 | HMATRIX_BF(name,value))
+
+/* Register access macros */
+#define __hmatrix_reg(reg)					\
+	(((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg)
+#define hmatrix_read(reg)					\
+	(__hmatrix_reg(reg))
+#define hmatrix_write(reg, value)				\
+	do { __hmatrix_reg(reg) = (value); } while (0)
+
+#define hmatrix_slave_read(slave, reg)				\
+	hmatrix_read(reg[HMATRIX_SLAVE_##slave])
+#define hmatrix_slave_write(slave, reg, value)			\
+	hmatrix_write(reg[HMATRIX_SLAVE_##slave], value)
+
+#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
index 833af6e..7bdefc1 100644
--- a/include/asm-avr32/sdram.h
+++ b/include/asm-avr32/sdram.h
@@ -22,15 +22,32 @@
 #ifndef __ASM_AVR32_SDRAM_H
 #define __ASM_AVR32_SDRAM_H
 
-struct sdram_info {
-	unsigned long phys_addr;
-	unsigned int row_bits, col_bits, bank_bits;
-	unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+struct sdram_config {
+	/* Number of data bits. */
+	enum {
+		SDRAM_DATA_16BIT,
+		SDRAM_DATA_32BIT,
+	} data_bits;
+
+	/* Number of address bits */
+	uint8_t row_bits, col_bits, bank_bits;
+
+	/* SDRAM timings in cycles */
+	uint8_t cas, twr, trc, trp, trcd, tras, txsr;
 
 	/* SDRAM refresh period in cycles */
 	unsigned long refresh_period;
 };
 
-extern unsigned long sdram_init(const struct sdram_info *info);
+/*
+ * Attempt to initialize the SDRAM controller using the specified
+ * parameters. Return the expected size of the memory area based on
+ * the number of address and data bits.
+ *
+ * The caller should verify that the configuration is correct by
+ * running a memory test, e.g. get_ram_size().
+ */
+extern unsigned long sdram_init(void *sdram_base,
+			const struct sdram_config *config);
 
 #endif /* __ASM_AVR32_SDRAM_H */
diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h
index 75373ab..fe819b2 100644
--- a/include/asm-avr32/sections.h
+++ b/include/asm-avr32/sections.h
@@ -25,15 +25,8 @@
 /* References to section boundaries */
 
 extern char _text[], _etext[];
-extern char __flashprog_start[], __flashprog_end[];
 extern char _data[], __data_lma[], _edata[], __edata_lma[];
 extern char __got_start[], __got_lma[], __got_end[];
 extern char _end[];
 
-/*
- * Everything in .flashprog will be locked in the icache so it doesn't
- * get disturbed when executing flash commands.
- */
-#define __flashprog __attribute__((section(".flashprog"), __noinline__))
-
 #endif /* __ASM_AVR32_SECTIONS_H */
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 5aad043..3fc9975 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -112,8 +114,11 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
@@ -137,11 +142,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
-#define CFG_SDRAM_16BIT			1
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -150,27 +153,20 @@
 #define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
 
 #define CFG_MALLOC_LEN			(256*1024)
-#define CFG_MALLOC_END							\
-	({								\
-		DECLARE_GLOBAL_DATA_PTR;				\
-		CFG_SDRAM_BASE + gd->sdram_size;			\
-	})
-#define CFG_MALLOC_START		(CFG_MALLOC_END - CFG_MALLOC_LEN)
-
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
 #define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
 
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 95aeab6..ba18eb6 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -139,9 +141,9 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_REGINFO
 
 #undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
 #undef CONFIG_CMD_XIMG
 
@@ -170,10 +172,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -185,17 +186,17 @@
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
-#define CFG_MAXARGS			8
+#define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 194788b..a528ddf 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7001		1
@@ -153,10 +155,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -167,17 +168,17 @@
 #define CFG_MALLOC_LEN			(256*1024)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
 #define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index b81fc21..fc9585e 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7002		1
@@ -153,11 +155,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
-#define CFG_SDRAM_16BIT			1
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -168,17 +168,17 @@
 #define CFG_MALLOC_LEN			(256*1024)
 
 /* Allow 2MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00200000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
 #define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
new file mode 100644
index 0000000..9fd49a5
--- /dev/null
+++ b/include/configs/atstk1006.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/memory-map.h>
+
+#define CONFIG_AVR32			1
+#define CONFIG_AT32AP			1
+#define CONFIG_AT32AP7000		1
+#define CONFIG_ATSTK1006		1
+#define CONFIG_ATSTK1000		1
+
+#define CONFIG_ATSTK1000_EXT_FLASH	1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ				1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL			1
+#define CFG_POWER_MANAGER		1
+#define CFG_OSC0_HZ			20000000
+#define CFG_PLL0_DIV			1
+#define CFG_PLL0_MUL			7
+#define CFG_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
+#define CFG_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
+#define CFG_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
+#define CFG_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
+#define CFG_CLKDIV_PBB			1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT			0x04
+
+#undef CONFIG_USART0
+#define CONFIG_USART1			1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=mtd3 fbmem=2400k"
+
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT			1
+#define CONFIG_AUTOBOOT_KEYED		1
+#define CONFIG_AUTOBOOT_PROMPT				\
+	"Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+#define CONFIG_NET_MULTI		1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART		1
+#define CONFIG_MACB			1
+#define CONFIG_PIO2			1
+#define CFG_NR_PIOS			5
+#define CFG_HSDRAMC			1
+#define CONFIG_MMC			1
+
+#define CFG_DCACHE_LINESZ		32
+#define CFG_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI			1
+#define CFG_FLASH_CFI_DRIVER		1
+#endif
+
+#define CFG_FLASH_BASE			0x00000000
+#define CFG_FLASH_SIZE			0x800000
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		135
+
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_SIZE			65536
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN			(256*1024)
+#define CFG_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT			"U-Boot> "
+#define CFG_CBSIZE			256
+#define CFG_MAXARGS			16
+#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP			1
+
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
+#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x3f00000)
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/lib_avr32/memset.S b/lib_avr32/memset.S
index dc3b09b..79e3c67 100644
--- a/lib_avr32/memset.S
+++ b/lib_avr32/memset.S
@@ -27,7 +27,7 @@
 	 *
 	 * Returns b in r12
 	 */
-	.text
+	.section .text.memset, "ax", @progbits
 
 	.global	memset
 	.type	memset, @function