Add esd cpci5200 and pf5200 boards

Patch by Reinhard Arlt, 22 Aug 2005

18 files changed, 3231 insertions, 3 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 0bc65b3..a95d70e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Add esd cpci5200 and pf5200 boards
+  Patch by Reinhard Arlt, 22 Aug 2005
+
 * Fix sysclock for TQM8540 and TQM8560 boards
   Patch by Martin Krause, 25 Jul 2005
 
diff --git a/MAINTAINERS b/MAINTAINERS
index 67f8bb4..b0d4aa4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -27,6 +27,9 @@ Pantelis Antoniou <panto@intracom.gr>
 
 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 
+	cpci5200		MPC5200
+	pf5200			MPC5200
+
 	CPCI750			PPC750FX/GX
 
 Yuli Barcohen <yuli@arabellasw.com>
diff --git a/MAKEALL b/MAKEALL
index 6829aa9..dcf86b0 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -25,9 +25,9 @@ LIST_5xx="	\
 #########################################################################
 
 LIST_5xxx="	\
-	icecube_5100	icecube_5200	EVAL5200	PM520		\
-	Total5100	Total5200	Total5200_Rev2	TQM5200_auto	\
-	o2dnt \
+	cpci5200	icecube_5100	icecube_5200	EVAL5200	\
+	pf5200		PM520		Total5100	Total5200	\
+	Total5200_Rev2	TQM5200_auto	o2dnt				\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index a204ce7..7106150 100644
--- a/Makefile
+++ b/Makefile
@@ -234,6 +234,9 @@ PATI_config:		unconfig
 aev_config: unconfig
 	@./mkconfig -a aev ppc mpc5xxx tqm5200
 
+cpci5200_config:  unconfig
+	@./mkconfig -a cpci5200  ppc mpc5xxx cpci5200 esd
+
 hmi1001_config:         unconfig
 	@./mkconfig hmi1001 ppc mpc5xxx hmi1001
 
@@ -280,6 +283,9 @@ inka4x0_config:		unconfig
 o2dnt_config:
 	@./mkconfig -a o2dnt ppc mpc5xxx o2dnt
 
+pf5200_config:  unconfig
+	@./mkconfig -a pf5200  ppc mpc5xxx pf5200 esd
+
 PM520_config \
 PM520_DDR_config \
 PM520_ROMBOOT_config \
diff --git a/board/esd/cpci5200/config.mk b/board/esd/cpci5200/config.mk
new file mode 100644
index 0000000..07b5de1
--- /dev/null
+++ b/board/esd/cpci5200/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
new file mode 100644
index 0000000..01c4171
--- /dev/null
+++ b/board/esd/cpci5200/cpci5200.c
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpci5200.c - main board support/init for the esd cpci5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_ata_reset(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_ata_reset();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPCI5200 (cpci5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void
+    ) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+	}
+}
+#endif				/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_ata_reset(void)
+{
+	debug("init_ata_reset\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	   "writepci- Write some data to pcibus\n",
+	   "<addr> <size>\n" "        - Write some data to pcibus.\n");
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
new file mode 100644
index 0000000..22d0a55
--- /dev/null
+++ b/board/esd/cpci5200/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
new file mode 100644
index 0000000..d76af02
--- /dev/null
+++ b/board/esd/cpci5200/strataflash.c
@@ -0,0 +1,804 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char *cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset,
+			 uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+			       cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 8) |
+		addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 24) |
+		(addr[(info->portwidth) - 1] << 16) |
+		(addr[(4 * info->portwidth) - 1] << 8) |
+		addr[(3 * info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size;
+	int i;
+	unsigned long address;
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf
+			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			     i, flash_info[0].size, flash_info[i].size << 20);
+		}
+	}
+
+#if 0				/* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for (i = 0;
+	     flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1;
+	     i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth << 3), (info->chipwidth << 3));
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	printf
+	    (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	     info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
+	     info->buffer_size);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n");
+		printf(" %08lX%5s",
+		       info->start[i], info->protect[i] ? " (RO)" : " ");
+	}
+	printf("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while (cnt >= info->portwidth) {
+		i = info->buffer_size > cnt ? cnt : info->buffer_size;
+		if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	/* handle the aligned part */
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif				/* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check(info, sector, info->erase_blk_tout,
+				     prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			int i;
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
+			      char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer(0);
+	while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt,
+			       info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if ((retcode == ERR_OK)
+	    && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,
+		       info->start[sector]);
+		if (flash_isset
+		    (info, sector, 0,
+		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+			printf("Command Sequence Error.\n");
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
+{
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *) cmdbuf;
+	for (i = 0; i < info->portwidth; i++)
+		*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+					FLASH_CMD_CFI);
+			if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
+					     'R')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
+					     'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio = 0;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+#if 0
+	invalidate_dcache_range(base, base + 0x400);
+#endif
+	if (flash_detect_cfi(info)) {
+
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions =
+		    flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp =
+			    flash_read_long(info, 0,
+					    FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size =
+			    (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) + 1;
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] =
+				    flash_isset(info, sect_cnt,
+						FLASH_OFFSET_PROTECT,
+						FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+		    (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+		    size_ratio;
+		info->buffer_size =
+		    (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
+		    1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+#ifdef DEBUG_FLASH
+	printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
+#endif
+#ifdef DEBUG_FLASH
+	printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+	printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t * info, ulong addr)
+{
+	int sector;
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					  "write to buffer")) == ERR_OK) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0,
+				FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+		    flash_full_status_check(info, sector,
+					    info->buffer_write_tout,
+					    "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif				/* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpci5200/u-boot.lds b/board/esd/cpci5200/u-boot.lds
new file mode 100644
index 0000000..d999dd1
--- /dev/null
+++ b/board/esd/cpci5200/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
new file mode 100644
index 0000000..603bbe2
--- /dev/null
+++ b/board/esd/pf5200/Makefile
@@ -0,0 +1,53 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+# 	  ../common/xilinx_jtag/micro.o \
+# 	  ../common/xilinx_jtag/ports.o
+
+# OBJS	= $(BOARD).o flash.o $(CPLD)
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/esd/pf5200/config.mk b/board/esd/pf5200/config.mk
new file mode 100644
index 0000000..07b5de1
--- /dev/null
+++ b/board/esd/pf5200/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
new file mode 100644
index 0000000..bfbd090
--- /dev/null
+++ b/board/esd/pf5200/flash.c
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK           0x00FF
+
+#define FPW                     FLASH_PORT_WIDTH
+#define FPWV                    FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1            0x0555
+#define FLASH_CYCLE2            0x0aaa
+#define FLASH_ID1               0x00
+#define FLASH_ID2               0x01
+#define FLASH_ID3               0x0E
+#define FLASH_ID4               0x0F
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_reset(flash_info_t * info);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(uint, ulong, ulong);
+
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	/* There is only ONE FLASH device */
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
+	size += flash_info[i].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef  CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t * info) {
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base) {
+	int i;
+	flash_info_t *info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		info = &flash_info[i];
+		if ((info->size) && (info->start[0] <= base)
+		    && (base <= info->start[0] + info->size - 1)) {
+			break;
+		}
+	}
+	return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info(flash_info_t * info) {
+	int i;
+	uchar *fmt;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt);
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+	       info->sector_count);
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		ulong size;
+		int erased;
+		ulong *flash = (unsigned long *)info->start[i];
+
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+		    (i !=
+		     (info->sector_count - 1)) ? (info->start[i + 1] -
+						  info->start[i]) >> 2 : (info->
+									  start
+									  [0] +
+									  info->
+									  size -
+									  info->
+									  start
+									  [i])
+		    >> 2;
+
+		for (flash = (unsigned long *)info->start[i], erased = 1;
+		     (flash != (unsigned long *)info->start[i] + size)
+		     && erased; flash++) {
+			erased = *flash == ~0x0UL;
+		}
+		printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
+		       info->protect[i] ? "(RO)" : "    ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info) {
+	int i;
+
+	/* Write auto select command: read Manufacturer ID                     */
+	/* Write auto select command sequence and test FLASH answer            */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD        */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.         */
+	/* This works for any bus width and any FLASH device width.            */
+	udelay(100);
+	switch (addr[FLASH_ID1] & 0x00ff) {
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus.     */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch ((FPW) addr[FLASH_ID2]) {
+		case (FPW) AMD_ID_MIRROR:
+			/* MIRROR BIT FLASH, read more ID bytes */
+			if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
+			    && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
+				/* attention: only the first 16 MB will be used in u-boot */
+				info->flash_id += FLASH_AMLV256U;
+				info->sector_count = 512;
+				info->size = 0x02000000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] =
+					    (ulong) addr + 0x10000 * i;
+				}
+				break;
+			}
+			/* fall thru to here ! */
+		default:
+			printf("unknown AMD device=%x %x %x",
+			       (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
+			       (FPW) addr[FLASH_ID4]);
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0x800000;
+			break;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+	}
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last) {
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	last = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+		if (info->protect[sect] != 0) {	/* protected, skip it */
+			continue;
+		}
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel. */
+		/* Let's wait 1 ms.                            */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {
+				/* every second */
+				putc('.');
+				last = get_timer(0);
+			}
+		}
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {
+			/* every second */
+			putc('.');
+			last = get_timer(0);
+		}
+		flash_reset(info);	/* reset to read mode */
+	}
+	printf(" done\n");
+	return (rcode);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+	return (res);
+}
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
new file mode 100644
index 0000000..22d0a55
--- /dev/null
+++ b/board/esd/pf5200/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
new file mode 100644
index 0000000..fa71c79
--- /dev/null
+++ b/board/esd/pf5200/pf5200.c
@@ -0,0 +1,370 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd ParaFinder (pf5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void
+    ) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+	}
+}
+#endif				/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+	*(vu_char *) CFG_CS1_START = 0x02;	/* Red Power LED on */
+	__asm__ volatile ("sync");
+
+	*(vu_char *) (CFG_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
+	__asm__ volatile ("sync");
+}
+
+void power_set_reset(int power)
+{
+	debug("ide_set_reset(%d)\n", power);
+
+	if (power) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6;
+		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
+		    0) {
+			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
+			    GPIO_USB0;
+		}
+
+	}
+}
+
+int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	power_set_reset(1);
+	return (0);
+}
+
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL);
+
+int phypower(int flag)
+{
+	u32 addr;
+	vu_long *reg;
+	int status;
+	pci_dev_t dev;
+
+	dev = PCI_BDF(0, 0x18, 0);
+	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
+	if (status == 0) {
+		reg = (vu_long *) (addr + 0x00000040);
+		*reg |= 0x40000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x001000c);
+		*reg |= 0x20000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x0010004);
+		if (flag != 0) {
+			*reg &= ~0x20000000;
+		} else {
+			*reg |= 0x20000000;
+		}
+		__asm__ volatile ("sync");
+	}
+	return (status);
+}
+
+int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int status;
+
+	if (argv[1][0] == '0') {
+		status = phypower(0);
+	} else {
+		status = phypower(1);
+	}
+	return (0);
+}
+
+U_BOOT_CMD(phypower, 2, 2, do_phypower,
+	   "phypower- Switch power of ethernet phy\n", NULL);
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	   "writepci- Write some data to pcibus\n",
+	   "<addr> <size>\n" "        - Write some data to pcibus.\n");
diff --git a/board/esd/pf5200/u-boot.lds b/board/esd/pf5200/u-boot.lds
new file mode 100644
index 0000000..d999dd1
--- /dev/null
+++ b/board/esd/pf5200/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 490fcd2..2cfa11c 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -49,7 +49,21 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
 	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
 	eieio();
 	udelay(10);
+#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
+	if (dev & 0x00ff0000) {
+		u32 val;
+		val  = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
+		udelay(10);
+		val = val << 16;
+		val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
+		*value = val;
+	} else {
+		*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+	}
+	udelay(10);
+#else
 	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+#endif
 	eieio();
 	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
 	udelay(10);
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
new file mode 100644
index 0000000..3898f91
--- /dev/null
+++ b/include/configs/cpci5200.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board	  */
+#define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */
+
+#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#if 1
+#define CONFIG_PCI		1
+#if 1
+#define CONFIG_PCI_PNP		1
+#endif
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+#if 0				/* test-only !!! */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+#endif
+
+#define ADD_PCI_CMD		CFG_CMD_PCI
+
+#else				/* MPC5100 */
+
+#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_EXT2	| \
+				 CFG_CMD_DATE	| \
+				 ADD_PCI_CMD	  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to esd CPU CPCI/5200;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=phypower 1;sleep 2;tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=cpci5200.esd\0" \
+	"script=cpci5200.bat\0" \
+	"image=/tftpboot/vxWorks_cpci5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+
+#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
+#define CFG_NVRAM_BASE_ADDR	0xfd010000
+#define CFG_NVRAM_SIZE		32*1024
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		86000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant	     */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_FLASH_INCREMENT	0x01000000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	128
+
+#define CFG_FLASH_PROTECTION	1	/* use hardware protection	     */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#if 1				/* test-only */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM	1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004DD00
+
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS1_START		0xfd000000
+#define CFG_CS1_SIZE		0x00010000
+#define CFG_CS1_CFG		0x10101410
+
+#define CFG_CS3_START		0xfd010000
+#define CFG_CS3_SIZE		0x00010000
+#define CFG_CS3_CFG		0x10109410
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
+
+#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+
+/* CPLD program pin configuration */
+#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+
+#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+
+#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET	0x00000000
+#define JTAG_GPIO_CFG_RESET	0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDI_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDO_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET	0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
new file mode 100644
index 0000000..a8edff2
--- /dev/null
+++ b/include/configs/pf5200.h
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+#define CONFIG_PF5200		1	/* ... on PF5200  board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/
+
+#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#if 0				/* test-only */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#else
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#endif
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#if 0				/* test-only !!! */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+#endif
+
+#define ADD_PCI_CMD		CFG_CMD_PCI
+
+#else				/* MPC5100 */
+
+#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_ELF	| \
+				 ADD_PCI_CMD	  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to ParaFinder pf5200;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=phypower 1;sleep 2;tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=pf5200.esd\0" \
+	"script=pf5200.bat\0" \
+	"image=/tftpboot/vxWorks_pf5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		86000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	512
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#if 1				/* test-only */
+#define CFG_ENV_IS_IN_FLASH	0
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM	1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004DD00
+
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS1_START		0xfd000000
+#define CFG_CS1_SIZE		0x00010000
+#define CFG_CS1_CFG		0x10101410
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
+
+#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+
+/* CPLD program pin configuration */
+#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+
+#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+
+#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET	0x00000000
+#define JTAG_GPIO_CFG_RESET	0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDI_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDO_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET	0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
+
+#endif				/* __CONFIG_H */