at91: use C structs for AT91 OHCI code

This patch is part of migrating the AT91 support towards
using C struct for all SOC access.

It removes one more CONFIG_AT91_LEGACY warning.

at91_pmc.h needs cleanup after migration of the drivers
has been done.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

2 files changed, 31 insertions, 20 deletions

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 29f3ba1..b2e03bc 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -25,11 +25,6 @@
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 
-#ifndef CONFIG_AT91_LEGACY
-#define CONFIG_AT91_LEGACY
-#warning Please update to use C structur SoC access !
-#endif
-
 #include <asm/arch/hardware.h>
 #include <asm/arch/io.h>
 #include <asm/arch/at91_pmc.h>
@@ -37,22 +32,23 @@
 
 int usb_cpu_init(void)
 {
+	at91_pmc_t *pmc	= (at91_pmc_t *)AT91_PMC_BASE;
 
 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
     defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
     defined(CONFIG_AT91SAM9261)
 	/* Enable PLLB */
-	at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init());
-	while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
+	writel(get_pllb_init(), &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
 		;
 #endif
 
 	/* Enable USB host clock. */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
+	writel(1 << AT91_ID_UHP, &pmc->pcer);
 #ifdef CONFIG_AT91SAM9261
-	at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0);
+	writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scer);
 #else
-	at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
+	writel(AT91_PMC_UHP, &pmc->scer);
 #endif
 
 	return 0;
@@ -60,19 +56,21 @@ int usb_cpu_init(void)
 
 int usb_cpu_stop(void)
 {
+	at91_pmc_t *pmc	= (at91_pmc_t *)AT91_PMC_BASE;
+
 	/* Disable USB host clock. */
-	at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
+	writel(1 << AT91_ID_UHP, &pmc->pcdr);
 #ifdef CONFIG_AT91SAM9261
-	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0);
+	writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr);
 #else
-	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
+	writel(AT91_PMC_UHP, &pmc->scdr);
 #endif
 
 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
     defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
 	/* Disable PLLB */
-	at91_sys_write(AT91_CKGR_PLLBR, 0);
-	while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0)
+	writel(0, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
 		;
 #endif
 
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 680fe33..5b1a85d 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -108,11 +108,12 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_PCKRDY3		0x00000800
 
 #ifdef CONFIG_AT91_LEGACY
-
 #define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
 #define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
 
 #define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
+#endif
+
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -128,27 +129,34 @@ typedef struct at91_pmc {
 #define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
 #define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
 
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
 #define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
 #define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
 
 #define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [SAM9RL, CAP9] */
+#endif
+
 #define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
 #define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
 #define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
 #define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
 
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
+#endif
 #define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
 #define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
+#endif
 #define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
 #define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
 #define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
+#endif
 #define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
 #define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
 #define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
@@ -160,7 +168,9 @@ typedef struct at91_pmc {
 #define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
 #define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
 
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
+#endif
 #define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
 #define			AT91_PMC_CSS_SLOW		(0 << 0)
 #define			AT91_PMC_CSS_MAIN		(1 << 0)
@@ -188,11 +198,13 @@ typedef struct at91_pmc {
 #define			AT91_PMC_PDIV_1			(0 << 12)
 #define			AT91_PMC_PDIV_2			(1 << 12)
 
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
 
 #define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
 #define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
 #define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
+#endif
 #define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
 #define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
 #define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
@@ -203,12 +215,13 @@ typedef struct at91_pmc {
 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
 #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
+#ifdef CONFIG_AT91_LEGACY
 #define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
 
 #define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
+#endif
 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
-
+#ifdef CONFIG_AT91_LEGACY
 #define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
-
 #endif /* CONFIG_AT91_LEGACY */
 #endif