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| author | Anson Huang <b20788@freescale.com> | 2012-10-15 18:21:27 -0400 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-10-16 15:06:12 -0400 |
| commit | d6ff40e31c8f8dcdeba646e931e97aa1c7c74ed0 (patch) | |
| tree | b74a3e9df7a5f77d2d8d405d7d50dd36a6a9dfa7 | |
| parent | 17d38b4648c2212472d76a6c02a966c54917b435 (diff) | |
| download | u-boot-imx-d6ff40e31c8f8dcdeba646e931e97aa1c7c74ed0.zip u-boot-imx-d6ff40e31c8f8dcdeba646e931e97aa1c7c74ed0.tar.gz u-boot-imx-d6ff40e31c8f8dcdeba646e931e97aa1c7c74ed0.tar.bz2 | |
ENGR00229614 mx6: disable VDDPU by default, xpu will enable it if needed.
Disable VDDPU_CAP by default, xPU will enable it
in driver when they need it.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | cpu/arm_cortexa8/mx6/generic.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index 6a98d04..a3d965c 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -100,6 +100,9 @@ enum pll_clocks { #define NFC_CLK_MAX PLL2_FREQ_MAX #endif +#define GPC_PGC_GPU_PGCR_OFFSET 0x260 +#define GPC_CNTR_OFFSET 0x0 + #define OCOTP_THERMAL_OFFSET 0x4E0 #define TEMPERATURE_MIN -40 #define TEMPERATURE_HOT 80 @@ -1013,10 +1016,19 @@ int arch_cpu_init(void) #ifndef CONFIG_L2_OFF l2_cache_enable(); #endif + /* Need to power down xPU in GPC before turn off PU LDO */ + val = readl(GPC_BASE_ADDR + GPC_PGC_GPU_PGCR_OFFSET); + writel(val | 0x1, GPC_BASE_ADDR + GPC_PGC_GPU_PGCR_OFFSET); + + val = readl(GPC_BASE_ADDR + GPC_CNTR_OFFSET); + writel(val | 0x1, GPC_BASE_ADDR + GPC_CNTR_OFFSET); + while (readl(GPC_BASE_ADDR + GPC_CNTR_OFFSET) & 0x1) + ; - /* Increase the VDDSOC to 1.2V */ + /* Increase the VDDSOC to 1.2V and disable VDDPU */ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE); val &= ~BM_ANADIG_REG_CORE_REG2_TRG; + val &= ~BM_ANADIG_REG_CORE_REG1_TRG; val |= BF_ANADIG_REG_CORE_REG2_TRG(0x14); REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val); |