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authorMarek Vasut <marex@denx.de>2014-08-04 01:47:09 +0200
committerStefano Babic <sbabic@denx.de>2014-08-20 12:21:57 +0200
commitfcfdfdd58c67dbade1bafb48e393be2f432be33a (patch)
tree044770d229f62e24132990e5cc32baf4ab20a5d8
parent68968901e79f91a2516ffa091959d0378526f838 (diff)
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ARM: mx6: Prevent overflow in DRAM size detection
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but only 3840 MiB of that can be really used. In case the controller is configured to operate a 4GiB module, the imx_ddr_size() function will correctly compute that there is 4GiB of DRAM in the system. Firstly, the return value is 32-bit, so the function will effectively return zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB of all that. Thus, clamp the returned size to 3840MiB in such case. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
-rw-r--r--arch/arm/imx-common/cpu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 7bb0e83..ed826a0 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -93,6 +93,11 @@ unsigned imx_ddr_size(void)
bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
bits += ESD_MMDC_CTL_GET_CS1(ctl);
+
+ /* The MX6 can do only 3840 MiB of DRAM */
+ if (bits == 32)
+ return 0xf0000000;
+
return 1 << bits;
}
#endif