summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSimon Glass <sjg@chromium.org>2016-01-17 16:11:19 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-01-24 12:08:16 +0800
commitf633efa30f6119c9cecb045e7edeb01554800d84 (patch)
tree6978ca15c37a273fc6f36d12f06df423e3f06cf0
parent2b27d205290b43418c7f51026915782551f03e6b (diff)
downloadu-boot-imx-f633efa30f6119c9cecb045e7edeb01554800d84.zip
u-boot-imx-f633efa30f6119c9cecb045e7edeb01554800d84.tar.gz
u-boot-imx-f633efa30f6119c9cecb045e7edeb01554800d84.tar.bz2
x86: ivybridge: Probe the LPC in CPU init
We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-rw-r--r--arch/x86/cpu/ivybridge/cpu.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index f32b4a1..65eea1f 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -212,7 +212,7 @@ int print_cpuinfo(void)
{
enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
char processor_name[CPU_MAX_NAME_LEN];
- struct udevice *dev;
+ struct udevice *dev, *lpc;
const char *name;
uint32_t pm1_cnt;
uint16_t pm1_sts;
@@ -245,12 +245,11 @@ int print_cpuinfo(void)
/* Early chipset init required before RAM init can work */
uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
- ret = uclass_first_device(UCLASS_PCH, &dev);
+ ret = uclass_first_device(UCLASS_LPC, &lpc);
if (ret)
return ret;
if (!dev)
return -ENODEV;
-
sandybridge_early_init(SANDYBRIDGE_MOBILE);
/* Check PM1_STS[15] to see if we are waking from Sx */