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authorDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-01-09 17:32:50 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-01-16 21:06:46 +0100
commitf53830e74ede7c15740e13d9620dafb335c522ce (patch)
tree253d2714fca0ec2dabbfe22d29f050d804099a93
parent0c7fd8f4660ed612db5d9e9343f77edfe5af090b (diff)
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MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-rw-r--r--arch/mips/Kconfig21
-rw-r--r--arch/mips/include/asm/cache.h14
2 files changed, 25 insertions, 10 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 388e4c0..1b39c4c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -28,6 +28,7 @@ config TARGET_MALTA
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SWAP_IO_SPACE
+ select MIPS_L1_CACHE_SHIFT_6
config TARGET_VCT
bool "Support vct"
@@ -196,6 +197,26 @@ config SWAP_IO_SPACE
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config MIPS_L1_CACHE_SHIFT_4
+ bool
+
+config MIPS_L1_CACHE_SHIFT_5
+ bool
+
+config MIPS_L1_CACHE_SHIFT_6
+ bool
+
+config MIPS_L1_CACHE_SHIFT_7
+ bool
+
+config MIPS_L1_CACHE_SHIFT
+ int
+ default "7" if MIPS_L1_CACHE_SHIFT_7
+ default "6" if MIPS_L1_CACHE_SHIFT_6
+ default "5" if MIPS_L1_CACHE_SHIFT_5
+ default "4" if MIPS_L1_CACHE_SHIFT_4
+ default "5"
+
endif
endmenu
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 0dfb54e..806bd26 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -7,15 +7,9 @@
#ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__
-/*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 128
-#endif
+#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
#endif /* __MIPS_CACHE_H__ */