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| author | Ye Li <ye.li@nxp.com> | 2017-04-13 11:40:46 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-14 11:11:19 +0800 |
| commit | e72f766c98a3df9b620feb51484e33c7d50bed3c (patch) | |
| tree | 2ff7ba7fee806e25393e91cc147e1081f14a88e6 | |
| parent | 636b19ace1205d82947eaa57958cd311e92edcf2 (diff) | |
| download | u-boot-imx-e72f766c98a3df9b620feb51484e33c7d50bed3c.zip u-boot-imx-e72f766c98a3df9b620feb51484e33c7d50bed3c.tar.gz u-boot-imx-e72f766c98a3df9b620feb51484e33c7d50bed3c.tar.bz2 | |
MLK-14689 mx7ulp: Workaround APLL PFD2 to 345.6Mhz
The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1.
This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz.
So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem.
The correct fix should let GPU handle the clock rate in kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e931d534fd68e0e639082766de17a20e705fd908)
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c index d0453d3..4db35e7 100644 --- a/arch/arm/cpu/armv7/mx7ulp/clock.c +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -302,9 +302,9 @@ void clock_init(void) scg_a7_soscdiv_init(); - /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ + /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); - scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20); + scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); init_clk_lpuart(); |