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authorPeng Fan <Peng.Fan@freescale.com>2015-06-11 18:30:36 +0800
committerStefano Babic <sbabic@denx.de>2015-06-27 18:18:40 +0200
commitdfd4861c22389066e37d104ddfb925321231f876 (patch)
tree9276b950dfb1c10678802ef484f20a575eb6c02c
parentb65d9d868efcae5bf40377deafc60a968f78e55c (diff)
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imx: mx6 correct get_cpu_rev
The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor | We also need to account for Major Lower. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index b21bd03..29de624 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(&anatop->digprog_sololite);
u32 type = ((reg >> 16) & 0xff);
+ u32 major;
if (type != MXC_CPU_MX6SL) {
reg = readl(&anatop->digprog);
@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
}
}
+ major = ((reg >> 8) & 0xff);
reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
+ return (type << 12) | (reg + (0x10 * (major + 1)));
}
/*