IGEP0146: Initial commit

Structure folders
defconfig
initial ram config
only UART will be configured for basic printf

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

14 files changed, 946 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 14d46ff..6b68168 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -153,12 +153,19 @@ config TARGET_GW_VENTANA
 
 config TARGET_IGEP0046
 	bool "Support IMX6 igep0046"
-	select CPU_V7
 	select DM
 	select DM_THERMAL
 	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 
+config TARGET_IGEP0146
+	bool "Support IMX6 igep0146"
+	select DM
+	select DM_THERMAL
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+
 config TARGET_KOSAGI_NOVENA
 	bool "Kosagi Novena"
 	select BOARD_LATE_INIT
@@ -511,6 +518,7 @@ source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/isee/igep0046/Kconfig"
+source "board/isee/igep0146/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
 source "board/liebherr/mccmon6/Kconfig"
diff --git a/board/isee/common/igep_eeprom.c b/board/isee/common/igep_eeprom.c
new file mode 100644
index 0000000..ff2e4e2
--- /dev/null
+++ b/board/isee/common/igep_eeprom.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * EEPROM support source file for IGEP0046 board
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/sys_proto.h>
+
+
+int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size)
+{
+    u32 i;
+    u32 remain = size % 32;
+    u32 blocks = size / 32;
+    for (i=0; i < blocks; i++){
+        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
+            return -1;
+        }
+        udelay(5000);
+    }
+    if(remain > 0){
+        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
+            return -1;
+        else
+            udelay(5000);
+    }
+    return 0;
+}
+
+int eeprom_read_setup (uint8_t s_addr, char* data, u32 size)
+{
+    u32 i;
+    u32 remain = size % 32;
+    u32 blocks = size / 32;
+    for (i=0; i < blocks; i++){
+        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
+            return -1;
+        }
+    }
+    if(remain > 0)
+        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
+            return -1;
+    return 0;
+}
+
+int check_eeprom (void)
+{
+    i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+    /* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		printf("Could not probe the EEPROM at 0x%x\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return -1;
+	}
+	return 0;
+}
diff --git a/board/isee/common/igep_eeprom.h b/board/isee/common/igep_eeprom.h
new file mode 100644
index 0000000..db56247
--- /dev/null
+++ b/board/isee/common/igep_eeprom.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * 0046 EEPROM Definitions
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EEPROM_BOARD_HELPER__
+#define __EEPROM_BOARD_HELPER__
+
+int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size);
+int eeprom_read_setup (uint8_t s_addr, char* data, u32 size);
+int check_eeprom (void);
+#endif
diff --git a/board/isee/igep0146/Kconfig b/board/isee/igep0146/Kconfig
new file mode 100644
index 0000000..69496fd
--- /dev/null
+++ b/board/isee/igep0146/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IGEP0146
+
+config SYS_BOARD
+	default "igep0146"
+
+config SYS_VENDOR
+	default "isee"
+
+config SYS_CONFIG_NAME
+	default "igep0146"
+
+endif
diff --git a/board/isee/igep0146/MAINTAINERS b/board/isee/igep0146/MAINTAINERS
new file mode 100644
index 0000000..4f06e15
--- /dev/null
+++ b/board/isee/igep0146/MAINTAINERS
@@ -0,0 +1,6 @@
+IGEP0046 BOARD
+M:	Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+S:	Maintained
+F:	board/isee/igep0146/igep0146.c
+F:	include/configs/igep0146.h
+F:	configs/mx6ul_igep0146_512M_defconfig
diff --git a/board/isee/igep0146/Makefile b/board/isee/igep0146/Makefile
new file mode 100644
index 0000000..7cab156
--- /dev/null
+++ b/board/isee/igep0146/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  += igep0146.o
diff --git a/board/isee/igep0146/igep0146.c b/board/isee/igep0146/igep0146.c
new file mode 100644
index 0000000..da7a348
--- /dev/null
+++ b/board/isee/igep0146/igep0146.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * Source file for IGEP0046 board
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <malloc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx6/sys_proto.h>
+#include <asm/io.h>
+#include "../common/igep_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MACRO MUX defines */
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define GPIO_LED_PAD_CTRL  (PAD_CTL_PUS_22K_UP |	\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_SRE_FAST )
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = imx_ddr_size();
+}
+
+/* UART MUX */
+static iomux_v3_cfg_t const uart3_pads[] =
+{
+	MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const led_pads[] = {
+	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
+};
+
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+static void setup_iomux_leds(void)
+{
+	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
+}
+
+
+int checkboard(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_leds();
+	
+	/* configure LEDS */
+	gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
+	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+
+	return 0;
+}
+
+int board_init(void)
+{
+
+	return 0;	
+}
+
+
+int board_late_init(void)
+{	
+	checkboard();
+	puts("\n");
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+	return;
+}
+#endif
\ No newline at end of file
diff --git a/board/isee/igep0146/igep0146_eeprom.c b/board/isee/igep0146/igep0146_eeprom.c
new file mode 100644
index 0000000..33bf1f3
--- /dev/null
+++ b/board/isee/igep0146/igep0146_eeprom.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * EEPROM support source file for IGEP0046 board
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/sys_proto.h>
+
+
+int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
+{
+    u32 i;
+    u32 remain = size % 32;
+    u32 blocks = size / 32;
+    for (i=0; i < blocks; i++){
+        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
+            return -1;
+        }
+        udelay(5000);
+    }
+    if(remain > 0){
+        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
+            return -1;
+        else
+            udelay(5000);
+    }
+    return 0;
+}
+
+int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
+{
+    u32 i;
+    u32 remain = size % 32;
+    u32 blocks = size / 32;
+    for (i=0; i < blocks; i++){
+        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
+            return -1;
+        }
+    }
+    if(remain > 0)
+        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
+            return -1;
+    return 0;
+}
+
+int check_eeprom (void)
+{
+    i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+    /* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		printf("Could not probe the EEPROM at 0x%x\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return -1;
+	}
+	return 0;
+}
diff --git a/board/isee/igep0146/igep0146_eeprom.h b/board/isee/igep0146/igep0146_eeprom.h
new file mode 100644
index 0000000..0ed4f37
--- /dev/null
+++ b/board/isee/igep0146/igep0146_eeprom.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * 0046 EEPROM Definitions
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EEPROM_BOARD_HELPER__
+#define __EEPROM_BOARD_HELPER__
+
+int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
+int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
+int check_eeprom (void);
+#endif
diff --git a/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg b/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg
new file mode 100644
index 0000000..e36084c
--- /dev/null
+++ b/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* New DDR type MT41K64M16TW-107 */
+
+//=============================================================================			
+// Enable all clocks (they are disabled by ROM code)			
+//=============================================================================	
+
+DATA 4 0x020c4068 0xffffffff    // CCM_CCGR0
+DATA 4 0x020c406c 0xffffffff    // CCM_CCGR1
+DATA 4 0x020c4070 0xffffffff    // CCM_CCGR2
+DATA 4 0x020c4074 0xffffffff    // CCM_CCGR3
+DATA 4 0x020c4078 0xffffffff    // CCM_CCGR4
+DATA 4 0x020c407c 0xffffffff    // CCM_CCGR5
+DATA 4 0x020c4080 0xffffffff    // CCM_CCGR6
+
+//=============================================================================			
+// IOMUX IMX6UL - MCIMX6G3CV
+//=============================================================================
+
+//DDR IO TYPE:				
+DATA 4 0x020E04B4 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+DATA 4 0x020E04AC 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+
+//CLOCK:			
+DATA 4 0x020E027C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
+
+//ADDRESS:
+DATA 4 0x020E0250 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B			
+DATA 4 0x020E024C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
+DATA 4 0x020E0490 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS
+
+//Control:
+DATA 4 0x020E0288 0x000C0030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET			
+DATA 4 0x020E0270 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+DATA 4 0x020E0260 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
+DATA 4 0x020E0264 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
+DATA 4 0x020E04A0 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS
+
+//Data Strobes:
+DATA 4 0x020E0494 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL			
+DATA 4 0x020E0280 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
+DATA 4 0x020E0284 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
+
+//Data:
+DATA 4 0x020E04B0 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+DATA 4 0x020E0498 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS
+DATA 4 0x020E04A4 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS
+
+DATA 4 0x020E0244 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+DATA 4 0x020E0248 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+
+//=============================================================================			
+// DDR Controller Registers			
+//=============================================================================			
+// Manufacturer:	Micron		
+// Device Part Number:  MT41K64M16TW-107		
+// Clock Freq.: 933 MHz	IMX6UL ensures data capture margin up to 400 Mhz	
+// Density per CS in Gb: 1 Gb		
+// Chip Selects used:	1		
+// Number of Banks:	8		
+// Row address:    	13		
+// Column address: 	10		
+// Data bus width	16		
+//=============================================================================
+
+DATA 4 0x021B001C 0x00008000    // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
+			
+//=============================================================================			
+// Calibration setup.	REVISAR		
+//=============================================================================	
+
+DATA 4 0x021B0800 0xA1390003	// MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
+
+// For target board, may need to run write leveling calibration to fine tune these settings.			
+DATA 4 0x021B080C 0x00000000	// MMDC_MPWLDECTRL0
+
+// Read DQS Gating calibration
+DATA 4 0x021B083C 0x415C015C	// MMDC_MPDGCTRL0
+
+// Read Calibration
+DATA 4 0x021B0848 0x40404040	// MMDC_MPRDDLCTL 0x40404244
+
+// Write Calibration
+DATA 4 0x021B0850 0x40404040	// MMDC_MPWRDLCTL 0x40405A58
+
+// Read Data bit delay
+DATA 4 0x021B081C 0x33333333	// MMDC_MPRDDQBY0DL
+DATA 4 0x021B0820 0x33333333	// MMDC_MPRDDQBY1DL
+DATA 4 0x021B082C 0xf3333333	// MMDC_MPWRDQBY0DL
+DATA 4 0x021B0830 0xf3333333	// MMDC_MPWRDQBY1DL
+
+// Control Duty Cicle DQS of and primary clock CK0
+DATA 4 0x021B08C0 0x24922492	// MMDC_MPDCCR 0x00921012 24922492 0x00921012
+
+// Complete Calibration by Forced Measurement
+DATA 4 0x021B08b8 0x00008000    // MMDC_MPMUR0
+
+//=============================================================================			
+// Calibration setup end			
+//=============================================================================	
+
+// MMCD Init
+DATA 4 0x021B0004 0x00020036	// MMDC_MDPDC 
+DATA 4 0x021B0008 0x1B333030	// MMDC_MDOTC 
+DATA 4 0x021B000C 0x676B52F3	// MMDC_MDCFG0 
+DATA 4 0x021B0010 0xB66D0B63    // MMDC_MDCFG1
+DATA 4 0x021B0014 0x01FF00DB	// MMDC_MDCFG2
+
+//MDMISC: RALAT kept to the high level of 5. 			
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			
+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			
+//b. Small performence improvment 
+DATA 4 0x021B0018 0x00201740	// MMDC_MDMISC
+DATA 4 0x021B001C 0x00000800    // MMDC_MDSCR
+DATA 4 0x021B002C 0x000026D2	// MMDC_MDRWD
+DATA 4 0x021B0030 0x006B1023	// MMDC_MDOR
+DATA 4 0x021B0040 0x0000004F	// MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
+DATA 4 0x021B0000 0x82180000	// MMDC_MDCTL
+
+// ????
+DATA 4 0x021B0890 0x00400000	// MMDC_MPPDCMPR2 DDR2 Only ???
+
+// Mode Register writes
+// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
+DATA 4 0x021B001C 0x02008032    // MMDC0_MDSCR, MR2 write, CS0
+DATA 4 0x021B001C 0x00008033	// MMDC0_MDSCR, MR3 write, CS0
+DATA 4 0x021B001C 0x00048031	// MMDC0_MDSCR, MR1 write, CS0
+DATA 4 0x021B001C 0x15208030	// MMDC0_MDSCR, MR0write, CS0
+DATA 4 0x021B001C 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
+
+
+DATA 4 0x021B0020 0x00000800    // MMDC0_MDREF
+
+DATA 4 0x021B0818 0x00000227	// DDR_PHY_P0_MPODTCTRL
+
+DATA 4 0x021B0004 0x0002552D	// MMDC0_MDPDC
+
+DATA 4 0x021B0404 0x00011006	// MMDC0_MAPSR
+
+DATA 4 0x021B001C 0x00000000	// MMDC0_MDSCR
diff --git a/board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg b/board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg
new file mode 100644
index 0000000..aff2a2e
--- /dev/null
+++ b/board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* DDR type MT41K256M16TW-107 */
+
+//=============================================================================			
+// Enable all clocks (they are disabled by ROM code)			
+//=============================================================================	
+
+DATA 4 0x020c4068 0xffffffff    // CCM_CCGR0
+DATA 4 0x020c406c 0xffffffff    // CCM_CCGR1
+DATA 4 0x020c4070 0xffffffff    // CCM_CCGR2
+DATA 4 0x020c4074 0xffffffff    // CCM_CCGR3
+DATA 4 0x020c4078 0xffffffff    // CCM_CCGR4
+DATA 4 0x020c407c 0xffffffff    // CCM_CCGR5
+DATA 4 0x020c4080 0xffffffff    // CCM_CCGR6
+
+//=============================================================================			
+// IOMUX IMX6UL - MCIMX6G3CV
+//=============================================================================
+
+//DDR IO TYPE:				
+DATA 4 0x020E04B4 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+DATA 4 0x020E04AC 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+
+//CLOCK:			
+DATA 4 0x020E027C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
+
+//ADDRESS:
+DATA 4 0x020E0250 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B			
+DATA 4 0x020E024C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
+DATA 4 0x020E0490 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS
+
+//Control:
+DATA 4 0x020E0288 0x000C0030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET			
+DATA 4 0x020E0270 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+DATA 4 0x020E0260 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
+DATA 4 0x020E0264 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
+DATA 4 0x020E04A0 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS
+
+//Data Strobes:
+DATA 4 0x020E0494 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL			
+DATA 4 0x020E0280 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
+DATA 4 0x020E0284 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
+
+//Data:
+DATA 4 0x020E04B0 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+DATA 4 0x020E0498 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS
+DATA 4 0x020E04A4 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS
+
+DATA 4 0x020E0244 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+DATA 4 0x020E0248 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+
+//=============================================================================			
+// DDR Controller Registers			
+//=============================================================================			
+// Manufacturer:	Micron		
+// Device Part Number:  MT41K256M16TW-107		
+// Clock Freq.: 933 MHz	IMX6UL ensures data capture margin up to 400 Mhz	
+// Density per CS in Gb: 4 Gb		
+// Chip Selects used:	1		
+// Number of Banks:	8		
+// Row address:		15		
+// Column address:	10		
+// Data bus width	16		
+//=============================================================================
+
+DATA 4 0x021B001C 0x00008000    // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
+			
+//=============================================================================			
+// Calibration setup.	REVISAR		
+//=============================================================================	
+
+DATA 4 0x021B0800 0xA1390003	// MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
+
+// For target board, may need to run write leveling calibration to fine tune these settings.			
+DATA 4 0x021B080C 0x00000000	// MMDC_MPWLDECTRL0
+
+// Read DQS Gating calibration
+DATA 4 0x021B083C 0x00000000	// MMDC_MPDGCTRL0
+
+// Read Calibration
+DATA 4 0x021B0848 0x40404040	// MMDC_MPRDDLCTL 0x40404244
+
+// Write Calibration
+DATA 4 0x021B0850 0x40404040	// MMDC_MPWRDLCTL 0x40405A58
+
+// Read Data bit delay
+DATA 4 0x021B081C 0x33333333	// MMDC_MPRDDQBY0DL
+DATA 4 0x021B0820 0x33333333	// MMDC_MPRDDQBY1DL
+DATA 4 0x021B082C 0xf3333333	// MMDC_MPWRDQBY0DL
+DATA 4 0x021B0830 0xf3333333	// MMDC_MPWRDQBY1DL
+
+// Control Duty Cicle DQS of and primary clock CK0
+DATA 4 0x021B08C0 0x24922492	// MMDC_MPDCCR 0x00921012 24922492 0x00921012
+
+// Complete Calibration by Forced Measurement
+DATA 4 0x021B08b8 0x00008000    // MMDC_MPMUR0
+
+//=============================================================================			
+// Calibration setup end			
+//=============================================================================	
+
+// MMCD Init
+DATA 4 0x021B0004 0x00020036	// MMDC_MDPDC 
+DATA 4 0x021B0008 0x00333030	// MMDC_MDOTC 
+DATA 4 0x021B000C 0x676B52F3	// MMDC_MDCFG0 
+DATA 4 0x021B0010 0xB66D0B63    // MMDC_MDCFG1
+DATA 4 0x021B0014 0x01FF00DB	// MMDC_MDCFG2
+
+//MDMISC: RALAT kept to the high level of 5.	
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			
+//b. Small performence improvment 
+DATA 4 0x021B0018 0x00201740	// MMDC_MDMISC
+DATA 4 0x021B001C 0x00000800    // MMDC_MDSCR
+DATA 4 0x021B002C 0x000026D2	// MMDC_MDRWD
+DATA 4 0x021B0030 0x006B1023	// MMDC_MDOR
+DATA 4 0x021B0040 0x0000003F	// MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
+DATA 4 0x021B0000 0x84180000	// MMDC_MDCTL
+
+// ????
+DATA 4 0x021B0890 0x00400000	// MMDC_MPPDCMPR2 DDR2 Only ???
+
+// Mode Register writes
+// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
+DATA 4 0x021B001C 0x02008032    // MMDC0_MDSCR, MR2 write, CS0
+DATA 4 0x021B001C 0x00008033	// MMDC0_MDSCR, MR3 write, CS0
+DATA 4 0x021B001C 0x00048031	// MMDC0_MDSCR, MR1 write, CS0
+DATA 4 0x021B001C 0x15208030	// MMDC0_MDSCR, MR0write, CS0
+DATA 4 0x021B001C 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
+
+
+DATA 4 0x021B0020 0x00000800    // MMDC0_MDREF
+
+DATA 4 0x021B0818 0x00000227	// DDR_PHY_P0_MPODTCTRL
+
+DATA 4 0x021B0004 0x0002556D	// MMDC0_MDPDC
+
+DATA 4 0x021B0404 0x00011006	// MMDC0_MAPSR
+
+DATA 4 0x021B001C 0x00000000	// MMDC0_MDSCR
diff --git a/board/isee/igep0146/mxul_igep0146_prcarlos.cfg b/board/isee/igep0146/mxul_igep0146_prcarlos.cfg
new file mode 100644
index 0000000..0ae8b0b
--- /dev/null
+++ b/board/isee/igep0146/mxul_igep0146_prcarlos.cfg
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN  board/freescale/mx6sxsabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000020
+DATA 4 0x020e02fc 0x00000020
+DATA 4 0x020e05f4 0x00000020
+
+/* Control */
+DATA 4 0x020e0340 0x00000020
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000020
+DATA 4 0x020e0314 0x00000020
+DATA 4 0x020e0614 0x00000020
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00220022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x41480144
+DATA 4 0x021b0840 0x01340130
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x3C3E4244
+DATA 4 0x021b0850 0x34363638
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b001c 0x00000000
+#endif
diff --git a/configs/igep0146_imx6ul_512M_defconfig b/configs/igep0146_imx6ul_512M_defconfig
new file mode 100644
index 0000000..2ba0418
--- /dev/null
+++ b/configs/igep0146_imx6ul_512M_defconfig
@@ -0,0 +1,16 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0146/mxul_igep0146_prcarlos.cfg,MX6UL"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_MX6UL=y
+CONFIG_TARGET_IGEP0146=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
+CONFIG_DISPLAY_BOARDINFO=y
\ No newline at end of file
diff --git a/include/configs/igep0146.h b/include/configs/igep0146.h
new file mode 100644
index 0000000..15f1718
--- /dev/null
+++ b/include/configs/igep0146.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * Header file for IGEP0046 board
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_IGEP0046_H
+#define __CONFIG_IGEP0046_H
+
+#include "mx6_common.h"	
+
+
+#define CONFIG_SECURE_BOOT
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+#define CONFIG_SYS_FSL_SEC_COMPAT    4 /* HAB version */
+#define CONFIG_FSL_CAAM
+#define CONFIG_SYS_FSL_SEC_LE
+
+/* Falcon Mode */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x88000000
+#define CONFIG_CMD_SPL_WRITE_SIZE      (128 * SZ_1K)
+
+/* Falcon Mode - RAW MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+#endif
+
+/* CPU */
+#define CONFIG_IMX_THERMAL
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* UART Configs */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART3_BASE
+#define CONSOLE_DEV					"ttymxc1"
+#define CONFIG_BAUDRATE				115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+/* Physical Memory Map */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Begin and End Address of simple memory test */
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x80800000
+
+
+/* Miscellaneous configurable options */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Press ESC to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR "\x1b"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* MMC Configs */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FAT_WRITE
+
+
+/* NET Configs */
+#define CONFIG_ENV_OVERWRITE		/* To allow write MAC into ethaddr variable */
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(128 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+/* Commands */
+#undef 	CONFIG_CMD_IMLS
+#define EMMC_ENV ""
+#define VIDEO_ARGS ""
+#define VIDEO_ARGS_SCRIPT ""
+
+
+#endif                         /* __IGEP0046_CONFIG_H */
+
+
+
+
+
+
+